WO2002062118A1 - A stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same - Google Patents

A stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same Download PDF

Info

Publication number
WO2002062118A1
WO2002062118A1 PCT/US2002/002276 US0202276W WO02062118A1 WO 2002062118 A1 WO2002062118 A1 WO 2002062118A1 US 0202276 W US0202276 W US 0202276W WO 02062118 A1 WO02062118 A1 WO 02062118A1
Authority
WO
WIPO (PCT)
Prior art keywords
microcircuit
pem
modified
bond
bond pad
Prior art date
Application number
PCT/US2002/002276
Other languages
French (fr)
Inventor
Douglas M. Albert
Keith D. Gann
Original Assignee
Irvine Sensors Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Irvine Sensors Corporation filed Critical Irvine Sensors Corporation
Priority to JP2002562134A priority Critical patent/JP2004523902A/en
Priority to EP02705988.0A priority patent/EP1360882B1/en
Publication of WO2002062118A1 publication Critical patent/WO2002062118A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/98—Methods for disconnecting semiconductor or solid-state bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81052—Detaching bump connectors, e.g. after testing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Definitions

  • This invention relates generally to the dense packaging of electronic circuitry through the stacking of integrated circuit (IC) chips (aka microcircuits or die) and, more specifically, to a stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same
  • IC integrated circuit
  • stacking of IC chips has emphasized use of identical- area chips, each of which performs the same function.
  • the resulting stack is a rectangular parallelepiped (or cube) having substantially planar outer surfaces.
  • One or more of the outer surfaces is an access plane, reached by electrical leads from the IC circuitry of the stacked chips, in order to permit connection to external circuitry.
  • Irvine Sensors was initially "stacking silicon" by (1) buying whole silicon wafers from a wafer manufacturer, (2) metalizing an upper surface of the wafer to connect each die's bond pads to an edge that will later be formed when the die is diced from the wafer; (3) dicing stackable die from the metallized wafer; (4) stacking the stackable die to form die-stacks, and then (5) forming edge connections on one or more sides of each die stack.
  • Irvine Sensors found it troublesome to make die stacks by stacking silicon die, however, for several reason.
  • the edge connects on the die stacks because they must be made within the dicing streets that have grown continually narrower as dicing technologies have improved.
  • the typical dicing street may be 6 mils or less and the saw kerf may be about 1.5 mils with poor registration relative to the die.
  • a die's original metallization may be undesirably exposed to the edge and thereby make it troublesome to form further access plane metallization along that edge without shorting.
  • Neo-Die Stacking As a result of the foregoing problems associated with silicon die stacking, Irvine Sensors developed new technology involved creating "Neo- Wafers” and then stacking "Neo-Chips” diced from the Neo-Wafers.
  • Irvine Sensors has two patents that relate to "Neo-Wafers" and "Neo-Chips", i.e. U.S. Patent No. 5,953,588 entitled “STACKABLE LAYERS CONTAINING ENCAPSULATED IC CHIPS” and U.S. Patent No. 6,072,234 entitled “STACK OF EQUAL LAYER NEO-CHIPS CONTAINING ENCAPSULATED IC CHIPS OF DIFFERENT SIZES.” The content of these two patents are hereby incorporated by reference in their entirety.
  • Neo-Wafer As disclosed more fully in the foregoing patents, the inventors make a "Neo-Wafer” by (1) buying bare die (preferably pre-tested or "known good” die); (2) arranging the bare die in a spaced arrangement within a wafer- shaped fixture; and then (3) pouring a potting material such as epoxy onto the bare die within the wafer-shaped fixture.
  • the Neo-Wafers after being removed from the fixture, are surface metalized and the potted die are cut from the Neo-Wafers to provide "Neo-Chips" of equal area that are suitable for stacking.
  • a significant benefit of Neo-Wafer and Neo-Chips is that know good die may be used and different sized and number of die may be incorporated into same sized Neo-Chips.
  • Neo-stacking offers significant improvements over silicon die stacking, but it also proved troublesome under certain market circumstances. In particular, it is often difficult to buy bare die because many manufacturers will only sell only packaged die. When trying to buy bare DRAM die from a particular manufacturer, for example, it was discovered that the manufacturer would not sell bare DRAM die, but would sell the DRAM die already pre-tested and installed in plastic packages, i.e. as "plastic encapsulated microcircuits" or PEMs. The existing stacking methodologies, however, do not address the stacking of die contained in a plastic encapsulated microcircuit.
  • the invention may be regarded as a method of making a stackable microcircuit layer comprising the steps of: providing a plastic encapsulated microcircuit (PEM) that includes (a) a microcircuit having an active surface containing integrated circuitry and a bond pad, and (b) an encapsulant in contact with the microcircuit; and modifying the PEM to produce a modified PEM having a modified surface on which modified surface is exposed a conductive member that is electrically connected to the bond pad.
  • PEM plastic encapsulated microcircuit
  • the invention may be regarded as a method of making a stackable microcircuit layer comprising the steps of: providing a plastic encapsulated microcircuit (PEM) that includes: (a) a microcircuit having a bond pad, (b) a conductive lead assembly connected to the bond pad, and (c) a plastic body encapsulating the microcircuit, the bond pad, and at least part of the conductive lead assembly; and grinding a top surface of the PEM to remove a top portion of the plastic body along with at least part of the conductive lead assembly to leave a planar section that contains the microcircuit and the bond pad.
  • PEM plastic encapsulated microcircuit
  • the invention may be regarded as a method of
  • a plastic encapsulated microcircuit that includes (a) a microcircuit having an active surface containing integrated circuitry and a bond pad, (b) a wire bond connected to the bond pad, a lead frame, and a wire that connects the wire bond to the lead frame, and (d) a plastic body that encapsulates the known-good microcircuit, the wire bond, the wire, and at least a portion of the lead frame; grinding a surface of the PEM to remove the lead frame and the wire and form a modified PEM that contains the microcircuit, the bond pad, and the wire bond, the modified PEM having a modified surface on which modified surface is exposed the wire bond that is connected to the bond pad; and forming an electrical lead on the modified surface that leads from the wire bond to an edge of the modified PEM.
  • PEM plastic encapsulated microcircuit
  • the invention may be regarded as a stackable microcircuit layer comprising: (1) a modified section of a plastic encapsulated microcircuit (PEM) that originally contained (a) a known-good microcircuit having a bond pad, (b) a conductive lead assembly connected to the bond pad, and (c) a plastic body encapsulating the known-good microcircuit, the bond pad, and the conductive lead assembly, the modified section formed by removing a portion of the conductive lead assembly from the PEM; the modified section having a modified surface, the modified section containing the known-good microcircuit, the bond pad, and a remaining portion of the conductive lead assembly with an end thereof exposed on the modified surface; and (2) a reroute lead on the modified surface of the modified section to connect the exposed portion of the remaining portion of conductive lead assembly with an edge of the modified section.
  • PEM plastic encapsulated microcircuit
  • Figure 1 is a perspective view of a die 210 that may be incorporated in a stackable microcircuit layer according to a preferred embodiment of this invention, the die 210 having an active surface 211 and a plurality its I/O bond pads 212 ;
  • Figure 2 is a perspective view of a plastic encapsulated microcircuit 300 provided as a 54-pin Thin Small Outline Package ("TSOP") that is formed from an encapsulant 310 that contains a die (not shown here, but see Figure 3) connected to a lead frame having lead tips 272;
  • Figure 3 is a perspective view of the PEM 300 of Figure 2 showing the die 210 (dashed lines) and a lead frame 270 encapsulated therein;
  • TSOP Thin Small Outline Package
  • Figures 4a to 4f are cross-sectional views that illustrate the steps of a preferred method of modifying a PEM 300 to first form a modified PEM 400 and ultimately to form a stackable microcircuit layer 400* where, in particular,
  • Figure 4a is a cross-sectional view of the PEM 300 of Figure 3, taken along section lines 4-4, showing the internal die 210 and a conductive lead assembly 230 contained inside of the encapsulant 310;
  • Figure 4b shows a modified PEM 400 formed by grinding a topside of the PEM 300 of Figure 4a until the lead frame 270 is removed and the gold ball bonds 231 are exposed;
  • Figure 4c shows the modified PEM 400 after application of metallization 241 that connects the die's bond pad 212, via the gold ball bonds 231 , with an edge 411 of the modified PEM 400;
  • Figure 4d shows the modified PEM 400 after application of an insulating layer 250
  • Figure 4e shows the modified PEM 400 after backside thinning
  • Figure 4f shows the final stackable microcircuit layer 400 * that is formed by reducing the area (if desired) of the modified PEM 400 of Figure 4e along the dashed lines;
  • Figure 5 shows a stack 450 of stackable microcircuit layers 400*, including a cap chip 451 that is electrically connected to metallization formed along an access plane of the stack;
  • FIG. 6 is a perspective view of a plastic encapsulated microcircuit 600 provided as a Plastic Ball Grid Array (PBGA) package that is formed from an encapsulant 610 that contains a die 510 (dashed lines) that is electrically connected (not shown) to a plurality of solder ball terminals 536 arranged in a grid pattern;
  • PBGA Plastic Ball Grid Array
  • Figures 7a to7d are cross-sectional views that illustrate the steps of a second preferred method of modifying a PEM, in this case a uBGA (micro Ball Grid Array) package 600, in order to form a modified PEM 700 and ultimately to form a stackable microcircuit layer 700* where, in particular, a uBGA (micro Ball Grid Array) package 600, in order to form a modified PEM 700 and ultimately to form a stackable microcircuit layer 700* where, in particular,
  • uBGA micro Ball Grid Array
  • Figure 7a is an inverted, cross-sectional view of the PEM 600 of Figure 3 (simplified to show only two solder ball terminals 536), showing the internal die 510 and a conductive lead assembly 530 that is contained inside of the encapsulant 610;
  • Figure 7b shows a modified PEM 700 formed by removing the solder ball terminals 536 such that one end 534 of a flexible lead beam 531 is exposed;
  • Figure 7c shows the modified PEM 700 after application of metallization 541 that connects the die's bond pad 512, via the flexible lead beam 531 that has one end 533 in contact with the bond pad 512 and another end 534 exposed to the metallization 543, with an edge 711 of the modified PEM 700;
  • Figure 7d shows the final stackable microcircuit layer 700* that is formed after application of an insulating layer 550 (there is thinning or reduction in area as in Figures 4e and 4f above because the uBGA was thin and chip scale to begin with);
  • Figure 8 shows a stack 750 of stackable microcircuit layers
  • cap chip 751 that is electrically connected to metallization formed along an access plane of the stack.
  • bare die have been potted in special fixtures in order to create stackable microcircuit layers known as "neo-chips".
  • bare die are not always available and even when they are, the manufacture's testing is often limited to statistical "pass/fail” verifications using parametric measurements and suitable guard bands.
  • the present invention is directed to creating stackable microcircuit layers in a novel "reverse” manner, i.e. by starting with plastic encapsulated microcircuits (PEMs) or, in other words, by starting with already packaged die.
  • PEMs plastic encapsulated microcircuits
  • PEMs are readily available for purchase in the marketplace.
  • the die contained in the PEMs are usually pre- tested and fully burned-in by the manufacturer.
  • Figure 1 shows, by way of background, a die 210 that includes an active surface 211 containing integrated circuitry and a plurality of bond pads 212.
  • wires are bonded to the bond pads 212 in order to provide power, communicate control signals, and the like, to and from the circuitry via the leads of a package that suitably contains the die 210.
  • the bond pads 212 are arranged in a straight line down the center of the die 210, but the actual arrangement of bond pads may vary. Dies like that shown in Figure 1 are carried in all varieties of packages, two of which are discussed below.
  • Preferred Embodiment - TSOP Package Figure 2 shows a typical plastic encapsulated microcircuit (PEM) 300 that is formed from a plastic, injection molded encapsulant 310 and may be used to practice this invention.
  • the particular PEM 300 of Figure 2 is a 54-pin TSOP (Thin Small Outline Package) that has a plurality of leads 272 extending from the encapsulant 310. It should be understood, however, that there are a wide variety of conventional and "chip-scale" package designs that already exist or may be later designed that may be used according to this invention.
  • Figure 3 shows that the die 210 is encapsulated inside of the PEM 300.
  • the die's bond pads 212 are electrically connected to a lead frame 270 that is encapsulated along with the die 210 while providing the leads 272 that extend from the PEM's encapsulant 310.
  • Figures 4a to 4f are cross-sectional views that illustrate the steps of a preferred method of modifying the PEM 300 of Figure 3 to first form a modified PEM 400 and ultimately to form a stackable microcircuit layer 400*.
  • a first embodiment of the herein disclosed method of making a stackable microcircuit layer 400 * comprising the steps of: providing a PEM 300 that includes (a) a microcircuit 210 having an active surface 211 containing integrated circuitry and a bond pad 212, and (b) an encapsulant 310 in contact with the microcircuit 210; and modifying the PEM 300 to produce a modified PEM 400 having a modified surface on which modified surface is exposed a conductive member (e.g. a section of the ball bond 231 or a section of the wire 232) that is electrically connected to the bond pad 212.
  • Figure 4a in more detail, is a cross-sectional view of the PEM
  • the conductive lead assembly 230 in this particular PEM 300 was formed by using a lead frame adhesive 320 (typically, in the case of a TSOP, a polymide adhesive layer that is located on either side of the bond pads 212) to secure a lead frame 270 above the die 210.
  • a thermosonic ball bond process was used to connect the bond pads 212 to the lead frame 270.
  • a plurality of wires 232 are connected from each bond pad 212 to a corresponding portion of the lead frame 270 by first forming a gold ball 231 at one end of the wire 232, ultrasonically bonding the gold ball 231 to the bond pad 212, and then compressing the other end of the wire 212 to the lead frame 270 to form a so- called "crescent bond" on the lead frame.
  • the PEM's encapsulant 310 usually formed in an injection molding process, surrounds the die 210 and includes an upper portion 311 that covers the conductive lead assembly 230 (gold ball 231 , wire 232, and lead frame 270).
  • Figure 4b relates to modifying the PEM 300, here by grinding or top thinning. Other alternatives could be used, of course, such as wet etching, dry etching as with a plasma, hand lapping with a diamond paste, and so on.
  • Figure 4b shows a first preferred method of modifying the PEM 300 to form a modified PEM 400.
  • the PEM 300 is ground from the top through the lead frame 270
  • this modifying step is accomplished by grinding a topside of the PEM 300 of Figure 4a in order to remove the lead frame 270, in order to expose an upper surface of the lead frame adhesive 320 that once secured the lead frame 270, and in order to expose a conductive member that is electrically connected to the bond pad 212 (e.g. a section of the wire 232 and/or a section of the gold ball bond 231).
  • the presently preferred method of grinding involves using a
  • Strausbaugh wafer grinder with the PEM mounted on a blank dummy wafer but different grinding methods may be used.
  • Figure 4c relates to adding reroute metal by forming an electrical lead 241 on the modified surface of the modified PEM 400.
  • Figure 4c shows the modified PEM 400 after application of metallization 241 that connects the die's bond pad 212, via the gold ball bond 231 , with an edge 411 of the modified PEM 400.
  • the processes used to lay down the reroute metaliization are well known.
  • One such process involves sputtering on a field layer of metal, applying an emulsion and processing it to define the desired pattern; and then etching away the undesired portions of the field layer to leave only the desired metallization.
  • the reroute metallization may be applied to each modified PEM 400, one at a time, or to several at a time by establishing a suitable gang processing procedure. It should be noted that in some applications it may be possible to retain the original lead frame 270 and not apply new reroute metal 24. This is particularly true for memory stacking applications where the access plane connections on the side of the stack are highly bused.
  • Figure 4d relates to adding an insulating layer 250 that covers the electrical reroute lead 241.
  • Figure 4d shows the modified PEM 400 after application of an insulating layer 250.
  • the preferred insulating layer 250 is a polyimide that is spun on or sprayed on as desired.
  • Figure 4e relates to an optional back thinning step.
  • Figure 4e shows the modified PEM 400 after such backside thinning.
  • Backside thinning is particular desirable in the case of a TSOP because it makes the ultimate stackable microcircuit layer 400* thinner (about 10 mils in thickness), because it removes plastic that would otherwise be thermally insulative, and because it allow for tighter height tolerance that may prevent tolerance runout when connecting to separate electrically isolated leads in a stack of the microcircuit layers 400 * .
  • Figure 4f relates to an optionally reducing the area of the modified PEM 500 by, in this case, dicing.
  • Figure 4f shows the final stackable microcircuit layer 400* that is formed by dicing the modified PEM 400 of Figure 4e along the dashed lines.
  • the stackable microcircuit layer 400* is comparable to a Neo-Chip except that here the die 210 was provided as part of a PEM 300 and was likely burned-in by the manufacturer and here the die 210 is surrounded by a portion of the encapsulant 310 that was part of the original PEM 300 rather than by an after-added potting material such as epoxy.
  • Figure 5 shows a typical stack 450 that may be formed from several stackable microcircuit layers 400*, including a cap chip 451 that provides interface pads that are electrically connected to metallization 453 that is formed along an access plane of the stack 450 in order to provide so- called "t-connections" with the reroute metallization 241 (or original lead frames) of the individual layers 400*.
  • the preferred cap chip 451 is a printed circuit board, but it could be made from any suitable insulator (e.g. ceramic) that can be processed to provide the required via holes (not separately numbered).
  • the stack is homogenous, but it is also possible, of course, to produce stacks of equal or unequal area layers that contain different sized and differently numbers of die.
  • a stackable • microcircuit layer 400* may itself be further potted, alone or with other die, to create a neo-chip of greater area or enhanced capability.
  • Figure 6 in particular, is a perspective view of a plastic
  • encapsulated microcircuit 600 provided as a micro-Ball Grid Array ( ⁇ BGA) package that is formed from an encapsulant 610 that contains a die 510 (dashed lines) that is electrically connected (not shown) to a plurality of solder ball terminals 536 arranged in a grid pattern on a bottom side of the package
  • ⁇ BGA micro-Ball Grid Array
  • Figure 7a is our starting place in that it shows an inverted, cross- sectional view of the PEM 600 of Figure 3 (simplified to show only two solder ball terminals 536).
  • Figure 7a shows that the die 510 and the conductive lead assembly 530 are contained inside of the encapsulant 610. There are some important differences, however, relative to the TSOP PEM 300.
  • the ⁇ BGA PEM 600 includes a flexible lead beam 531 that is supported on an elastomeric pad 620 having one end adhered to the bond pad 512 and another end in contact with a deposited solder ball 536.
  • the flexible lead beam 531 is typically formed from a conductive trace provided on a flexible substrate such as a polyimide film.
  • a succession of insulating layers 631 are provided in the original manufacture of the PEM 600.
  • Figure 7b like Figure 4b, relates to modifying the PEM.
  • the modifying is not accomplished by grinding or top thinning, but rather by removing at least a portion of the solder balls 536.
  • the removing of at least a portion of the solder ball is accomplished by heating the solder ball to form molten solder and wicking away the molten solder. It may also be possible to remove a portion of the solder balls 536 through a mechanical shearing operation.
  • Figure 7b shows a modified PEM 700 formed by removing the solder balls 536 such that one end 534 of a flexible lead beam 531 is exposed;
  • Figure 7c like Figure 4c, relates to adding reroute metal by forming an electrical lead 541 on the modified surface of the modified PEM 700.
  • Figure 7c shows the modified PEM 700 after application of reroute metallization 541 that connects the die's bond pad 512, via the flexible lead beam 531 that has one end 533 in contact with the bond pad 512 and another end 534 exposed to the metallization 543, with an edge 711 of the modified PEM 700; and
  • Figure 7d like Figure 4d, relates to adding an insulating layer 550 that covers the electrical reroute lead 541. At this point, the result is the final stackable microcircuit layer 700*. There is no need for back thinning or reduction in area as in Figures 4e and 4f above because the uBGA was thin and chip scale to begin.
  • Figure 8 shows a typical stack 750 that may be formed from several stackable microcircuit layers 700*, including a cap chip 751 that provides interface pads that are electrically connected to metallization 753 that is formed along an access plane of the stack 750 in order to provide so- called "t-connections" with the reroute metallization 541 of the individual layers 700*.
  • Figure 8 is comparable to Figure 5.
  • the stack 750 is shows as homogenous, but it is also possible, of course, to produce a stack of equal or unequal area layers that contain different sized and differently numbers of die. It should also be noted that a stackable microcircuit layer 700* may itself be further potted, alone or with other die, to create a neo-chip of greater area or enhanced capability. From the foregoing description, it will be apparent that the method and apparatus disclosed in this application will provide the significant functional benefits summarized in the introductory portion of the specification.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A stackable microcircuit layer formed from a plastic encapsulated microcircuit (PEM) and a method of making the PEM by providing PEM contains a microcircuit (210) with in an encapsulant (310) and modifying the PEM to expose conductive members (270) which is connected to the microcircuit's bonding pads (212), reroute metallization is applied to connect the conductive members (270) which exposed by grinding to an edge of the modified PEM (300) stacking to form an a assembly (450).

Description

A Stackable Microcircuit Layer Formed From a Plastic Encapsulated Microcircuit and Method of Making the Same
BACKGROUND OF THE INVENTION
Field of the Invention This invention relates generally to the dense packaging of electronic circuitry through the stacking of integrated circuit (IC) chips (aka microcircuits or die) and, more specifically, to a stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same
Description of the Related Art
A publication titled "Three-Dimensional Electronics Packaging" was issued in November, 1993 by Tech Search International. It describes the 3-D packaging techniques offered by over thirty manufacturers. It includes a table comparing 23 types of packaging in terms of density, manufacturability, flexibility and affordability. The publication also refers to four types of 3-D stacking techniques, one of which is "bare die stacking". It then divides "bare die assembly into standard ICS" and "custom ICs". The assignee of this application, Irvine Sensors Corporation, has been a leader in developing high density packaging of IC chips, originally for use in focal plane modules, and then for use in a variety of computer functions, such as memory. In the publication cited in the preceding paragraph, Irvine Sensors is listed as a developer of "bare die assemblies" using "custom ICs".
Generally, stacking of IC chips has emphasized use of identical- area chips, each of which performs the same function. The resulting stack is a rectangular parallelepiped (or cube) having substantially planar outer surfaces. One or more of the outer surfaces is an access plane, reached by electrical leads from the IC circuitry of the stacked chips, in order to permit connection to external circuitry.
An early effort to provide a 3-D electronics stack combining different functions, different area electronic chips is illustrated by Kravitz et al., U.S. Patent No. 3,370,203. That patent shows stacked "frames" having dimensions "such that integrated circuits which have slightly different dimensions can be mounted thereon", explaining that "integrated circuits from different sources of supply are often advantageously incorporated in a single module". Irvine Sensors' experience with various stacking methods has evolved over time:
Silicon Die Stacking
Irvine Sensors was initially "stacking silicon" by (1) buying whole silicon wafers from a wafer manufacturer, (2) metalizing an upper surface of the wafer to connect each die's bond pads to an edge that will later be formed when the die is diced from the wafer; (3) dicing stackable die from the metallized wafer; (4) stacking the stackable die to form die-stacks, and then (5) forming edge connections on one or more sides of each die stack. Irvine Sensors found it troublesome to make die stacks by stacking silicon die, however, for several reason.
First, it was difficult to buy whole wafers because the wafer manufacturers do not want to reveal their yield or expose their built-in test structures that would make it easier to reverse engineer their circuitry, because the manufacturers do not usually have an existing sales structure for selling whole wafers, and because the manufacturers were concerned about liability issues if the stacked product should come to include a defective die.
Second, it was sometimes difficult to form the edge connects on the die stacks because they must be made within the dicing streets that have grown continually narrower as dicing technologies have improved. For example, the typical dicing street may be 6 mils or less and the saw kerf may be about 1.5 mils with poor registration relative to the die. As a result, a die's original metallization may be undesirably exposed to the edge and thereby make it troublesome to form further access plane metallization along that edge without shorting.
Third, the probability of having a defective die in any one die-stack increases dramatically on the basis of the number of wafers in the wafer stack. Finally, silicon stacking inherently requires same sized or
homogenous die sizes.
Neo-Die Stacking As a result of the foregoing problems associated with silicon die stacking, Irvine Sensors developed new technology involved creating "Neo- Wafers" and then stacking "Neo-Chips" diced from the Neo-Wafers.
Irvine Sensors has two patents that relate to "Neo-Wafers" and "Neo-Chips", i.e. U.S. Patent No. 5,953,588 entitled "STACKABLE LAYERS CONTAINING ENCAPSULATED IC CHIPS" and U.S. Patent No. 6,072,234 entitled "STACK OF EQUAL LAYER NEO-CHIPS CONTAINING ENCAPSULATED IC CHIPS OF DIFFERENT SIZES." The content of these two patents are hereby incorporated by reference in their entirety.
As disclosed more fully in the foregoing patents, the inventors make a "Neo-Wafer" by (1) buying bare die (preferably pre-tested or "known good" die); (2) arranging the bare die in a spaced arrangement within a wafer- shaped fixture; and then (3) pouring a potting material such as epoxy onto the bare die within the wafer-shaped fixture. The Neo-Wafers, after being removed from the fixture, are surface metalized and the potted die are cut from the Neo-Wafers to provide "Neo-Chips" of equal area that are suitable for stacking. A significant benefit of Neo-Wafer and Neo-Chips is that know good die may be used and different sized and number of die may be incorporated into same sized Neo-Chips. Neo-stacking offers significant improvements over silicon die stacking, but it also proved troublesome under certain market circumstances. In particular, it is often difficult to buy bare die because many manufacturers will only sell only packaged die. When trying to buy bare DRAM die from a particular manufacturer, for example, it was discovered that the manufacturer would not sell bare DRAM die, but would sell the DRAM die already pre-tested and installed in plastic packages, i.e. as "plastic encapsulated microcircuits" or PEMs. The existing stacking methodologies, however, do not address the stacking of die contained in a plastic encapsulated microcircuit.
There remains a need, therefore, for a stackable microcircuit layer formed from a plastic encapsulated microcircuit and a method of making the same.
SUMMARY OF THE INVENTION
In a first aspect, the invention may be regarded as a method of making a stackable microcircuit layer comprising the steps of: providing a plastic encapsulated microcircuit (PEM) that includes (a) a microcircuit having an active surface containing integrated circuitry and a bond pad, and (b) an encapsulant in contact with the microcircuit; and modifying the PEM to produce a modified PEM having a modified surface on which modified surface is exposed a conductive member that is electrically connected to the bond pad. In a second aspect, the invention may be regarded as a method of making a stackable microcircuit layer comprising the steps of: providing a plastic encapsulated microcircuit (PEM) that includes: (a) a microcircuit having a bond pad, (b) a conductive lead assembly connected to the bond pad, and (c) a plastic body encapsulating the microcircuit, the bond pad, and at least part of the conductive lead assembly; and grinding a top surface of the PEM to remove a top portion of the plastic body along with at least part of the conductive lead assembly to leave a planar section that contains the microcircuit and the bond pad. In a third aspect, the invention may be regarded as a method of
• making a stackable microcircuit layer comprising the steps of: providing a plastic encapsulated microcircuit (PEM) that includes (a) a microcircuit having an active surface containing integrated circuitry and a bond pad, (b) a wire bond connected to the bond pad, a lead frame, and a wire that connects the wire bond to the lead frame, and (d) a plastic body that encapsulates the known-good microcircuit, the wire bond, the wire, and at least a portion of the lead frame; grinding a surface of the PEM to remove the lead frame and the wire and form a modified PEM that contains the microcircuit, the bond pad, and the wire bond, the modified PEM having a modified surface on which modified surface is exposed the wire bond that is connected to the bond pad; and forming an electrical lead on the modified surface that leads from the wire bond to an edge of the modified PEM.
In a fourth aspect, the invention may be regarded as a stackable microcircuit layer comprising: (1) a modified section of a plastic encapsulated microcircuit (PEM) that originally contained (a) a known-good microcircuit having a bond pad, (b) a conductive lead assembly connected to the bond pad, and (c) a plastic body encapsulating the known-good microcircuit, the bond pad, and the conductive lead assembly, the modified section formed by removing a portion of the conductive lead assembly from the PEM; the modified section having a modified surface, the modified section containing the known-good microcircuit, the bond pad, and a remaining portion of the conductive lead assembly with an end thereof exposed on the modified surface; and (2) a reroute lead on the modified surface of the modified section to connect the exposed portion of the remaining portion of conductive lead assembly with an edge of the modified section.
BRIEF DESCRIPTION OF THE DRAWINGS
The just summarized invention can be best understood with reference to the following description taken in view of the drawings of which: Figure 1 is a perspective view of a die 210 that may be incorporated in a stackable microcircuit layer according to a preferred embodiment of this invention, the die 210 having an active surface 211 and a plurality its I/O bond pads 212 ; Figure 2 is a perspective view of a plastic encapsulated microcircuit 300 provided as a 54-pin Thin Small Outline Package ("TSOP") that is formed from an encapsulant 310 that contains a die (not shown here, but see Figure 3) connected to a lead frame having lead tips 272; Figure 3 is a perspective view of the PEM 300 of Figure 2 showing the die 210 (dashed lines) and a lead frame 270 encapsulated therein;
Figures 4a to 4f are cross-sectional views that illustrate the steps of a preferred method of modifying a PEM 300 to first form a modified PEM 400 and ultimately to form a stackable microcircuit layer 400* where, in particular,
Figure 4a is a cross-sectional view of the PEM 300 of Figure 3, taken along section lines 4-4, showing the internal die 210 and a conductive lead assembly 230 contained inside of the encapsulant 310;
Figure 4b shows a modified PEM 400 formed by grinding a topside of the PEM 300 of Figure 4a until the lead frame 270 is removed and the gold ball bonds 231 are exposed; Figure 4c shows the modified PEM 400 after application of metallization 241 that connects the die's bond pad 212, via the gold ball bonds 231 , with an edge 411 of the modified PEM 400;
Figure 4d shows the modified PEM 400 after application of an insulating layer 250; Figure 4e shows the modified PEM 400 after backside thinning; and
Figure 4f shows the final stackable microcircuit layer 400* that is formed by reducing the area (if desired) of the modified PEM 400 of Figure 4e along the dashed lines; Figure 5 shows a stack 450 of stackable microcircuit layers 400*, including a cap chip 451 that is electrically connected to metallization formed along an access plane of the stack;
Figure 6 is a perspective view of a plastic encapsulated microcircuit 600 provided as a Plastic Ball Grid Array (PBGA) package that is formed from an encapsulant 610 that contains a die 510 (dashed lines) that is electrically connected (not shown) to a plurality of solder ball terminals 536 arranged in a grid pattern;
Figures 7a to7d are cross-sectional views that illustrate the steps of a second preferred method of modifying a PEM, in this case a uBGA (micro Ball Grid Array) package 600, in order to form a modified PEM 700 and ultimately to form a stackable microcircuit layer 700* where, in particular,
Figure 7a is an inverted, cross-sectional view of the PEM 600 of Figure 3 (simplified to show only two solder ball terminals 536), showing the internal die 510 and a conductive lead assembly 530 that is contained inside of the encapsulant 610;
Figure 7b shows a modified PEM 700 formed by removing the solder ball terminals 536 such that one end 534 of a flexible lead beam 531 is exposed; Figure 7c shows the modified PEM 700 after application of metallization 541 that connects the die's bond pad 512, via the flexible lead beam 531 that has one end 533 in contact with the bond pad 512 and another end 534 exposed to the metallization 543, with an edge 711 of the modified PEM 700; and Figure 7d shows the final stackable microcircuit layer 700* that is formed after application of an insulating layer 550 (there is thinning or reduction in area as in Figures 4e and 4f above because the uBGA was thin and chip scale to begin with); and Figure 8 shows a stack 750 of stackable microcircuit layers
700*, including a cap chip 751that is electrically connected to metallization formed along an access plane of the stack.
DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS In the past, bare die have been potted in special fixtures in order to create stackable microcircuit layers known as "neo-chips". Unfortunately, bare die are not always available and even when they are, the manufacture's testing is often limited to statistical "pass/fail" verifications using parametric measurements and suitable guard bands. The present invention, however, is directed to creating stackable microcircuit layers in a novel "reverse" manner, i.e. by starting with plastic encapsulated microcircuits (PEMs) or, in other words, by starting with already packaged die. There are two significant benefits to starting with PEMs. First, PEMs are readily available for purchase in the marketplace. Second, the die contained in the PEMs are usually pre- tested and fully burned-in by the manufacturer.
Figure 1 shows, by way of background, a die 210 that includes an active surface 211 containing integrated circuitry and a plurality of bond pads 212. Ordinarily, wires are bonded to the bond pads 212 in order to provide power, communicate control signals, and the like, to and from the circuitry via the leads of a package that suitably contains the die 210. Here, the bond pads 212 are arranged in a straight line down the center of the die 210, but the actual arrangement of bond pads may vary. Dies like that shown in Figure 1 are carried in all varieties of packages, two of which are discussed below.
Preferred Embodiment - TSOP Package Figure 2 shows a typical plastic encapsulated microcircuit (PEM) 300 that is formed from a plastic, injection molded encapsulant 310 and may be used to practice this invention. The particular PEM 300 of Figure 2 is a 54-pin TSOP (Thin Small Outline Package) that has a plurality of leads 272 extending from the encapsulant 310. It should be understood, however, that there are a wide variety of conventional and "chip-scale" package designs that already exist or may be later designed that may be used according to this invention.
As visually suggested by mentally moving the die 210 of Figure 1 into the PEM 300 of Figure 2, Figure 3 shows that the die 210 is encapsulated inside of the PEM 300. In this particular case, the die's bond pads 212 are electrically connected to a lead frame 270 that is encapsulated along with the die 210 while providing the leads 272 that extend from the PEM's encapsulant 310.
Figures 4a to 4f are cross-sectional views that illustrate the steps of a preferred method of modifying the PEM 300 of Figure 3 to first form a modified PEM 400 and ultimately to form a stackable microcircuit layer 400*. As shown in such figures, a first embodiment of the herein disclosed method of making a stackable microcircuit layer 400* comprising the steps of: providing a PEM 300 that includes (a) a microcircuit 210 having an active surface 211 containing integrated circuitry and a bond pad 212, and (b) an encapsulant 310 in contact with the microcircuit 210; and modifying the PEM 300 to produce a modified PEM 400 having a modified surface on which modified surface is exposed a conductive member (e.g. a section of the ball bond 231 or a section of the wire 232) that is electrically connected to the bond pad 212. Figure 4a, in more detail, is a cross-sectional view of the PEM
300 of Figure 3, taken along section lines 4-4, showing the internal die 210 and a conductive lead assembly 230 contained inside of the encapsulant 310. The conductive lead assembly 230 in this particular PEM 300 was formed by using a lead frame adhesive 320 (typically, in the case of a TSOP, a polymide adhesive layer that is located on either side of the bond pads 212) to secure a lead frame 270 above the die 210. In this particular case, moreover, a thermosonic ball bond process was used to connect the bond pads 212 to the lead frame 270. The precise manner of connection is not relevant to the present invention, but generally, as is well known in the art, a plurality of wires 232 are connected from each bond pad 212 to a corresponding portion of the lead frame 270 by first forming a gold ball 231 at one end of the wire 232, ultrasonically bonding the gold ball 231 to the bond pad 212, and then compressing the other end of the wire 212 to the lead frame 270 to form a so- called "crescent bond" on the lead frame. As further shown in Figure 4a, the PEM's encapsulant 310, usually formed in an injection molding process, surrounds the die 210 and includes an upper portion 311 that covers the conductive lead assembly 230 (gold ball 231 , wire 232, and lead frame 270). Figure 4b relates to modifying the PEM 300, here by grinding or top thinning. Other alternatives could be used, of course, such as wet etching, dry etching as with a plasma, hand lapping with a diamond paste, and so on. Figure 4b, in particular, shows a first preferred method of modifying the PEM 300 to form a modified PEM 400. Here, the PEM 300 is ground from the top through the lead frame 270 In other words, this modifying step is accomplished by grinding a topside of the PEM 300 of Figure 4a in order to remove the lead frame 270, in order to expose an upper surface of the lead frame adhesive 320 that once secured the lead frame 270, and in order to expose a conductive member that is electrically connected to the bond pad 212 (e.g. a section of the wire 232 and/or a section of the gold ball bond 231). The presently preferred method of grinding involves using a
Strausbaugh wafer grinder with the PEM mounted on a blank dummy wafer, but different grinding methods may be used.
Figure 4c relates to adding reroute metal by forming an electrical lead 241 on the modified surface of the modified PEM 400. Figure 4c, in particular, shows the modified PEM 400 after application of metallization 241 that connects the die's bond pad 212, via the gold ball bond 231 , with an edge 411 of the modified PEM 400. The processes used to lay down the reroute metaliization are well known. One such process, for example, involves sputtering on a field layer of metal, applying an emulsion and processing it to define the desired pattern; and then etching away the undesired portions of the field layer to leave only the desired metallization. The reroute metallization may be applied to each modified PEM 400, one at a time, or to several at a time by establishing a suitable gang processing procedure. It should be noted that in some applications it may be possible to retain the original lead frame 270 and not apply new reroute metal 24. This is particularly true for memory stacking applications where the access plane connections on the side of the stack are highly bused.
Figure 4d relates to adding an insulating layer 250 that covers the electrical reroute lead 241. Figure 4d, in particular, shows the modified PEM 400 after application of an insulating layer 250. The preferred insulating layer 250 is a polyimide that is spun on or sprayed on as desired.
Figure 4e relates to an optional back thinning step. Figure 4e, in particular, shows the modified PEM 400 after such backside thinning. Backside thinning is particular desirable in the case of a TSOP because it makes the ultimate stackable microcircuit layer 400* thinner (about 10 mils in thickness), because it removes plastic that would otherwise be thermally insulative, and because it allow for tighter height tolerance that may prevent tolerance runout when connecting to separate electrically isolated leads in a stack of the microcircuit layers 400*.
Figure 4f relates to an optionally reducing the area of the modified PEM 500 by, in this case, dicing. Figure 4f, in particular, shows the final stackable microcircuit layer 400* that is formed by dicing the modified PEM 400 of Figure 4e along the dashed lines. At this point, the stackable microcircuit layer 400* is comparable to a Neo-Chip except that here the die 210 was provided as part of a PEM 300 and was likely burned-in by the manufacturer and here the die 210 is surrounded by a portion of the encapsulant 310 that was part of the original PEM 300 rather than by an after-added potting material such as epoxy.
Figure 5 shows a typical stack 450 that may be formed from several stackable microcircuit layers 400*, including a cap chip 451 that provides interface pads that are electrically connected to metallization 453 that is formed along an access plane of the stack 450 in order to provide so- called "t-connections" with the reroute metallization 241 (or original lead frames) of the individual layers 400*. The preferred cap chip 451 is a printed circuit board, but it could be made from any suitable insulator (e.g. ceramic) that can be processed to provide the required via holes (not separately numbered). Here, the stack is homogenous, but it is also possible, of course, to produce stacks of equal or unequal area layers that contain different sized and differently numbers of die. It should also be noted that a stackable • microcircuit layer 400* may itself be further potted, alone or with other die, to create a neo-chip of greater area or enhanced capability.
Alternative Embodiment - uBGA Package
As suggested above, the present invention may be practiced with different types of packages and is not limited to plastic TSOPs. In order to illustrate this concept, the inventors also contemplate modifying a μBGA package in order to produce a stackable microcircuit layer. Figure 6, in particular, is a perspective view of a plastic
encapsulated microcircuit 600 provided as a micro-Ball Grid Array (μBGA) package that is formed from an encapsulant 610 that contains a die 510 (dashed lines) that is electrically connected (not shown) to a plurality of solder ball terminals 536 arranged in a grid pattern on a bottom side of the package
The application of the present invention to a PEM 600 in the form of a μBGA Package is illustrated by Figures Figures 7a to 7d.
Figure 7a is our starting place in that it shows an inverted, cross- sectional view of the PEM 600 of Figure 3 (simplified to show only two solder ball terminals 536). Figure 7a shows that the die 510 and the conductive lead assembly 530 are contained inside of the encapsulant 610. There are some important differences, however, relative to the TSOP PEM 300.
The precise manufacture of the μBGA PEM 600 is well known, but a few observations as to its finished structure may help as related to this invention. Unlike the TSOP discussed above, the encapsulant 610 more closely conforms to the area of the die 510 (i.e. it is a "chip scale" package) and an inactive surface of the die 510 is exposed. The conductive lead assembly 530 also differs from that found in a TSOP. In particular, the μBGA PEM 600 includes a flexible lead beam 531 that is supported on an elastomeric pad 620 having one end adhered to the bond pad 512 and another end in contact with a deposited solder ball 536. The flexible lead beam 531 is typically formed from a conductive trace provided on a flexible substrate such as a polyimide film. A succession of insulating layers 631 are provided in the original manufacture of the PEM 600. Figure 7b, like Figure 4b, relates to modifying the PEM. Here, however, the modifying is not accomplished by grinding or top thinning, but rather by removing at least a portion of the solder balls 536. In the preferred embodiment, the removing of at least a portion of the solder ball is accomplished by heating the solder ball to form molten solder and wicking away the molten solder. It may also be possible to remove a portion of the solder balls 536 through a mechanical shearing operation. Figure 7b shows a modified PEM 700 formed by removing the solder balls 536 such that one end 534 of a flexible lead beam 531 is exposed; Figure 7c, like Figure 4c, relates to adding reroute metal by forming an electrical lead 541 on the modified surface of the modified PEM 700. Figure 7c, in particular, shows the modified PEM 700 after application of reroute metallization 541 that connects the die's bond pad 512, via the flexible lead beam 531 that has one end 533 in contact with the bond pad 512 and another end 534 exposed to the metallization 543, with an edge 711 of the modified PEM 700; and
Figure 7d, like Figure 4d, relates to adding an insulating layer 550 that covers the electrical reroute lead 541. At this point, the result is the final stackable microcircuit layer 700*. There is no need for back thinning or reduction in area as in Figures 4e and 4f above because the uBGA was thin and chip scale to begin.
Figure 8 shows a typical stack 750 that may be formed from several stackable microcircuit layers 700*, including a cap chip 751 that provides interface pads that are electrically connected to metallization 753 that is formed along an access plane of the stack 750 in order to provide so- called "t-connections" with the reroute metallization 541 of the individual layers 700*. Figure 8, of course, is comparable to Figure 5.
As noted before, the stack 750 is shows as homogenous, but it is also possible, of course, to produce a stack of equal or unequal area layers that contain different sized and differently numbers of die. It should also be noted that a stackable microcircuit layer 700* may itself be further potted, alone or with other die, to create a neo-chip of greater area or enhanced capability. From the foregoing description, it will be apparent that the method and apparatus disclosed in this application will provide the significant functional benefits summarized in the introductory portion of the specification.
The following claims are intended not only to cover the specific embodiments disclosed, but also to cover the inventive concepts explained herein with the maximum breadth and comprehensiveness permitted by the prior art.

Claims

What Is Claimed Is:
1. A method of making a stackable microcircuit layer comprising the steps of: providing a plastic encapsulated microcircuit (PEM) that includes (a) a microcircuit having an active surface containing integrated circuitry and a bond pad, and (b) an encapsulant in contact with the microcircuit; and modifying the PEM to produce a modified PEM having a modified surface on which modified surface is exposed a conductive member that is electrically connected to the bond pad.
2. The method of Claim 1 further comprising the step of forming an electrical lead on the modified surface of the modified PEM that leads from the conductive member to an edge of the modified PEM
3. The method of Claiml wherein the microcircuit is a pretested microcircuit.
4. The method of Claim 1 wherein the microcircuit is a burned-in microcircuit.
5. The method of Claim 2 wherein the modifying step is accomplished through grinding.
6. The method of Claim 2 comprising the further step of covering the electrical lead with an insulating layer.
7. The method of Claim 1 comprising the further step of reducing the thickness of the modified PEM by thinning a backside of the modified PEM that is opposite to the electrical lead.
8. The method of Claim 7 wherein the step of reducing the thickness of the modified PEM by thinning a back side of the modified PEM is accomplished through grinding.
9. The method of Claim 1 comprising the further step of reducing the area of the modified PEM.
10. The method of Claim 9 wherein the further step reducing the area of the modified PEM is accomplished by sawing the modified PEM along one or more edges.
11. The method of Claim 1 wherein the conductive member that electrically connects to the bond pad is part of a wire bond.
12. The method of Claim 11 wherein the conductive member is
a gold ball bond.
13. The method of Claim 11 wherein the conductive member is a wire.
14. The method of Claim 11 wherein the conductive member is a wedge bond.
15. The method ofClaim 11 wherein the conductive member is a lead frame.
16. The method of Claim 1 wherein the conductive member that electrically connects to the bond pad is a conductive trace on a flexible substrate.
17. The method of Claim 16 wherein the conductive trace is a flexible lead beam and the flexible substrate is a polyimide film.
18. The method of Claim 1 wherein the PEM's encapsulant is a plastic body that at least partially encapsulates the microcircuit.
19. The method of Claim 18 wherein the conductive member that is electrically connected to the bond pad is encapsulated in the plastic body of the PEM and wherein the modifying step comprises thinning a first side of the PEM to expose the conductive member.
20. The method of Claim 19 wherein the PEM comprises a thin small outline package (TSOP) containing a gold ball bond, a lead frame, and a wire that are collectively encapsulated in the plastic body of the PEM, wherein the gold ball bond is formed on the bond pad, wherein the wire connects the gold ball bond to the lead frame, and wherein the gold ball bond is the conductive member exposed on the modified surface of the modified PEM through thinning.
21. The method of Claim 20 wherein the thinning removes the lead frame and the wire along with a portion of the plastic body.
22. The method of Claim 18 wherein the PEM comprises a uBGA package that includes a polyimide film and a flexible lead beam that are collectively encapsulated in the plastic body, wherein one end of the flexible lead beam is connected to the bond pad, and wherein a solder ball is deposited onto an exterior side of the polyimide film in contact with an opposite second end of the flexible lead beam.
23. The method of Claim 22 wherein the modifying step comprises removing at least a portion of the solder ball.
24. The method of Claim 23 wherein the removing of at least a portion of the solder ball is accomplished by heating the solder ball to form molten solder and wicking away the molten solder.
25. The method of Claim 24 wherein the he removing of at least a portion of the solder ball is accomplished by shearing.
26. A method of making a stackable microcircuit layer
comprising the steps of: providing a plastic encapsulated microcircuit (PEM) that
includes:
(a) a microcircuit having a bond pad,
(b) a conductive lead assembly connected to the bond pad, and
(c) a plastic body encapsulating the microcircuit, the bond pad, and at least part of the conductive lead assembly; and grinding a top surface of the PEM to remove a top portion of the plastic body along with at least part of the conductive lead assembly to leave a planar section that contains the microcircuit and the bond pad.
27. The method of Claim 26 further comprising the step of forming an electrical lead on top of the planar section which leads from the bond pad of the microcircuit to at least one edge of the planar section.
28. The method of Claim 26 wherein the grinding step also leaves a vestigial part of the conductive lead assembly in the planar section.
29. The method of Claim 26 wherein the vestigial part of the conductive lead assembly is a part of a wire bond.
30. A method of making a stackable microcircuit layer comprising the steps of: providing a plastic encapsulated microcircuit (PEM) that includes (a) a microcircuit having an active surface containing integrated circuitry and a bond pad,
(b) a wire bond connected to the bond pad, a lead frame, and a wire that connects the wire bond to the lead frame, and
(d) a plastic body that encapsulates the known-good microcircuit, the wire bond, the wire, and at least a portion of the lead frame; grinding a surface of the PEM to remove the lead frame and the wire and form a modified PEM that contains the microcircuit, the bond pad, and the wire bond, the modified PEM having a modified surface on which modified surface is exposed the wire bond that is connected to the bond pad; and forming an electrical lead on the modified surface that leads from the wire bond to an edge of the modified PEM.
31. The method of Claim 30 wherein the PEM has a package form factor known as a thin small outline package (TSOP).
32. The method of Claim 30 comprising the further step of covering the electrical lead with an insulating layer.
33. The method of Claim 30 comprising the further step of reducing the thickness of the modified PEM by thinning a backside of the modified PEM that is opposite to the electrical lead.
34. The method of Claim 30 comprising the further step of reducing the area of the modified PEM.
35. The method of Claim 34 wherein the further step reducing the area of the modified PEM is accomplished by sawing the modified PEM along one or more edges.
36. A stackable microcircuit layer comprising:
(1) a modified section of a plastic encapsulated microcircuit
(PEM) that originally contained (a) a known-good microcircuit having a bond pad, (b) a conductive lead assembly connected to the bond pad, and (c) a plastic body encapsulating the known-good microcircuit, the bond pad, and the conductive lead assembly, the modified section formed by removing a portion of the conductive lead assembly from the PEM; the modified section having a modified surface, the modified section containing the known-good microcircuit, the bond pad, and a remaining portion of the conductive lead assembly with an end thereof exposed on the modified -> surface; and
(2) a reroute lead on the modified surface of the modified section to connect the exposed portion of the remaining portion of conductive lead assembly with an edge of the modified section.
37. The 'stackable microcircuit layer of Claim 36wherein the commercially packaged microcircuit assembly has a package form factor known as a thin small outline package (TSOP).
38. The stackable microcircuit layer of Claim 37 wherein the modified section is a planar section containing the known-good microcircuit, the bond pad, the remaining portion of the conductive lead assembly, and a reduced-height portion of the plastic body.
39. The stackable microcircuit layer of Claim 38 wherein the conductive lead assembly originally comprises a wire bond, a lead frame, and a wire that are collectively encapsulated in the plastic body of the PEM, wherein the wire bond is formed on the bond pad, and wherein the wire connects the wire bond to the lead frame.
40. The stackable microcircuit layer of Claim 39 wherein the remaining portion of the conductive lead assembly that is exposed on the modified surface is the wire bond.
41. The stackable microcircuit layer of Claim 40 wherein the wire bond is exposed on the modified surface by grinding away a portion of the plastic body along with the lead frame, the wire, and a portion of the wire bond.
42. The stackable microcircuit layer of Claim 36 wherein the commercially packaged microcircuit assembly has a package form factor known as a micro-Ball Grid Array (uBGA) package.
43. The stackable microcircuit layer of Claim 42 wherein the modified section contains the known-good microcircuit, the bond pad, the remaining portion of the conductive lead assembly, and the plastic body.
44. The stackable microcircuit layer of Claim 43 wherein the conductive lead assembly originally comprises a conductive trace, a flexible substrate that supports the conductive trace, and a solder ball, a first end of the conductive trace connected to the bond pad and a second end of the conductive trace connected to the solder ball.
45. The stackable microcircuit layer of Claim 44 wherein the remaining portion of the conductive lead assembly that is exposed on the modified surface is the second end of the conductive trace.
PCT/US2002/002276 2001-01-26 2002-01-25 A stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same WO2002062118A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2002562134A JP2004523902A (en) 2001-01-26 2002-01-25 Stackable microcircuit layer formed from resin-sealed microcircuit and method of making same
EP02705988.0A EP1360882B1 (en) 2001-01-26 2002-01-25 Method of making a stackable microcircuit layer strating from a plastic encapsulated microcircuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/770,864 US20020100600A1 (en) 2001-01-26 2001-01-26 Stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same
US09/770,864 2001-01-26

Publications (1)

Publication Number Publication Date
WO2002062118A1 true WO2002062118A1 (en) 2002-08-08

Family

ID=25089941

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/002276 WO2002062118A1 (en) 2001-01-26 2002-01-25 A stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same

Country Status (4)

Country Link
US (2) US20020100600A1 (en)
EP (1) EP1360882B1 (en)
JP (1) JP2004523902A (en)
WO (1) WO2002062118A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2186131A2 (en) * 2007-08-03 2010-05-19 Tessera Technologies Hungary Kft. Stack packages using reconstituted wafers
EP2186134A2 (en) * 2007-07-27 2010-05-19 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
US7872339B2 (en) 2002-04-22 2011-01-18 Keith Gann Vertically stacked pre-packaged integrated circuit chips
US9899353B2 (en) 2006-10-10 2018-02-20 Tessera, Inc. Off-chip vias in stacked chips

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030221313A1 (en) * 2001-01-26 2003-12-04 Gann Keith D. Method for making stacked integrated circuits (ICs) using prepackaged parts
US7174627B2 (en) * 2001-01-26 2007-02-13 Irvine Sensors Corporation Method of fabricating known good dies from packaged integrated circuits
DE10231385B4 (en) * 2001-07-10 2007-02-22 Samsung Electronics Co., Ltd., Suwon Semiconductor chip with bond pads and associated multi-chip package
US6667225B2 (en) * 2001-12-17 2003-12-23 Intel Corporation Wafer-bonding using solder and method of making the same
US6690088B2 (en) * 2002-01-31 2004-02-10 Macintyre Donald M. Integrated circuit package stacking structure
US7777321B2 (en) * 2002-04-22 2010-08-17 Gann Keith D Stacked microelectronic layer and module with three-axis channel T-connects
EP1520454B1 (en) * 2002-06-27 2012-01-25 PPG Industries Ohio, Inc. Single or multi-layer printed circuit board with extended breakaway tabs and method of manufacture thereof
KR100621991B1 (en) * 2003-01-03 2006-09-13 삼성전자주식회사 Chip scale stack package
US20040264148A1 (en) * 2003-06-27 2004-12-30 Burdick William Edward Method and system for fan fold packaging
US7214605B2 (en) * 2003-10-09 2007-05-08 Intel Corporation Deposition of diffusion barrier
US8074082B2 (en) * 2004-10-08 2011-12-06 Aprolase Development Co., Llc Anti-tamper module
DE102004057485B4 (en) 2004-11-29 2007-10-18 Infineon Technologies Ag Power semiconductor component and method for its production
US7709943B2 (en) 2005-02-14 2010-05-04 Daniel Michaels Stacked ball grid array package module utilizing one or more interposer layers
EP1724835A1 (en) * 2005-05-17 2006-11-22 Irvine Sensors Corporation Electronic module comprising a layer containing integrated circuit die and a method for making the same
JP4819398B2 (en) * 2005-05-18 2011-11-24 アプロレーザ ディベロップメント カンパニー リミテッド ライアビリティー カンパニー Electronic module
US8051557B2 (en) * 2006-03-31 2011-11-08 Princo Corp. Substrate with multi-layer interconnection structure and method of manufacturing the same
US7990727B1 (en) 2006-04-03 2011-08-02 Aprolase Development Co., Llc Ball grid array stack
US8723332B2 (en) 2007-06-11 2014-05-13 Invensas Corporation Electrically interconnected stacked die assemblies
TWI473183B (en) * 2007-06-19 2015-02-11 Invensas Corp Wafer level surface passivation of stackable integrated circuit chips
TW200917391A (en) * 2007-06-20 2009-04-16 Vertical Circuits Inc Three-dimensional circuitry formed on integrated circuit device using two-dimensional fabrication
KR101348748B1 (en) * 2007-08-24 2014-01-08 삼성전자주식회사 Method for manufacturing a semiconductor package using a pad redistribution substrate
US8704379B2 (en) 2007-09-10 2014-04-22 Invensas Corporation Semiconductor die mount by conformal die coating
JP2009071095A (en) * 2007-09-14 2009-04-02 Spansion Llc Method of manufacturing semiconductor device
KR101554761B1 (en) 2008-03-12 2015-09-21 인벤사스 코포레이션 Support mounted electrically interconnected die assembly
US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
US7863159B2 (en) * 2008-06-19 2011-01-04 Vertical Circuits, Inc. Semiconductor die separation method
WO2010104543A2 (en) * 2008-12-31 2010-09-16 Arizona Board Of Regents, For And On Behalf Of Arizona State University Integrated circuits secure from invasion and methods of manufacturing the same
KR101013562B1 (en) * 2009-01-23 2011-02-14 주식회사 하이닉스반도체 Cube semiconductor package
US8194411B2 (en) * 2009-03-31 2012-06-05 Hong Kong Applied Science and Technology Research Institute Co. Ltd Electronic package with stacked modules with channels passing through metal layers of the modules
JP5963671B2 (en) * 2009-06-26 2016-08-03 インヴェンサス・コーポレーション Electrical interconnection for stacked dies in zigzag configuration
US20110031982A1 (en) * 2009-08-06 2011-02-10 Irvine Sensors Corporation Tamper-resistant electronic circuit and module incorporating electrically conductive nano-structures
US20110085304A1 (en) * 2009-10-14 2011-04-14 Irvine Sensors Corporation Thermal management device comprising thermally conductive heat spreader with electrically isolated through-hole vias
US20110096511A1 (en) * 2009-10-26 2011-04-28 Christian Krutzik Ultra-low profile multi-chip module
WO2011056668A2 (en) 2009-10-27 2011-05-12 Vertical Circuits, Inc. Selective die electrical insulation additive process
TWI544604B (en) 2009-11-04 2016-08-01 英維瑟斯公司 Stacked die assembly having reduced stress electrical interconnects
US20110147568A1 (en) * 2009-12-18 2011-06-23 Irvine Sensors Corporation High density array module and connector
US9431275B2 (en) 2010-09-17 2016-08-30 Pfg Ip Llc Wire bond through-via structure and method
US9113829B2 (en) * 2013-03-27 2015-08-25 Google Inc. Systems and methods for encapsulating electronics in a mountable device
KR102099878B1 (en) * 2013-07-11 2020-04-10 삼성전자 주식회사 Semiconductor Package
US9490146B2 (en) 2014-06-02 2016-11-08 Stmicroelectronics, Inc. Semiconductor device with encapsulated lead frame contact area and related methods
US9165867B1 (en) 2014-08-01 2015-10-20 Stmicroelectronics, Inc. Semiconductor device with lead frame contact solder balls and related methods
US9490195B1 (en) 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
US9825002B2 (en) 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
US9595511B1 (en) 2016-05-12 2017-03-14 Invensas Corporation Microelectronic packages and assemblies with improved flyby signaling operation
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
CN107170676B (en) * 2017-05-26 2019-08-30 武汉新芯集成电路制造有限公司 A method of improving semiconductor structure side section flatness
US10777457B2 (en) * 2017-10-03 2020-09-15 Ubotic Company Limited Carrier substrate, package, and method of manufacture
CN113517222B (en) * 2021-03-26 2023-06-16 中国船舶重工集团公司第七二三研究所 Microsystem component stacking method based on rewiring technology
CN113299626B (en) * 2021-06-29 2022-10-18 广东佛智芯微电子技术研究有限公司 Conductive assembly for multi-chip packaging and manufacturing method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5086018A (en) * 1991-05-02 1992-02-04 International Business Machines Corporation Method of making a planarized thin film covered wire bonded semiconductor package
US5424254A (en) 1994-02-22 1995-06-13 International Business Machines Corporation Process for recovering bare semiconductor chips from plastic packaged modules by thermal shock
US5454160A (en) * 1993-12-03 1995-10-03 Ncr Corporation Apparatus and method for stacking integrated circuit devices
US5953588A (en) 1996-12-21 1999-09-14 Irvine Sensors Corporation Stackable layers containing encapsulated IC chips
US6060373A (en) * 1998-07-10 2000-05-09 Citizen Watch Co., Ltd. Method for manufacturing a flip chip semiconductor device
US6342398B1 (en) * 1998-12-17 2002-01-29 Taiwan Semiconductor Manufacturing Company Method of backside emission analysis for BGA packaged IC's

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4028722A (en) * 1970-10-13 1977-06-07 Motorola, Inc. Contact bonded packaged integrated circuit
US4994215A (en) * 1980-08-04 1991-02-19 Fine Particle Technology Corp. Method of fabricating complex microcircuit boards, substrates and microcircuits and the substrates and microcircuits
US4889612A (en) * 1987-05-22 1989-12-26 Abbott Laboratories Ion-selective electrode having a non-metal sensing element
US5008213A (en) * 1988-12-09 1991-04-16 The United States Of America As Represented By The Secretary Of The Air Force Hybrid wafer scale microcircuit integration
US4989063A (en) * 1988-12-09 1991-01-29 The United States Of America As Represented By The Secretary Of The Air Force Hybrid wafer scale microcircuit integration
FR2688630B1 (en) * 1992-03-13 2001-08-10 Thomson Csf METHOD AND DEVICE FOR THREE-DIMENSIONAL INTERCONNECTION OF ELECTRONIC COMPONENT PACKAGES.
US5270673A (en) * 1992-07-24 1993-12-14 Hewlett-Packard Company Surface mount microcircuit hybrid
US5369056A (en) * 1993-03-29 1994-11-29 Staktek Corporation Warp-resistent ultra-thin integrated circuit package fabrication method
US5291061A (en) * 1993-04-06 1994-03-01 Micron Semiconductor, Inc. Multi-chip stacked devices
FR2704690B1 (en) * 1993-04-27 1995-06-23 Thomson Csf Method for encapsulating semiconductor wafers, device obtained by this process and application to the interconnection of wafers in three dimensions.
US5585600A (en) * 1993-09-02 1996-12-17 International Business Machines Corporation Encapsulated semiconductor chip module and method of forming the same
US5701233A (en) * 1995-01-23 1997-12-23 Irvine Sensors Corporation Stackable modules and multimodular assemblies
US5739581A (en) * 1995-11-17 1998-04-14 National Semiconductor Corporation High density integrated circuit package assembly with a heatsink between stacked dies
KR100214562B1 (en) * 1997-03-24 1999-08-02 구본준 Stacked semiconductor chip package and making method thereof
US5923081A (en) * 1997-05-15 1999-07-13 Micron Technology, Inc. Compression layer on the leadframe to reduce stress defects
TW344076B (en) * 1997-10-21 1998-11-01 Hon Hai Prec Ind Co Ltd Process for producing magnet core
US6001723A (en) * 1997-12-24 1999-12-14 National Semiconductor Corporation Application of wire bond loop as integrated circuit package component interconnect
US6307256B1 (en) * 1998-10-26 2001-10-23 Apack Technologies Inc. Semiconductor package with a stacked chip on a leadframe
US6429028B1 (en) * 2000-08-29 2002-08-06 Dpa Labs, Incorporated Process to remove semiconductor chips from a plastic package
US6368886B1 (en) * 2000-09-15 2002-04-09 The Charles Stark Draper Laboratory, Inc. Method of recovering encapsulated die
US6440835B1 (en) * 2000-10-13 2002-08-27 Charles W. C. Lin Method of connecting a conductive trace to a semiconductor chip
US6630369B2 (en) * 2001-07-17 2003-10-07 Ultra Tec Manufacturing, Inc. Sample preparation apparatus and method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5086018A (en) * 1991-05-02 1992-02-04 International Business Machines Corporation Method of making a planarized thin film covered wire bonded semiconductor package
US5454160A (en) * 1993-12-03 1995-10-03 Ncr Corporation Apparatus and method for stacking integrated circuit devices
US5424254A (en) 1994-02-22 1995-06-13 International Business Machines Corporation Process for recovering bare semiconductor chips from plastic packaged modules by thermal shock
US5953588A (en) 1996-12-21 1999-09-14 Irvine Sensors Corporation Stackable layers containing encapsulated IC chips
US6072234A (en) 1996-12-21 2000-06-06 Irvine Sensors Corporation Stack of equal layer neo-chips containing encapsulated IC chips of different sizes
US6060373A (en) * 1998-07-10 2000-05-09 Citizen Watch Co., Ltd. Method for manufacturing a flip chip semiconductor device
US6342398B1 (en) * 1998-12-17 2002-01-29 Taiwan Semiconductor Manufacturing Company Method of backside emission analysis for BGA packaged IC's

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1360882A4

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7872339B2 (en) 2002-04-22 2011-01-18 Keith Gann Vertically stacked pre-packaged integrated circuit chips
US8012803B2 (en) 2002-04-22 2011-09-06 Aprolase Development Co., Llc Vertically stacked pre-packaged integrated circuit chips
US9899353B2 (en) 2006-10-10 2018-02-20 Tessera, Inc. Off-chip vias in stacked chips
EP2186134A2 (en) * 2007-07-27 2010-05-19 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
EP2186131A2 (en) * 2007-08-03 2010-05-19 Tessera Technologies Hungary Kft. Stack packages using reconstituted wafers

Also Published As

Publication number Publication date
US20020100600A1 (en) 2002-08-01
EP1360882A1 (en) 2003-11-12
EP1360882A4 (en) 2009-05-06
JP2004523902A (en) 2004-08-05
US6706971B2 (en) 2004-03-16
EP1360882B1 (en) 2018-06-13
US20020126459A1 (en) 2002-09-12

Similar Documents

Publication Publication Date Title
US6706971B2 (en) Stackable microcircuit layer formed from a plastic encapsulated microcircuit
US7326592B2 (en) Stacked die package
US6043109A (en) Method of fabricating wafer-level package
US7528005B2 (en) Method of manufacturing chip size package semiconductor device without intermediate substrate
US6518655B2 (en) Multi-chip package-type semiconductor device
US7198980B2 (en) Methods for assembling multiple semiconductor devices
US7335986B1 (en) Wafer level chip scale package
US20110209908A1 (en) Conductor package structure and method of the same
US6852607B2 (en) Wafer level package having a side package
US8101461B2 (en) Stacked semiconductor device and method of manufacturing the same
US8994161B2 (en) Semiconductor device package and methods for producing same
JP2001024024A (en) Semiconductor package and manufacturing method
JP2003086762A (en) Semiconductor device and manufacturing method therefor
US7511369B2 (en) BGA-scale stacks comprised of layers containing integrated circuit die and a method for making the same
US6852570B2 (en) Method of manufacturing a stacked semiconductor device
US20110031607A1 (en) Conductor package structure and method of the same
US20100136747A1 (en) Method for manufacturing semiconductor package
US6339253B1 (en) Semiconductor package
US7332430B2 (en) Method for improving the mechanical properties of BOC module arrangements
CN113725096B (en) Semiconductor packaging method and semiconductor packaging structure
US20110031594A1 (en) Conductor package structure and method of the same
US6551855B1 (en) Substrate strip and manufacturing method thereof
CN113725097B (en) Semiconductor packaging method and semiconductor packaging structure
EP1724835A1 (en) Electronic module comprising a layer containing integrated circuit die and a method for making the same
US20020053450A1 (en) Wafer-level package

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2002562134

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 2002705988

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 2002705988

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642