WO2002058038A1 - Appareil, procede et programme de cryptage a compression arithmetique - Google Patents

Appareil, procede et programme de cryptage a compression arithmetique Download PDF

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Publication number
WO2002058038A1
WO2002058038A1 PCT/JP2002/000365 JP0200365W WO02058038A1 WO 2002058038 A1 WO2002058038 A1 WO 2002058038A1 JP 0200365 W JP0200365 W JP 0200365W WO 02058038 A1 WO02058038 A1 WO 02058038A1
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Prior art keywords
symbol
key
arithmetic
piecewise linear
encryption
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PCT/JP2002/000365
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English (en)
Japanese (ja)
Inventor
Kiyosi Tanaka
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Evolvable Systems Research Institute, Inc.
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Priority to JP2002558245A priority Critical patent/JP4086660B2/ja
Publication of WO2002058038A1 publication Critical patent/WO2002058038A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/41—Bandwidth or redundancy reduction
    • H04N1/411—Bandwidth or redundancy reduction for the transmission or storage or reproduction of two-tone pictures, e.g. black and white pictures
    • H04N1/413—Systems or arrangements allowing the picture to be reproduced without loss or modification of picture-information
    • H04N1/417—Systems or arrangements allowing the picture to be reproduced without loss or modification of picture-information using predictive or differential encoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/40—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
    • H03M7/4006—Conversion to or from arithmetic code
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/44—Secrecy systems
    • H04N1/448—Rendering the image unintelligible, e.g. scrambling
    • H04N1/4486—Rendering the image unintelligible, e.g. scrambling using digital data encryption

Definitions

  • the present invention relates to an arithmetic compression encryption device, an arithmetic compression encryption method, and a program for encoding a symbol based on the appearance probability of the symbol output from a model device for predicting the appearance probability of a symbol.
  • Arithmetic compression / encryption device that can achieve high security without compromising the original data compression rate by arithmetic coding when data compression and encryption are performed simultaneously using an encoding method.
  • Conventional technology Conventional technology
  • the arithmetic encoder to be realized is composed of a model unit that predicts the appearance probability of a symbol, and an encoder that performs re-encoding based on the appearance probability of the symbol output from the model unit and actual input symbols. Since it is configured, encryption is performed for this model unit or encoder.
  • techniques for encrypting model devices include “Witten,“ On the Privacy Afforded by Adaptive Text Compression ”, Computer & Security, Vol. 7, pp. 397-408 , 1998 (hereinafter referred to as the “Witten method”) ”and“ Liu, “Resisting the Bergen-Hogan Attack on Adaptive Arithmetic Coding”, Proc.IMA Conference on Coding and Cryptography, pp.199-208, 1998 (hereinafter “ iu method) j and "Uehara,” Attacking and Mending Ar ithmetic Coding Encryption Schemes ", Proc. Twenty-Second Australian Computer Science Conference, pp. 408-419, 1998 (hereinafter referred to as the” Uehara method ").
  • the Witten method is a technology that uses the model device to be used and its initial value as an encryption key.
  • the Uu method uses W as the encryption key using the initial value of the model device as in the ten method, and uses the initial value in the encoder.
  • the Uehara method is a technique that selects a mapping section with a key and then encodes a dummy symbol at the beginning. Similar to the Witten method, the initial value of the model unit is used as an encryption key, and the code output from the encoder is used. This is a technology that performs a masking operation by XOR on a word.
  • encryption technologies for encoders include “Tarukawa,“ Secret key cryptosystem using arithmetic codes ”, IEICE Technical Report, IT91-34, 1991 (hereinafter“ Tarukawa method ”). "), And a secret key encryption / decryption method disclosed in Japanese Patent Application Laid-Open No. H11-73102, and an encoding method disclosed in Japanese Patent Application Laid-Open No. HEI 6-112280. Decoding methods and the like are known.
  • the Tarukawa method is a technique in which an encoder replaces a section corresponding to a resymbol with a key and performs encoding, and further encodes a dummy symbol in the beginning.
  • Japanese Patent Application Laid-Open No. H11-731102 The invention according to the gazette uses the upper limit value of the initial mapping section in the encoder as a key, and the invention according to Japanese Patent Laid-Open Publication No. The probability of appearance is the key.
  • the model device used and its initial value are used as an encryption key. Therefore, there is a problem that the key is easily specified when the model device is specified. In particular, in an international standard system that employs an arithmetic coding method, the model device is known, so the security is reduced.
  • an encoder is subject to encryption, such as the Tarukawa method, Japanese Patent Application Laid-Open No. H11-71032, and Japanese Patent Application Laid-Open No. H6-111280, There is a problem that sufficient agitation cannot be obtained for the power code, and a problem that the compression ratio is reduced by coding the dummy symbol.
  • An object of the present invention is to provide an arithmetic compression encryption device, an arithmetic compression encryption method, and a program that can obtain high security without impairing the data compression ratio.
  • an arithmetic-type compression encryption device includes a code for the symbol based on the appearance probability of the symbol output from a model device that predicts the appearance probability of the symbol.
  • An arithmetic-type compression encryption device for performing the conversion, wherein an appearance probability input means for inputting the appearance probability of the symbol from the model device, and a dynamic based on the appearance probability of the symbol input by the appearance probability input means.
  • Compression encoding means for controlling a piecewise linear map with an encryption key to compress and encrypt an output code.
  • the compression encryption means is characterized in that the output code is disturbed by replacing the position of the dynamic piecewise linear mapping with the encryption key.
  • the compression encryption unit is characterized in that the output code is disturbed by perturbing the slope of the dynamic piecewise linear mapping with the encryption key.
  • the information source is expanded to disturb the output code.
  • FIG. 1 is a block diagram showing a configuration of an arithmetic compression encryption device according to an embodiment of the present invention.
  • Fig. 2 is a diagram showing the sections allocated according to the symbol appearance probabilities.
  • Figure 3 is a diagram showing a generalized Berne-Isift mapping known as one of the piecewise linear mappings that generate chaotic orbits.
  • FIG. 4 is a diagram showing a mapping used when the position of a dynamic piecewise linear mapping is replaced with a key and the output code is disturbed.
  • FIG. 5 is a diagram showing an allocation section when the output code is disturbed by replacing the position of the dynamic piecewise linear mapping with a key.
  • FIG. 6 is a diagram illustrating an example of section division in a case where the position of a dynamic piecewise linear mapping is replaced with a key and output codes are disturbed.
  • FIG. 7 is a flowchart showing a processing procedure at the time of encoding when the output code is disturbed by replacing the position of the dynamic piecewise linear mapping with a key.
  • FIG. 8 is a flowchart showing a processing procedure at the time of decoding when the output code is disturbed by replacing the position of a dynamic piecewise linear mapping with a key.
  • FIG. 9 is a diagram showing a mapping used in a case where the slope of a dynamic piecewise linear mapping is perturbed with a key to disturb the output code.
  • FIG. 10 is a diagram showing an allocation section in the case where the inclination of a dynamic piecewise linear mapping is perturbed with a key to disturb the output code.
  • Figure 11 shows that the output code is obtained by perturbing the slope of a dynamic piecewise linear map with a key. It is a figure showing an example of section division in the case of disturbance.
  • FIG. 12 is a flowchart showing a processing procedure at the time of encoding when the output code is disturbed by perturbing the slope of the dynamic piecewise linear map with a key.
  • FIG. 13 is a flowchart showing a processing procedure at the time of decoding when the output code is disturbed by perturbing the inclination of the dynamic piecewise linear map with a key.
  • FIG. 14 is a diagram showing a mapping used when a dynamic piecewise linear mapping is controlled by a key and the output codes are disturbed by arbitrarily combining the methods (1) and (2).
  • FIG. 15 is a diagram showing an allocation section in the case where the piecewise linear mapping shown in FIGS. 9 and 14 is used.
  • FIG. 16 is a diagram showing an example of section division in the case where the output codes are disturbed by arbitrarily combining the methods (1) and (2) when controlling a dynamic piecewise linear mapping with a key.
  • Figure 17 is a flow chart showing the processing steps during encoding when the output code is disturbed by arbitrarily combining the methods (1) and (2) when controlling a dynamic piecewise linear mapping with a key. It is.
  • FIG. 18 is a flowchart showing a processing procedure at the time of decoding when the output code is disturbed by arbitrarily combining the methods (1) and (2) when a dynamic piecewise linear mapping is controlled by a key. It is.
  • FIG. 19 is a diagram showing a piecewise linear mapping in a case where the output code is disturbed by expanding the information source.
  • FIG. 20 is a block diagram showing a configuration when the arithmetic compression encryption device is implemented by JBIG2.
  • FIG. 21 is an explanatory diagram showing a method of generating a context by extracting a 16-bit reference pixel from a reference pixel area by a context generator in JBIG2.
  • Figure 22 is an explanatory diagram showing a context learning table that dynamically manages the index I (GX) and MPS corresponding to the context.
  • FIG. 23 is an explanatory diagram showing a state (index) transition table used in JBIG2.
  • FIG. 24 is an explanatory diagram showing a method of controlling (moving) the probability estimation value q k obtained from the state transition diagram by the perturbation method in the direction of an ideal value using a key.
  • I og 2 ⁇ to be prepared in order to derive the I og 2 S - is an explanatory diagram showing a table which gives the approximate value of I og 2 0xAAAA.
  • FIG. 26 is an explanatory diagram showing a table giving an approximate value of log 2 Qe prepared for deriving log 2 ⁇ 5.
  • FIG. 27 is a flowchart showing the entire encoding process in the compression encryption device.
  • FIG. 28 is a flowchart showing the initialization process (INITENC) of S10.
  • FIG. 29 is a flowchart showing the encoding process (ENCODE) of the 1-bit symbol a; of S12.
  • FIG. 30 is a flowchart showing the encoding process (C0DE1) of S31.
  • FIG. 31 is a flowchart showing the encoding process (C0DE0) of S32.
  • FIG. 32 is a flowchart showing the perturbation processing (GHANGEQE) of S 40, S 50, and S 220.
  • FIG. 33 is a flowchart showing the mapping switching process (GODELPSENGRYPT) of S42 and S52.
  • FIG. 34 is a flowchart showing the mapping switching processing (CODEMPSENCRYPT) of S43 and S53.
  • FIG. 35 is a flowchart showing the section width normalization processing (REM0RME) of S90 and S111.
  • FIG. 36 is a flowchart showing the byte-by-byte output processing (BYTE0UT) of S122.
  • FIG. 37 is a flowchart showing the encoding completion processing (FLUSH) of S14.
  • FIG. 38 is a flowchart showing the final bit setting process (SETB ITS) of S140.
  • FIG. 39 is a block diagram showing a configuration in a case where the arithmetic decompression decoding device is implemented by JBIG2.
  • FIG. 40 is a flowchart showing the entire decoding process in the decompression decoder. It is.
  • FIG. 41 is a flowchart showing the initialization processing (INI TDEC) of S200.
  • FIG. 42 is a flowchart showing the decoding process (DECODE) of 1-bit symbol a i of S202.
  • FIG. 43 is a flowchart showing the decoding process (LPS_EXGHANGE DECRYPT) of S2334.
  • Fig. 44 is a flow chart showing the decryption processing (MPS—EXCHANGE DECRYPT) of S230.
  • FIG. 45 is a flowchart showing the section width normalization processing (REN0RMD) of S231 and S235.
  • FIG. 46 is a protocol showing the byte-by-byte read processing (BYTE IN) of S2261.
  • FIG. 47 is an explanatory diagram showing mathematical expressions. Explanation of reference numerals
  • M is a model unit
  • N is an encoder
  • ai is 1 bit input Shinporu
  • Y (a,) is the lower limit for ai
  • a n is an input symbol sequence n bit
  • W (a n) is the interval width to a n
  • X ( a n) is the lower limit of W (a n)
  • K is the key sequence
  • ⁇ (a n) is a code word for a n.
  • FIG. 1 is a block diagram showing a configuration of an arithmetic compression encryption device according to the present embodiment.
  • the arithmetic compression encryption device 10 includes a model unit M and an encoder N.
  • the encoder N is a processing unit that performs encryption according to the present invention, and performs data compression and encryption by controlling a dynamic piecewise linear mapping with a key in the encoding process of the arithmetic encoding method. Perform at the same time.
  • the arithmetic compression encoding device 10 considers the decoding process of the arithmetic coding method as a repetition of the Bernoulli-Shift mapping, which is known as a piecewise linear mapping that generates chaotic orbits. Encoding is performed in the encoder N of the encoding method.
  • the piecewise linear mapping used is interpreted as a generalized dynamic Bernoulli-Shift mapping. Can be used. This As a result, a practically high data compression ratio and security can be satisfied at the same time. Also, it is used in combination with the encryption method for model units such as the Witten method, the Liu method, and the Uehara method, the method of encoding dummy symbols, and the method of performing masking operation on the output code as described in the section of the prior art. You can do that too.
  • the dynamic piecewise linear mapping is controlled using the key, so that the obtained output code does not impair the original data compression rate by the arithmetic coding. , Is randomly and uniformly distributed throughout the mapping domain [0, 1], making it difficult for third parties to provide clues for decryption.
  • the half-open interval [0, 1] is assigned to the interval shown in FIG. 2 according to the appearance probability of the symbol.
  • interval width W (a ') and its lower limit X (a') for the symbol sequence a i a, a 2 ... a;
  • X (a ') X ( a preparative 1) + W (a 1 - 1) Y (a') (2) I Ri is recursively determined.
  • X (a 1 ) indicates the lower limit of the section allocated to the i-bit symbol sequence a 1 , and the lower limit Y (ai Different from You.
  • Decoding in the arithmetic coding method is performed using Fig. 2 used for coding.
  • the first symbol a, of the symbol sequence a ⁇ to be decoded is decoded by determining which symbol in FIG. 2 corresponds to which symbol in z.
  • the arithmetic compression encryption device 10 differs from the arithmetic coding method in that the data compression is performed by controlling a dynamic piecewise linear mapping with a key in the coding process of the arithmetic coding. And encryption at the same time.
  • (1) a method in which the position of a dynamic piecewise linear map is replaced with a key to disturb the output code, and (2) the output code is changed by changing the slope of the dynamic piecewise linear map with a key.
  • (3) a method of disturbing an output code by arbitrarily combining the methods (1) and (2) when controlling a dynamic piecewise linear mapping with a key; (4) a dynamic piecewise linear mapping
  • the key is controlled by the methods (1) to (3), the method of expanding the information source and disturbing the output code is adopted. Therefore, these methods will be described in more detail below.
  • symbol decoding is a mapping ⁇ .
  • FIG. 7 is a flowchart showing a processing procedure at the time of encoding when the output code is disturbed by replacing the position of the dynamic piecewise linear mapping with a key. As shown in the figure, it sets the variable i to 1 (step S 7 0 1), ⁇ ,, k r; and a; inputting the (scan Tetsupu S 7 0 2).
  • step S704 it is checked whether or not k is 0, and whether or not a
  • Step S710 the variable i is compared with n (step S711), and when both are equal, step S off 1 1 Yes), outputs the cp (a n) (step S 7 1 2). If the two are not equal (No at Step S711), the process moves to Step S702 and the same processing is repeated.
  • X i obtained from the mapping corresponding to k “i”
  • the symbol ai is decoded by determining whether it is in the section corresponding to the bol. This was repeated n times, to decode the symbol sequence a n.
  • FIG. 8 is a flowchart showing a processing procedure at the time of decoding when the output code is disturbed by replacing the position of a dynamic piecewise linear mapping with a key.
  • chi iota phi (3 one and then, after setting a variable i to 1 (step S 8 0 1), and inputs the k r i (Step S 8 0 2).
  • step S804 it is checked whether or not k is 0 and whether or not X is smaller than (steps S803, S804, S807 ), and if kri is 0 and X If i is smaller than CM (Yes at step S804),
  • Step S810 After incrementing the variable ⁇ (Step S810), the variable i is compared with n (Step S811), and if both are equal, (Step S810) step S 8 1 1 Yes), outputs the a n (step S 8 1 2). If the two are not equal (No at Step S811), the process moves to Step S820 and the same processing is repeated.
  • step S806 the same processing (steps 3810 to 3812) is performed.
  • the output code can be agitated without impairing the data compression rate, and high security can be achieved. Can be held.
  • ) of the piecewise linear map used in the decoding process is clearly larger than 1 and is an enlarged map. Therefore, if the inclination of the map changes slightly due to perturbation, the obtained orbit will gradually change completely different from the chaotic nature. As a result, the decoding result of the symbol is similarly meaningless.
  • the lower limit Y (a,) defined as ⁇ 10 is used at the time of encoding.
  • the key sequence K s causes the slope of the piecewise linear mapping to be used to change due to perturbation, and the position of the section corresponding to the symbol sequence a ⁇ , that is, the code word is arbitrarily stirred. Can be.
  • Figure "! 2" is a flowchart showing a coding procedure in the case where the output code is disturbed by perturbing the slope of a dynamic piecewise linear map with a key.
  • step S 1 2 0 1 it sets the variable i to 1 (step S 1 2 0 1), ai, enter the k s i and ai (Step S 1 2 0 2), to determine the Bi from k s i Later (step S1 203), ⁇
  • ' 6
  • step S 1208 After incrementing the variable ⁇ ⁇ ⁇ ⁇ (step S 1208), the variable i is compared with n (step S 1209), and both are equal. If (step S 1 2 0 9 Yes), it outputs the cp (a n) (Sutetsu flop S 1 2 1 0). If the two are not equal (No at Step S 1209), the process moves to Step S 122 and the same processing is repeated.
  • Decoding code words obtained in this way ⁇ (a ") is performed as follows. First, the first time period value X (a n), ⁇ the Arufaiota using 6j determined from the value of the key k ' Then, from Fig. 10 it is determined which symbol X, corresponds to which interval, and the first symbol a, is decoded. Then, the mapping by Eq. to give alms X 2, similarly with the beta 2 which is determined from the value of k s 2 Fixed alpha 2 to alpha 2 ', it decrypts the chi 2 from Figure 1 0.
  • the key! Ai is changed to a using Bi determined from the value of ⁇ , and it is determined whether Xi obtained from the mapping by Eq. (8) is in the interval corresponding to either symbol in Fig. 10. Decode the symbol ai. This is repeated n times to decode the symbol sequence a n .
  • FIG. 13 is a flowchart showing a processing procedure at the time of decoding when the output code is disturbed by perturbing the slope of the dynamic piecewise linear map with a key.
  • x 1 (a p (a n)
  • sets the variable ⁇ to 1 (Step S 1 3 0 1).
  • enter the k s i (Step S 1 3 0 2 ), This or After determining Bi from them (step S133), (Step S1304).
  • step S1305 it is checked whether X
  • step S1308 After incrementing the variable i (step S1308), the variable ⁇ is compared with ⁇ (step S1309), and both are equal. correct if (step S 1 3 0 9 Yes), outputs the a n (step S 1 3 1 0). If they are not equal (No at Step S1309), the process moves to Step S1302 and the same processing is repeated.
  • the perturbation method of cti by equation (7) includes (i) a method of directly multiplying ⁇ , by, a method of calculating a small numerical value (addition, subtraction, XOR, etc.) in (Ui), and (ii) It is possible to use a method of creating and using a table in advance corresponding to cti, etc. (3) When controlling a dynamic piecewise linear mapping with a key, any combination of the methods (1) and (2) can be used.
  • FIG. 10 is extended to FIG. 15, and the result of the encoding according to FIG. 15 and the equations (1) and (2) is further different from that of the conventional method.
  • FIG. 17 is a flow chart showing the processing procedure for encoding when the output code is disturbed by arbitrarily combining the methods (1) and (2) when controlling a dynamic piecewise linear mapping with a key. It is.
  • step S 1 706 affirmative
  • step S1772 After incrementing the variable ⁇ ⁇ ⁇ ⁇ (step S1772), the variable ⁇ is compared with ⁇ (step S1773), and both are equal. correct if (step S 1 7 1 3 Yes), it outputs the cp (a n) (Sutetsu flop 'S 1 7 1 4). If the two are not equal (No at step S1713), the process moves to step S1702 and the same processing is repeated.
  • Step S1710 and perform the same processing (step S1712 to S1714).
  • Step SI 7 11 1 the same processing (Steps S 1 7 1 2 to S 17 Perform 1) 4).
  • Fig. 18 is a flowchart showing the processing procedure for decoding when the output code is disturbed by arbitrarily combining the methods (1) and (2) when controlling the dynamic segmented linear mapping with the key. It is one.
  • step S1812 After incrementing the variable i (step S1812), the variable i is compared with n (step S1813), and the two are equal. If (step S 1 8 1 3 Yes), it outputs the a n (step S 1 8 1 4). If they are not equal (No at Step S1813), the process moves to Step S1802 and the same processing is repeated.
  • step S 18 if k is 0 and X i force ⁇ h or more (step S 18
  • step S 1 8 0 9 affirmative If k is 1 and X i is smaller than C ′ (step S 1 8 0 9 affirmative),
  • Step S1810 and perform the same processing (step S1812 to S1814).
  • x i + 1 (xi— 1 + ⁇ , ') / ⁇ ,'
  • Step S 811 and perform the same processing (Steps S 1812 to S 1814).
  • the encoder N of the arithmetic compression encryption device 10 replaces the position of the dynamic piecewise linear mapping with the key based on the appearance probability input from the model device M.
  • the key is to change the slope of the dynamic piecewise linear mapping, or these are combined, or the information source is expanded, so that the output code can be easily mixed without impairing the data compression rate. High security can be maintained.
  • FIG. 24 is an explanatory diagram showing a method of controlling (moving) the probability estimation value q k obtained from the state transition diagram by the perturbation method with a key in the direction of an ideal value in the fifth embodiment. is there.
  • the direction and magnitude of this displacement ( The probability estimate c used in the calculation of the encoding is moved in a direction approaching the typical value q k '.
  • S the key data K of many bits is used, and when S is small, the key data K of at least 0 bit is used to control the movement amount.
  • the perturbation can be applied efficiently, and by applying the perturbation, the probability estimation value q k used in the calculation of the encoding becomes more ideal value q k '. Therefore, the coding efficiency (compression rate) is improved as compared with the ordinary MQ coder.
  • FIG. 20 is a block diagram showing a configuration in a case where an arithmetic compression encryption device is implemented in JBIG2.
  • the well-known JBIG 2 arithmetic coder (MQ coder) consists of three main blocks.
  • the model unit inputs the context CX from the context generator, and inputs the information about the presence / absence of normalization described later and information on whether ai is MPS or not from the coder. (I (CX)) and MPS values are output.
  • the encoder has the values of the interval width A (a ( -') and the lower limit C (ai- 1 ) of the interval as the internal state, and the values of the information source index u (I (GX)) and the value of the MPS. Is input, and further, key data K is input, and the compressed encryption data CD and information on the presence / absence of normalization and information on whether ai is MPS are output.
  • the context generator and the model device can be adopted as they are from the well-known MQ coder configuration and processing, so detailed description is omitted.
  • Figure 21 shows a method of extracting a 16-bit reference pixel from the reference pixel area with a context generator and generating a context CX in JBIG2.
  • FIG. The pixel of interest read out the pixel values of r 1 6 from the reference pixel position r, defined in advance by any method, the first six bits con vertex preparative CX is produced.
  • FIG. 27 is a flowchart showing the entire encoding process in the compression encryption device including the functions of the encoder and the model device.
  • an initialization process (ITENC) described later is performed.
  • the context CX and the 1-bit input symbol ai are read.
  • an encoding process (ENCODE) described later is performed.
  • FIG. 28 is a flowchart showing the initialization processing (INITENC) of S10.
  • the interval width A is 8000 in hexadecimal
  • the lower limit C of the interval is 0
  • the file pointer BP for writing data is BPST-1 (the initial value is 11)
  • the number of coding bits is Set the variable CT used for counting (write data when it reaches 0) to 12.
  • the context learning table is also initialized in the initialization processing.
  • FIG. 29 is a flowchart showing the encoding process (ENCODE) of the 1-bit symbol ai of S12.
  • ENCODE the encoding process
  • S31 the encoding process (C0DE1) when ai is 1 is performed.
  • S32 an encoding process (C0DE0) when ai is 0 is performed.
  • FIG. 30 is a flowchart showing the encoding process (C0DE1) of S31.
  • C Qe is obtained by perturbation processing (GHANGEQE) described later.
  • GANGEQE perturbation processing
  • FIG. 22 is an explanatory diagram showing a context learning table for dynamically managing the index I (CX) and the MPS corresponding to the context. As shown in the figure, the MPS value and the current index I (GX) are stored for each context value. MPS and I (CX) change with time, and their initial values are all zero.
  • mapping switching process when the input symbol is LPS described later is performed, and in S 43, the input symbol is MPS described later. In this case, a mapping switching process (GODEMPSENCRYPT) is performed.
  • FIG. 31 is a flowchart showing the encoding process (G0DE0) of S32.
  • C Qe is obtained by perturbation processing (GHANGEQE) described later.
  • GANGEQE perturbation processing
  • FIG. 32 is a flowchart showing the perturbation processing (GHANGEQE) of S40 and S50.
  • GANGEQE the perturbation processing
  • a (a ') OxAAAA + m
  • 2 5 is an explanatory diagram showing the contents of the table gives the approximate value of I og 2 1 ⁇ I- I og 2 0xAAAA for deriving the I og 2 [delta]. For each predetermined range of interval width A, log 2 l ⁇ I - approximation of log 2 0xAAAA is described.
  • FIG. 26 is an explanatory diagram showing a table giving an approximate value of log 2 Qe prepared for deriving log 2 S. The approximate value of I og 2 Q e is described for each index.
  • FIG. 2 5 tables are calculated at high speed without using.
  • og 2 0xAAAA Ri by an approximation to the method shown in the following
  • FIG. 2 5 tables are calculated at high speed without using.
  • the table shown in Fig. 25 what is the calculated value of log 2 (
  • the target log 2 (
  • ⁇ ) -N.
  • the concept of the table in Fig. 25 is used, the value of hexadecimal ⁇ is not stored in the memory, and the calculation of I og 2 (
  • step S68 it is determined whether KeyBitNum is negative. If the determination result is positive, the flow shifts to S69 to set KeyBitNum to 0. In step S0, the variables KeyBits and counter are set to 0.In step S71, it is determined whether the counter value is equal to KeyBitNum.If the determination result is affirmative, the process proceeds to step S74. If not, shift to S72. Te is S 7 2 smell, read one bit from the key data K, and k s. In the S 7 3, shift to Bok the KeyBits to 1-bit left, to the least significant bit of KeyBits and k s. Also, add 1 to counter.
  • S74 it is determined whether or not A is smaller than AAAA. If the determination result is affirmative, the process shifts to S76. If the determination result is negative, the process shifts to S75.
  • S75 refer to the state transition table in Fig. 23 from the index. Add KeyBits to the obtained Q e value to obtain CQ e.
  • S76 KeyB s is subtracted from the Qe value obtained by referring to the state transition table in FIG. 23 to obtain C Qe.
  • FIG. 23 is an explanatory diagram showing a state (index) transition table used in JBIG2. For each index from 0 to 46, the transition destination (next) index number and SWITCH value are described when the Qe value, MPS or LPS appears.
  • the SWITCH value is a flag indicating whether or not the value of MPS is inverted when normalized by LPS when Qe is close to 0.5.
  • FIG. 33 is a flowchart showing the mapping switching process (GODELPSENGRYPT) of S42 and S52.
  • the present embodiment includes a process of exchanging a mapping interval according to the present invention, in which the interval is exchanged when the 1-bit value k r read from the key data K is “1”.
  • S80 1-bit read k r is obtained from key data K, and C Qe is subtracted from A. Then, the value of A is substituted into InvQe.
  • S81 it is determined whether or not A is smaller than CQe. If the determination result is affirmative, the process proceeds to S85, but if negative, the process proceeds to S82.
  • FIG. 34 is a flowchart showing the mapping switching process (GODEMPSENGRYPT) of S43 and S53.
  • the present embodiment includes a process of exchanging a mapping interval according to the present invention, in which the interval is exchanged when the 1-bit value k r read from the key data K is 1.
  • the interval is exchanged when the 1-bit value k r read from the key data K is 1.
  • subtracting the CQ e from A In the S 1 0 0, and from the key data K and 1-bit read-k r, subtracting the CQ e from A. Then, substitute the value of A into I nvQe.
  • S101 it is determined whether the logical product of A and hexadecimal 8000 is 0, and if the determination result is affirmative, the process proceeds to S104, but if the determination result is negative, S10 Move to 2.
  • S102 it is determined whether or not the key data kr is 0. If the result is affirmative, the flow shifts to S103, where CQ e is
  • S 104 it is determined whether A is smaller than CQ e . If the determination result is affirmative, the process proceeds to S 107, but if the result is negative, the process proceeds to S 105. . In S105, it is determined whether or not the key data kr is 0. If the result is affirmative, the flow shifts to S106 and CQ e is added to C. In S107, CQ e is substituted for A. In S108, it is determined whether the key data kr is 1 or not. If the result is affirmative, the process proceeds to S109 and C Add I nvQe to.
  • the context learning table in FIG. 22 is updated by substituting NLPS (I (CX)) for state I (GX) with reference to the state transition table in FIG.
  • normalization processing REN0RME described later is performed.
  • FIG. 35 is a flowchart showing the section width normalization processing (REN0RME) of S90 and S111.
  • S120 A is shifted left by one bit, Shift C left by one bit and subtract 1 from CT.
  • S121 it is determined whether or not CT is 0. If the result is affirmative, the flow shifts to S122 to perform byte unit output processing (BYTE0UT) described later.
  • S123 it is determined whether the logical product of A and the hexadecimal number 8000 is 0 or not. If the determination result is positive, the process returns to S120, but if the determination result is negative, the process is performed. finish.
  • FIG. 36 is a flowchart showing the byte-by-byte output processing (BYTE0UT) of S122.
  • BYTE0UT byte-by-byte output processing
  • FIG. 37 is a flowchart showing the encoding completion processing (FLUSH) of S14.
  • S40 a final bit setting process (SETB ITS) described later is performed.
  • S141 C is shifted left by CT bit.
  • S144 the above-described byte unit output processing (BYTE0UT) is performed, and in S144, C is shifted left by CT bit.
  • BYTE0UT the above-mentioned Bit unit output processing
  • step 4 1 is added to BP, and B is set to FF in hexadecimal.
  • step 4 if 7FFF follows FF in hexadecimal, 7FFF is removed (optional).
  • step148 1 is added to BP, B is set to AC in hexadecimal, and 1 is added to BP.
  • FIG. 38 is a flowchart showing the last bit setting processing (SETBITS) of S140.
  • (C + A) is assigned to TEMPG, and the logical sum of the lower limit C and hexadecimal FFFF is assigned to C.
  • S151 it is determined whether or not C is greater than or equal to TEMPG. If the determination result is negative, the process is terminated.
  • S152 8000 is subtracted in hexadecimal from the beginning.
  • FIG. 39 is a block diagram showing a configuration in a case where the arithmetic decompression decoding device is implemented by JBIG2.
  • the functions of the context generator and the model unit are the same as those of the encoder.
  • the decoder inputs the input data CD, key data K, index l (GX), and MPS, and basically performs the reverse process of the encoder to decode the data a. Outputs information on whether or not is MPS.
  • FIG. 40 is a flowchart showing the entire decoding process in the decompression decoder.
  • initialization processing IITDEC
  • context CX is read from the context generator.
  • S202 a decoding process of a 1-bit symbol a i described later is performed.
  • FIG. 41 is a flowchart showing the initialization processing (INITDEG) of S200.
  • BPST initial value of the read address value
  • BYTE IN byte unit read processing
  • FIG. 42 is a flowchart showing the decoding process (DECODE) of the 1-bit symbol ai of S202.
  • DECODE decoding process
  • perturbation processing shown in Fig. 32
  • CQe is obtained.
  • 1-bit read k r from the key data K in the S 2 2 1.
  • S222 it is determined whether kr is 1 or not. If the determination result is affirmative, the process proceeds to S224, but if negative, the process proceeds to S223.
  • CQ e is substituted for RepQe.
  • S2224 (A—CQe) is substituted for RepQe.
  • S 2 229 it is determined whether the logical product of A and hex hexadecimal 8000 is 0 or not. 3 Move to 2.
  • decoding processing MPS_EXCHANGE DECRYPT
  • a is obtained.
  • section width normalization processing REN0RMD
  • S 2 32 In this case, the value of MPS (CX) is assigned to ai.
  • FIG. 43 is a flowchart showing a decoding process (LPS_EXGHANGE DECRYPT) of S234. This process is performed when a 1-bit symbol is decoded as LPS.
  • LPS_EXGHANGE DECRYPT a decoding process
  • CQ e is substituted into A
  • the value of MPS (CX) is substituted into ai with reference to the context learning table
  • NMPS d (CX) obtained from the state transition table is obtained. It is assigned to index I (GX), and the context learning table is updated.
  • FIG. 44 is a flowchart showing the decoding processing (MPS—EXCHANGE DECRYPT) of S230.
  • This process is the process when 1-bit symbol is decoded as MPS.
  • S250 it is determined whether or not A is smaller than CQ e.If the determination result is affirmative, the process proceeds to S251, but if not, the process proceeds to S252. I do.
  • S251 the value of MPS (GX) is substituted for ai with reference to the context learning table, and the NMPS (I (CX)) obtained from the state transition table is indexed.
  • FIG. 45 is a flowchart showing the section width normalization processing (REN0RMD) of S231 and S235. In S260, it is determined whether or not CT is 0.
  • FIG. 46 is a flowchart showing the byte unit read processing (BYTE IN) of S261.
  • B the value indicated by the file pointer BP
  • FF the value indicated by the file pointer BP
  • S271 it is determined whether B1 (the value indicated by address BP + 1) is larger than 8F in hexadecimal, and if the determination result is positive, the process proceeds to S273. However, if not, the flow shifts to S272. In S272, 1 is added to BP, B is shifted to the left by 9 bits, added to C, and CT is set to 7. In S2273, FF00 is added to C in hexadecimal, and CT is set to 8. In S274, 1 is added to BP, B is shifted left by 8 bits, added to C, and CT is set to 8. Industrial applicability
  • the appearance probability of a symbol is input from a model device, and a dynamic piecewise linear map based on the input symbol occurrence probability is controlled with a cryptographic key to compress and compress an output code. Because it is configured to encrypt, when data compression and encryption are performed simultaneously using arithmetic coding, high security can be obtained without impairing the original data compression rate due to arithmetic coding. An effect is obtained that a possible arithmetic type compression encryption device is obtained. In addition, since the position of the dynamic piecewise linear mapping is replaced with the encryption key to disturb the output code, an arithmetic compression encryption device capable of efficiently disturbing the output code with simple processing is obtained. The effect is that it can be done.
  • the output code is disturbed by perturbing the slope of the dynamic piecewise linear map with the encryption key, the output code can be efficiently disturbed without excessively decreasing the encoding efficiency. An effect is obtained that an arithmetic compression encryption device can be obtained.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

Selon l'invention, l'appareil de cryptage à compression arithmétique concerné est un codeur arithmétique qui code un symbole de sortie à partir d'un dispositif modèle pour prévoir la probabilité d'apparition de ce symbole, commande une correspondance linéaire en sections dynamique en fonction de la probabilité d'apparition d'un symbole d'entrée au moyen de clés de cryptage, comprime et crypte un code de sortie. Cet appareil de cryptage à compression arithmétique permet d'atteindre une haute sécurité, sans que le taux de compression de données intrinsèque soit affecté par un codage arithmétique. Un code de sortie est perturbé efficacement au moyen d'un simple traitement.
PCT/JP2002/000365 2001-01-22 2002-01-21 Appareil, procede et programme de cryptage a compression arithmetique WO2002058038A1 (fr)

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CN100390698C (zh) * 2004-11-04 2008-05-28 白根弟 防止木马或病毒窃取输入信息的方法
JP2014109697A (ja) * 2012-12-03 2014-06-12 Nippon Telegr & Teleph Corp <Ntt> 符号化装置、方法、プログラム及び記録媒体
JP7023584B2 (ja) 2018-09-26 2022-02-22 東芝情報システム株式会社 公開鍵暗号システム、公開鍵暗号方法、公開鍵暗号プログラム
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CN100390698C (zh) * 2004-11-04 2008-05-28 白根弟 防止木马或病毒窃取输入信息的方法
JP2014109697A (ja) * 2012-12-03 2014-06-12 Nippon Telegr & Teleph Corp <Ntt> 符号化装置、方法、プログラム及び記録媒体
JP7023584B2 (ja) 2018-09-26 2022-02-22 東芝情報システム株式会社 公開鍵暗号システム、公開鍵暗号方法、公開鍵暗号プログラム
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CN114419719B (zh) * 2022-03-29 2022-08-12 北京爱笔科技有限公司 一种生物特征的处理方法及装置

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JPWO2002058039A1 (ja) 2004-05-27
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JPWO2002058038A1 (ja) 2004-05-27
WO2002058039A1 (fr) 2002-07-25

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