WO2002056586A2 - Systeme perfectionne d'enregistrement et de reproduction numerique de medias - Google Patents

Systeme perfectionne d'enregistrement et de reproduction numerique de medias Download PDF

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Publication number
WO2002056586A2
WO2002056586A2 PCT/CA2002/000039 CA0200039W WO02056586A2 WO 2002056586 A2 WO2002056586 A2 WO 2002056586A2 CA 0200039 W CA0200039 W CA 0200039W WO 02056586 A2 WO02056586 A2 WO 02056586A2
Authority
WO
WIPO (PCT)
Prior art keywords
digital
set forth
playback
digital information
interface
Prior art date
Application number
PCT/CA2002/000039
Other languages
English (en)
Other versions
WO2002056586A3 (fr
Inventor
Hui Zhao
Original Assignee
Video Links International
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Video Links International filed Critical Video Links International
Priority to AU2002226216A priority Critical patent/AU2002226216A1/en
Publication of WO2002056586A2 publication Critical patent/WO2002056586A2/fr
Publication of WO2002056586A3 publication Critical patent/WO2002056586A3/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/79—Processing of colour television signals in connection with recording
    • H04N9/80—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
    • H04N9/804—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving pulse code modulation of the colour picture signal components
    • H04N9/8042—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving pulse code modulation of the colour picture signal components involving data reduction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/907—Television signal recording using static stores, e.g. storage tubes or semiconductor memories

Definitions

  • the present invention relates to an advanced digital media system (ADMS) and more particularly, the present invention relates to a system and method of digital storage and playback of high quality video clips.
  • ADMS advanced digital media system
  • This invention relates generally to digital multimedia and digital storage technologies, and specifically to a system of high quality video playback.
  • the present invention has applicability in the digital media art. DISCLOSURE OF THE INVENTION
  • the present invention addresses and satiates the restrictions inherent with the prior art.
  • an improved digital media system and method of storing and playing digital signals in pure digital form is provided.
  • the instant system uses pure digital technology.
  • the video playback involves digital video storage, digital video processing and digital video display.
  • the system is absent any analog to digital or digital to analog conversion to therefore avoid degradation in signal quality.
  • the system is also noise tolerable.
  • a further object of one embodiment of the present invention is to provide a digital media system, comprising: a) a microprocessor; b) audio video decoding means; c) display means for displaying decoded video signals and playback decoded audio signals; d) interface means for interfacing storage means and the display means; e) storage means for storing audio and video signals; and f) a system bus for interfacing components a) through f).
  • the system incorporates flash memory, a solid state non-volatile device not limited by the disadvantages noted above.
  • suitable storage devices include compact flash, internet storage, microdrive hard drive or any other suitable storage arrangement capable of storing digital information/signals.
  • a further object of one embodiment of the present invention is to provide a digital media system, comprising: digital information storage means for storing digital information; digital playback means for playing back stored digital information; and digital interface means for interfacing the digital information and the digital playback means, whereby the digital information is retained in a pure digital form from storage to playback.
  • the invention has unified components capable of creating digital playback of MPEG 2 from flash memory for display on a TFT display. This amalgamation has previously not been proposed, since complex architecture problems arise when components with moving parts are replaced entirely with nonmoving or solid state components. Furthermore, simple substitution of components does not result in an operable system.
  • another object of one embodiment of the present invention is to provide a method for storage and playback of a pure digital signal, comprising: providing digital information storage means for storing digital information, digital playback means for playing back stored digital information and digital interface means for interfacing the digital information and the digital playback means; providing an audio video decoder in the playback means; interfacing the audio video decoder directly with the digital playback means; storing digital information; and playing back stored digital information in pure digital form.
  • system interface may be a PCMCIA, USB or FirewireTM or other suitable arrangement.
  • Alternatives for the storage means have been indicated and it will be understood by those skilled that several of a certain type of storage device may be used in appropriate connection or a series of different types may be used.
  • TFT TFT
  • plasma plasma
  • projection etc.
  • Figure 1 is a schematic illustration of one embodiment of the system according to the present invention
  • Figure 2 is a schematic illustration of the process according to one embodiment of the invention
  • Figure 3 is a schematic illustration of a further embodiment of the system according to the present invention.
  • Figure 4 is a schematic of a still further embodiment of the system according to the present invention.
  • the ADMS architecture includes a microprocessor (12) connected to a system bus (11), along with at least one or more video decoders (13), one TFT display controller (14), and one PCMCIA interface adaptor (15).
  • the microprocessor (12) is preferably formed primarily on a single integrated circuit chip. It is connected to the system bus (11), which includes address, data, and control lines. Peripheral chips which may complement the system include ROM, SRAM, input/output devices, i.e. none of which is shown.
  • the microprocessor (12) is the controller of the system, which controls the process as illustrated in Figure 2. Suitable microprocessors which may be used include any microprocessor such as IntelTM i960 series, IntelTM StrongArm series, IntelTM Pentium series, MotorolaTM 68K series, MotorolaTM PowerPC series, AMD K7 series, etc.
  • the audio/video decoder (13) is connected to the system bus (not shown). Ancillary chips may be used in conjunction, such as SDRAM, audio D/A converter, (not shown).
  • the decoder decodes and plays back the audio/video data sent to it by the microprocessor (12).
  • the audio/video decoder is preferably formed primarily on at least one integrated circuit chip.
  • one MPEG2 decoder that is used in the system can decode MPEG2 and MPEG1 audio/video data.
  • the choice of the decoder is not limited; suitable examples include SigmaTM Designs EM8400 series, LSITM Logic's L64020/L64021, C-Cube'sTM ZiVA-3v, IBMTM CS24 series, etc.
  • the TFT controller (14) is connected to the system bus (11 ). Auxiliary chips may also be used with it, such as an SDRAM (not shown).
  • the controller provides video acceleration for display, such as frame buffer controlling, YUV to RGB conversion, horizontal/vertical interpolation, screen refreshing, etc.
  • the TFT (14) controller is preferably formed primarily on an integrated circuit chip and any TFT controller may be may be used in the system, such as AsiliantTM 69000/s69030, ATITM Rage LT Pro, NeoMagicTM 256AV, Trident CyberTM 9397, etc.
  • the PCMCIA adaptor (15) is connected to bus (11 ).
  • the PCMCIA adaptor provides an interface to external storage device with PCMCIA interface, such as flash memory card and IBMTM microdrive, etc.
  • the PCMCIA adaptor (15) is preferably formed primarily on an integrated circuit chip. Suitable interface chips include such as TlTM PCI1451A, IntelTM 82092, CirrusTM CL-PD6710/20/30, etc.
  • the system bus (11 ) is the signaling bus connecting all the components. It provides data lines, address lines, and control lines among the components.
  • the components (12,13,14,15) and the system bus (11) follow the same bus standard and are interfaced as indicated by numeral 21.
  • the interface (22) between external storage device (17) and PCMCIA adaptor (16) is a PCMCIA interface. All the storage devices following the PCMCIA interface could be used in the system, including PC-CardTM, SmartCardTM, CompactCardTM, etc.
  • the specific storage media could be linear flash memory, ATA flash memory, small hard drives such as IBMTM microdrive, etc.
  • the interface (23) between the audio/video decoder (13) and the TFT controller (14) is a digital video interface, such as YUV or RGB.
  • the interface (24) between the TFT controller (14) and TFT screen (16) is a digital interface. If the TFT screen is integrated with the system, the interface would comprise a digital RGB interface; if the TFT screen is separate from the system, the interface could be selected from TMDS, LVDS, or GVIF. Referring now to Figure 3 shown is an implementation of present invention with of all the components listed in Figure 1.
  • the system bus (11) comprises a PCI Bus connected to a Microprocessor (12) which may comprise an IntelTM i960VH.
  • the A/V Decoder (13) may comprise a SigmaTM Designs EM840X1 C interconnected with a TFT controller (14) such as an AsiliantTM 69030.
  • a suitable example is a TlTM PCI1451A CardBusTM-PCI bridge connected to an integrated TFT monitor (16) connected to an LG LM151X2.
  • the components interface (21 ) may comprise a PCI Interface and Storage Interface (22) connected to a CardBusTM of PCMCIA standard.
  • Video interface (23) comprises a Digital YUV connected to a display ilnterface (24) connected to digital RGB.
  • the TFT monitor is external, so an LVDS transmitter chip (16) is used to interface to an external TFT monitor with LVDS interface.
  • the LVDS transmitter is DS90C385 of National Semiconductor.
  • the invention set forth herein provides a shock and weather resistant device which is also portable, effectively self-contained and operable under temperature extremes normally encountered outdoors.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

L'invention concerne un système et un procédé d'enregistrement et de reproduction numérique de médias. Ce système se compose d'un microprocesseur relié à un décodeur audio et vidéo, d'un écran destiné à l'affichage des signaux vidéo décodés et à la reproduction des signaux audio décodés, d'une interface destinée à relier un support d'enregistrement permettant d'enregistrer les signaux audio et vidéo à l'écran et d'un bus système destiné à relier tous les composants du système.
PCT/CA2002/000039 2001-01-09 2002-01-09 Systeme perfectionne d'enregistrement et de reproduction numerique de medias WO2002056586A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002226216A AU2002226216A1 (en) 2001-01-09 2002-01-09 Digital media system

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US26021101P 2001-01-09 2001-01-09
US60/260,211 2001-01-09
US31882201P 2001-09-14 2001-09-14
US60/318,822 2001-09-14

Publications (2)

Publication Number Publication Date
WO2002056586A2 true WO2002056586A2 (fr) 2002-07-18
WO2002056586A3 WO2002056586A3 (fr) 2003-02-27

Family

ID=26947801

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2002/000039 WO2002056586A2 (fr) 2001-01-09 2002-01-09 Systeme perfectionne d'enregistrement et de reproduction numerique de medias

Country Status (2)

Country Link
AU (1) AU2002226216A1 (fr)
WO (1) WO2002056586A2 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5864554A (en) * 1993-10-20 1999-01-26 Lsi Logic Corporation Multi-port network adapter
US6154600A (en) * 1996-08-06 2000-11-28 Applied Magic, Inc. Media editor for non-linear editing system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5864554A (en) * 1993-10-20 1999-01-26 Lsi Logic Corporation Multi-port network adapter
US6154600A (en) * 1996-08-06 2000-11-28 Applied Magic, Inc. Media editor for non-linear editing system

Also Published As

Publication number Publication date
AU2002226216A1 (en) 2002-07-24
WO2002056586A3 (fr) 2003-02-27

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