WO2002054175A3 - Quad aware locking primitive - Google Patents

Quad aware locking primitive Download PDF

Info

Publication number
WO2002054175A3
WO2002054175A3 PCT/US2001/049529 US0149529W WO02054175A3 WO 2002054175 A3 WO2002054175 A3 WO 2002054175A3 US 0149529 W US0149529 W US 0149529W WO 02054175 A3 WO02054175 A3 WO 02054175A3
Authority
WO
WIPO (PCT)
Prior art keywords
lock
primitive
processor
utilized
computer system
Prior art date
Application number
PCT/US2001/049529
Other languages
French (fr)
Other versions
WO2002054175A2 (en
Inventor
Paul Edward Mckenney
Benedict Jackson
Ramakrishnan Rajamony
Ronald L Rockhold
Original Assignee
Ibm
Paul Edward Mckenney
Benedict Jackson
Ramakrishnan Rajamony
Ronald L Rockhold
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm, Paul Edward Mckenney, Benedict Jackson, Ramakrishnan Rajamony, Ronald L Rockhold filed Critical Ibm
Priority to AU2002235235A priority Critical patent/AU2002235235A1/en
Priority to JP2002554808A priority patent/JP4051284B2/en
Priority to PL01365899A priority patent/PL365899A1/en
Priority to HU0302546A priority patent/HUP0302546A3/en
Priority to IL15652201A priority patent/IL156522A0/en
Priority to EP01985598A priority patent/EP1358529A4/en
Publication of WO2002054175A2 publication Critical patent/WO2002054175A2/en
Publication of WO2002054175A3 publication Critical patent/WO2002054175A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. The method organizes at least some of the processors in the system into a hierarchy (910, 920), and processes an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive (800) and an unconditional lock acquisition primitive (600), and an unconditional lock release primitive for releasing the lock from a particular processor. In order to prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized. Accordingly, efficiency of a computer system may be enhanced with the ability to utilize a locking primitive for an interruptible lock that determines lock selection among processors based upon a hierarchical position of the processor and the primitive utilized for lock selection.
PCT/US2001/049529 2000-12-28 2001-12-28 Quad aware locking primitive WO2002054175A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
AU2002235235A AU2002235235A1 (en) 2000-12-28 2001-12-28 Quad aware locking primitive
JP2002554808A JP4051284B2 (en) 2000-12-28 2001-12-28 Quad recognition lock primitive
PL01365899A PL365899A1 (en) 2000-12-28 2001-12-28 Quad aware locking primitive
HU0302546A HUP0302546A3 (en) 2000-12-28 2001-12-28 Method for effeciently handling high contention looking in a multiprocessor computer system and computer program for implementing the method
IL15652201A IL156522A0 (en) 2000-12-28 2001-12-28 Quad aware locking primitive
EP01985598A EP1358529A4 (en) 2000-12-28 2001-12-28 Quad aware locking primitive

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/753,062 2000-12-28
US09/753,062 US7500036B2 (en) 2000-12-28 2000-12-28 Quad aware locking primitive

Publications (2)

Publication Number Publication Date
WO2002054175A2 WO2002054175A2 (en) 2002-07-11
WO2002054175A3 true WO2002054175A3 (en) 2003-01-03

Family

ID=25028992

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/049529 WO2002054175A2 (en) 2000-12-28 2001-12-28 Quad aware locking primitive

Country Status (10)

Country Link
US (2) US7500036B2 (en)
EP (1) EP1358529A4 (en)
JP (2) JP4051284B2 (en)
AU (1) AU2002235235A1 (en)
CZ (1) CZ20031814A3 (en)
HU (1) HUP0302546A3 (en)
IL (1) IL156522A0 (en)
PL (1) PL365899A1 (en)
TW (1) TWI238944B (en)
WO (1) WO2002054175A2 (en)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6842809B2 (en) * 2001-04-12 2005-01-11 International Business Machines Corporation Apparatus, method and computer program product for converting simple locks in a multiprocessor system
US6892260B2 (en) * 2001-11-30 2005-05-10 Freescale Semiconductor, Inc. Interrupt processing in a data processing system
US7529844B2 (en) * 2002-04-26 2009-05-05 Sun Microsystems, Inc. Multiprocessing systems employing hierarchical spin locks
US7779417B2 (en) * 2005-10-25 2010-08-17 Oracle International Corporation Method and apparatus for making inter-process procedure calls through shared memory
US7949815B2 (en) * 2006-09-27 2011-05-24 Intel Corporation Virtual heterogeneous channel for message passing
US8145903B2 (en) * 2007-05-25 2012-03-27 Red Hat, Inc. Method and system for a kernel lock validator
US8707315B2 (en) * 2008-07-31 2014-04-22 Wind River Systems, Inc. Method and system for implementing realtime spinlocks
US9262235B2 (en) * 2011-04-07 2016-02-16 Microsoft Technology Licensing, Llc Messaging interruptible blocking wait with serialization
US8930952B2 (en) * 2012-03-21 2015-01-06 International Business Machines Corporation Efficient lock hand-off in a symmetric multiprocessing system
US8694706B2 (en) 2012-04-27 2014-04-08 Oracle International Corporation System and method for NUMA-aware locking using lock cohorts
US8966491B2 (en) 2012-04-27 2015-02-24 Oracle International Corporation System and method for implementing NUMA-aware reader-writer locks
US9197520B2 (en) * 2013-03-15 2015-11-24 Microsoft Technology Licensing, Llc Methods and computer program products for transaction analysis of network traffic in a network device
US9396226B2 (en) 2013-06-24 2016-07-19 International Business Machines Corporation Highly scalable tree-based trylock
US9817703B1 (en) * 2013-12-04 2017-11-14 Amazon Technologies, Inc. Distributed lock management using conditional updates to a distributed key value data store
US9378069B2 (en) 2014-03-05 2016-06-28 International Business Machines Corporation Lock spin wait operation for multi-threaded applications in a multi-core computing environment
US9996402B2 (en) 2014-04-07 2018-06-12 Oracle International Corporation System and method for implementing scalable adaptive reader-writer locks
JP2018180768A (en) * 2017-04-07 2018-11-15 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2019067289A (en) * 2017-10-04 2019-04-25 ルネサスエレクトロニクス株式会社 Semiconductor apparatus
GB201810644D0 (en) * 2018-06-28 2018-08-15 Microsoft Technology Licensing Llc Managing global and local execution phases
US10929199B2 (en) 2018-07-02 2021-02-23 International Business Machines Corporation Memory lock serialization
US10740159B2 (en) * 2018-07-24 2020-08-11 EMC IP Holding Company LLC Synchronization object prioritization systems and methods

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4975833A (en) * 1986-07-15 1990-12-04 Fujitsu Limited Multiprocessor system which only allows alternately accessing to shared memory upon receiving read and write request signals
US5175829A (en) * 1988-10-25 1992-12-29 Hewlett-Packard Company Method and apparatus for bus lock during atomic computer operations
US5319780A (en) * 1987-10-19 1994-06-07 International Business Machines Corporation System that implicitly locks a subtree or explicitly locks a node based upon whether or not an explicit lock request is issued
US5432915A (en) * 1987-05-16 1995-07-11 Nec Corporation Interprocessor communication system in an information processing system enabling communication between execution processor units during communication between other processor units
US5778441A (en) * 1994-03-01 1998-07-07 Intel Corporation Method and apparatus for accessing split lock variables in a computer system
US6338112B1 (en) * 1997-02-21 2002-01-08 Novell, Inc. Resource management in a clustered computer system

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02129742A (en) 1988-11-10 1990-05-17 Fujitsu Ltd Method for detecting abnormality in address signal to memory
JPH02170259A (en) 1988-12-23 1990-07-02 Nec Corp Control system for shared resources of multiprocessor system
JPH03245257A (en) 1990-02-23 1991-10-31 Nec Corp Acquisition method for ownership of multiprocessor system resources
US5669002A (en) * 1990-06-28 1997-09-16 Digital Equipment Corp. Multi-processor resource locking mechanism with a lock register corresponding to each resource stored in common memory
US6282583B1 (en) * 1991-06-04 2001-08-28 Silicon Graphics, Inc. Method and apparatus for memory access in a matrix processor computer
JPH05225149A (en) 1992-02-13 1993-09-03 Toshiba Corp Lock system
JPH05257902A (en) 1992-03-10 1993-10-08 Fujitsu Ltd Lock acquisition processing system in processing program mode
US5596754A (en) * 1992-10-29 1997-01-21 Digital Equipment Corporation Method for performing private lock management
US5515516A (en) * 1994-03-01 1996-05-07 Intel Corporation Initialization mechanism for symmetric arbitration agents
JP3059098B2 (en) 1996-01-31 2000-07-04 株式会社東芝 Multiprocessor system
JPH10161985A (en) 1996-11-28 1998-06-19 Hitachi Ltd Processor allocating method, and multiprocessor computer system
US5895492A (en) * 1997-05-28 1999-04-20 International Business Machines Corporation Processor associated blocking symbol controls for serializing the accessing of data resources in a computer system
US6163831A (en) * 1997-11-14 2000-12-19 Lucent Technologies, Inc. Minimum refractory period in a multiple agent resource sharing environment
JPH11170259A (en) 1997-12-12 1999-06-29 Saito Kanagata Seisakusho:Kk Method for molding ball for ball game, molding device, and ball for ball game
US6141733A (en) * 1998-02-17 2000-10-31 International Business Machines Corporation Cache coherency protocol with independent implementation of optimized cache operations
JP3546694B2 (en) 1998-03-31 2004-07-28 日本電気株式会社 Multi-thread computer system and multi-thread execution control method
US6389519B1 (en) * 1999-07-19 2002-05-14 Ati International Srl Method and apparatus for providing probe based bus locking and address locking
JP2001095350A (en) 1999-09-27 2001-04-10 Kubota Corp Chain tensioner of reaping machine
JP2001108290A (en) 1999-10-04 2001-04-20 Takenaka Komuten Co Ltd Floor structure for spectator seats in tiers
US6473819B1 (en) * 1999-12-17 2002-10-29 International Business Machines Corporation Scalable interruptible queue locks for shared-memory multiprocessor
US6823511B1 (en) * 2000-01-10 2004-11-23 International Business Machines Corporation Reader-writer lock for multiprocessor systems
US6651146B1 (en) * 2000-02-24 2003-11-18 International Business Machines Corporation Method and apparatus for managing access contention to a linear list without the use of locks
US6742135B1 (en) * 2000-11-07 2004-05-25 At&T Corp. Fault-tolerant match-and-set locking mechanism for multiprocessor systems
US6792497B1 (en) * 2000-12-12 2004-09-14 Unisys Corporation System and method for hardware assisted spinlock
US20020073260A1 (en) * 2000-12-12 2002-06-13 Kuang-Shin Lin Method for preventing processes between processors from conflicting in a multiprocessor based computer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4975833A (en) * 1986-07-15 1990-12-04 Fujitsu Limited Multiprocessor system which only allows alternately accessing to shared memory upon receiving read and write request signals
US5432915A (en) * 1987-05-16 1995-07-11 Nec Corporation Interprocessor communication system in an information processing system enabling communication between execution processor units during communication between other processor units
US5319780A (en) * 1987-10-19 1994-06-07 International Business Machines Corporation System that implicitly locks a subtree or explicitly locks a node based upon whether or not an explicit lock request is issued
US5175829A (en) * 1988-10-25 1992-12-29 Hewlett-Packard Company Method and apparatus for bus lock during atomic computer operations
US5778441A (en) * 1994-03-01 1998-07-07 Intel Corporation Method and apparatus for accessing split lock variables in a computer system
US6338112B1 (en) * 1997-02-21 2002-01-08 Novell, Inc. Resource management in a clustered computer system

Also Published As

Publication number Publication date
WO2002054175A2 (en) 2002-07-11
JP4750074B2 (en) 2011-08-17
US20020087769A1 (en) 2002-07-04
US7500036B2 (en) 2009-03-03
HUP0302546A2 (en) 2003-10-28
AU2002235235A1 (en) 2002-07-16
EP1358529A4 (en) 2008-06-04
TWI238944B (en) 2005-09-01
US20090063826A1 (en) 2009-03-05
CZ20031814A3 (en) 2003-10-15
PL365899A1 (en) 2005-01-10
HUP0302546A3 (en) 2004-12-28
EP1358529A2 (en) 2003-11-05
US7979617B2 (en) 2011-07-12
IL156522A0 (en) 2004-01-04
JP4051284B2 (en) 2008-02-20
JP2007265426A (en) 2007-10-11
JP2004523032A (en) 2004-07-29

Similar Documents

Publication Publication Date Title
WO2002054175A3 (en) Quad aware locking primitive
JPS5443644A (en) Processing system for deadlock automatic release at exclusive control time
WO2003009093A3 (en) System and method for transaction processing with synchronized callback processing feature
EP0945797A3 (en) Method and apparatus for object-oriented interrupt system
CA2522814A1 (en) Managing locks and transactions
WO1990014629A3 (en) Parallel multithreaded data processing system
EP0932101A3 (en) A method, apparatus and computer program product for locking interrelated data structures in a multi-threaded computing environment
EP0953906A3 (en) Method and apparatus for detecting input directed to a thread in a multi-threaded process
EP1435572A3 (en) Method and apparatus for providing dynamic locks for resources
JPS5326539A (en) Data exchenge system
ES2140241T3 (en) PROCEDURE FOR THE SYNCHRONIZATION OF PROGRAMS IN DIFFERENT COMPUTERS OF AN INTEGRATED SYSTEM.
EP0955584A3 (en) Fast synchronization for programs written in the java programming language
EP0973093A3 (en) Method of and apparatus for processing information, and providing medium
JPS5429542A (en) Information processing system
JPS5534316A (en) Store buffer control system
JPS54107647A (en) Data processor
Stevens Data collection: An essential complement to MRP II.
Bussard Nuclear rocketry- The first bright hopes
JPS5574656A (en) Control unit for information processing system
Zhou et al. Multimode image compression method based on a normalized standard image
JPS54119123A (en) Piping cramping lag
JPS52143543A (en) Manufacturing system of wave-like fin
McGrath Comparative analysis of the national liberation movements in Northern Ireland, South Africa, and Algeria with specific reference to the development and interrelationship of political ideology and military strategy
ANDERSON NASA-Johnson Space Center
Rossello et al. Deriving specifications of embeddings in recursive program design.

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 156522

Country of ref document: IL

WWE Wipo information: entry into national phase

Ref document number: 2002554808

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: PV2003-1814

Country of ref document: CZ

WWE Wipo information: entry into national phase

Ref document number: 2001985598

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: PV2003-1814

Country of ref document: CZ

WWP Wipo information: published in national office

Ref document number: 2001985598

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642