JPH10161985A - Processor allocating method, and multiprocessor computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate useless data transfer between caches and to improve the execution efficiency of a computer system as a whole. SOLUTION: An instruction string 505 for accessing shared data is sandwiched by a lock acquiring procedure 404 and a lock releasing procedure 406 and any processor is designated by a 2nd argument flag of the lock acquiring procedure 404. A multiprocessor computer system allocates a process for executing the instruction string 505 sandwiched by the lock acquiring procedure 404 and the lock releasing procedure 406 to the processor designated by the 2nd argument flag of the lock acquiring procedure 404. Since the plural processes for accessing the shared data are allocated to the same processor, there is no useless data transfer between caches and the execution efficiency of the entire system can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor allocation method and a multiprocessor computer system, and more particularly, to a processor allocation method and a multiprocessor computer system capable of reducing the number of data transfers between caches and improving the execution efficiency of the entire system. The present invention relates to a processor computer system.

[0002]

2. Description of the Related Art In a multiprocessor computer system having a plurality of processors and caches respectively corresponding to the processors, when a plurality of processes allocated to different processors access the shared data, the shared data must be kept consistent. The control for moving the shared data between the caches of the different processors is performed. For details of such control, see "UNIX Kernel Internal Analysis Cache and Multiprocessor Management, C. Sc
himmel, translated by Maekawa Mamoru, translated by Iwamoto Shinichi, Softbank Corp., pp. 293-327. "

[0003]

In the case of performing control for moving shared data between caches of different processors,
For example, if the processes assigned to different processors alternately write data to the shared data, the number of data transfers between caches increases and the execution efficiency of the entire computer system decreases. Therefore, an object of the present invention is to provide a processor allocation method and a multiprocessor computer system capable of reducing the number of data transfers between caches and improving the execution efficiency of the entire system.

[0004]

According to a first aspect, the present invention is a processor allocation method in a multiprocessor computer system having a plurality of processors and caches respectively corresponding to the processors, wherein the plurality of processes are shared. When accessing data, a processor allocation method is characterized in that these processes are allocated to the same processor. In the above processor allocation method, since a plurality of processes accessing the shared data are allocated to the same processor, useless data transfer between caches is eliminated, and the execution efficiency of the entire system can be improved. When there are a plurality of shared data, a load can be distributed by associating a different processor with each shared data.

According to a second aspect, the present invention is a processor allocation method in a multiprocessor computer system having a plurality of processors and caches respectively corresponding to the processors, wherein a processor is designated before an instruction sequence. A mutual exclusion start instruction is arranged, and after the instruction sequence, a mutual exclusion end instruction capable of canceling the designation of the processor is arranged. If a processor is specified by the mutual exclusion start instruction, the specified processor The instruction sequence sandwiched between the mutual exclusion start instruction and the mutual exclusion end instruction is executed, and if a processor is not specified by the mutual exclusion start instruction, the processor starts the mutual exclusion start instruction and the mutual exclusion end by any processor. A method for allocating a processor, comprising executing the instruction sequence sandwiched by instructions, is provided. In the above processor allocation method, the instruction sequence for accessing the shared data is sandwiched between the mutual exclusion start instruction and the mutual exclusion end instruction, and the processor is specified by the mutual exclusion start instruction. Can be assigned.
Therefore, useless data transfer between caches is eliminated, and the execution efficiency of the entire system can be improved. When there are a plurality of instruction sequences for accessing the shared data, the load can be distributed by specifying a different processor for each instruction sequence. In the above configuration, the processor may be specified by specifying the processor number or by causing the multiprocessor computer system to select one processor.
In the latter case, for example, the multiprocessor computer system selects a processor based on the number of the processor that has executed the mutual exclusion start instruction, or selects a processor corresponding to the cache in which the shared data currently exists.

According to a third aspect, the present invention provides a multiprocessor computer system having a plurality of processors and caches respectively corresponding to the processors.
When the processor is specified by the mutual exclusion start instruction, the instruction following the mutual exclusion start instruction is executed by the specified processor, and when the mutual exclusion end instruction is executed, the arbitrary exclusion is performed by any processor. There is provided a multiprocessor computer system comprising a processor assignment control means for executing an instruction following an end instruction. In the above-mentioned multiprocessor computer system, the instruction sequence for accessing the shared data in the program is sandwiched between the mutual exclusion start instruction and the mutual exclusion end instruction, and the processor is designated by the mutual exclusion start instruction, so that the process of accessing the shared data is the same Of processors. Therefore, useless data transfer between caches is eliminated, and the execution efficiency of the entire system can be improved. When there are a plurality of instruction sequences for accessing the shared data, the load can be distributed by specifying a different processor for each instruction sequence. In the above configuration, the processor may be specified by specifying the processor number or by causing the multiprocessor computer system to select one processor. In the latter case, the processor allocation control means selects a processor based on, for example, the number of the processor that has executed the mutual exclusion start instruction, or selects a processor corresponding to the cache in which the shared data currently exists.

[0007]

FIG. 1 is a block diagram of a multiprocessor computer system 101 according to one embodiment of the present invention. This multiprocessor computer system 101
Indicates a plurality of processors 102 (1) to 102 (N) and cache memories 103 (1) to 103 (103) for each processor.
(N), a secondary storage device 104 such as a magnetic disk for storing instruction sequences and data, a main memory 106, and a system bus 105.

In the main memory 106, program storage areas 120 (1) to 120 (L) to be executed by the processor 102 are stored.
And a process management table 117 for managing the process
A running process management table 116 for managing processes running on the processors 102 (1) to 102 (N);
An executable process list 118 that manages, in a list structure, processes that are not yet allocated to the processors 102 (1) to 102 (N) but are in an executable state, and are allocated to the processors 102 (1) to 102 (N). A process switching procedure storage area 119 for storing a procedure for switching processes, and a mutual exclusion for preventing other processes from reading and writing the shared data in order to maintain consistency of data shared by a plurality of processes. Lock data storage area 110 (1) to (M) for storing information
A lock initialization procedure storage area 107 for storing procedures for initializing the lock data storage areas 110 (1) to 110 (M), and a procedure for instructing mutual exclusion in front of an instruction sequence for accessing shared data. There is a lock acquisition procedure storage area 108 for storing the lock release procedure storage area 109 for storing a procedure for instructing cancellation of mutual exclusion after an instruction sequence for accessing shared data.

The lock data storage area 110 (1)-
(M) includes a lock variable storage area 111 indicating whether the corresponding data is being mutually excluded, a lock acquisition flag storage area 112 indicating whether there is a process accessing the corresponding data, There is an allocated processor number storage area 113 for storing the number of the processor to which the process accessing the data to be allocated is allocated, and a standby process list 114 for managing a list of processes waiting for when the corresponding data can be accessed. .

FIG. 2 is a configuration diagram of the process management table 117. Each row of the process management table 117 corresponds to one process. Each row has an index 201 for storing a row number, a process number 202 for storing a process number corresponding to the row, an execution state 203 for storing a state of a process corresponding to the row, and a process corresponding to the row. Save area 204 for storing a storage area in which register information such as a program counter is saved when execution of the process is interrupted, and executable process list 1
A next process index 205 storing the line number (or the identifier END indicating the end of the list structure) of the link destination process used to create a list structure such as 18
And an assigned processor number 206 for storing the number of the processor to which the process corresponding to the row is assigned when the number is determined.

FIG. 3 shows the running process management table 116.
FIG. Each row of the running process management table 116 corresponds to each of the processors 102 (1) to 102 (N). Each row corresponds to the processor 102 corresponding to the row.
A processor number 301 for storing numbers (1 to N) of (1) to 102 (N) and a process number 3 for storing the number of a process executed by the processor 102 corresponding to the row
02.

FIG. 4 shows lock initialization 402, lock acquisition 404, and lock release 406, which are procedures called by the operating system to perform mutual exclusion.
FIG.

Lock initialization (procedure name init_lock) 40
2 takes the address idp of the variable storage area for returning the lock data identifier id as an argument. Then, it has a function of initializing the lock data storage area 110 and storing the lock data identifier id given to the initialized lock data storage area 110 in the variable storage area indicated by the address idp.

The lock acquisition (procedure name lock) 404 is the lock data identifier id obtained in the lock initialization 402.
As a first argument, and an identifier flag for specifying the type of function as a second argument. If the value of the identifier flag of the second argument is a processor number (1 to N), the process that accesses the data corresponding to the lock data identifier id is assigned to the processor number (1 to N). If -1 is assigned to one processor selected on the system side, and if the value of the identifier flag is -2, mutual exclusion and process scheduling similar to the semaphore provided in the prior art (process for selecting a process assigned to a processor) ) Is provided.
The semaphore implements mutual exclusion using a P instruction and a V instruction. For details of P and V instructions, see "Functions and Configuration of Operating System, Takahashi et al., Iwanami Shoten, 198
3, pp. 147-150 ”and“ UNIX Kernel Design,
Maurice / Sakamoto et al., Kyoritsu Shuppan, 1990, 334-
341 ". For details of process scheduling, see "Designing UNIX Kernel, Maurice
Author, Sakamoto et al., Kyoritsu Shuppan, 1990, 211-219
Page ".

The lock release (procedure name unlock) 406 is
The lock data identifier i obtained in the lock initialization 402
Let d be an argument. Then, it has a function of assigning a process that subsequently accesses data corresponding to the lock data identifier id to an arbitrary processor.

FIG. 5 is a view showing an example of a program instruction sequence including procedures of lock initialization 402, lock acquisition 404, and lock release 406. A lock acquisition 404 is placed before an instruction sequence 505 to be mutually excluded between a plurality of processes accessing the shared data, and a lock release 406 is placed after. And lock initialization 4 before lock acquisition 404
Put 02. Note that lock acquisition 404 and lock release 40
The instruction sequence 505 sandwiched between 6 is called a dangerous area.

FIG. 6 is a PAD diagram showing the processing of lock initialization 402. In step 601, a lock data storage area 110 is secured, and this is defined as a structure lock_data. The lock variable storage area 111, the lock acquisition flag storage area 112, the assigned processor number storage area 113, and the standby process list 114 of the lock data storage area 110 are members of the lock_data structure lock_data, respectively.
ybody, processor, and list. In step 602,
The members lock, anybody, processor, of the structure lock_data,
Set the initial value in list. Initial value of member lock FALSE
Means that the corresponding data is not mutually exclusive. The initial value NO_PROCESS of the member anybody means that no process is accessing the corresponding data.
The initial value -1 of the member "processor" means that the process for accessing the corresponding data is not assigned to the processor. The initial value of the member list is an identifier meaning empty (there is no standby process). Step 60
In 3, the lock data structure lock_data is given a lock data identifier id. In step 604, the lock data identifier id is stored in the variable storage area indicated by the argument address idp. In step 605, the process returns to the caller of the lock initialization 402.

FIG. 7 shows the process of lock acquisition 404.
It is an AD diagram. In step 701, a lock data structure lo corresponding to the lock data identifier id of the first argument
Get ck_data. In step 702, the value of the flag flag of the second argument is determined. If the value is 1 to N (processor number) or -1 (identifier for assigning a process to a certain processor), the process proceeds to step 703; Proceed to step 704. In step 703, a procedure for acquiring a new lock 703 is executed. This new lock acquisition 703
Will be described later with reference to FIG.

In steps 704 and 705, a TS (Test) which can read / write the memory indivisiblely by one instruction.
and Set) instructions to use the lock data structure lock
Set the value of the member lock of _data to true. Step 705 is processing to wait until the execution of the dangerous area is completed when another processor is executing the instruction sequence of the dangerous area. For details of the TS instruction, see "Functions and Configuration of Operating System, Takahashi et al., Iwanami Shoten, 1983, 1.
47 ". According to the TS instruction, the processing 2 of step 706 to step 707 or step 70
It is guaranteed that the processing up to the processing 2 of 9 is executed by only one processor.

In step 706, it is determined whether or not the value of the member anybody of the lock data structure lock_data is NO_PROCESS. If the value is NO_PROCESS (that is, if another process is not executing the instruction string 5 in the dangerous area) Proceed to step 707 and if the value is not NO_PROCESS (ie,
The process proceeds to step 709 (if another process is executing the instruction string in the dangerous area).

In step 707, in process 1, the value of member “anybody” of the lock data structure lock_data is set to EXIST
_PROCESS. In the process 2, the value of the member lock of the lock data structure lock_data is set to FALSE. In step 708, the process returns to the caller of the lock acquisition 404.

In step 709, in process 1, the own process is registered in the member list of the lock data structure lock_data, and the execution of the other process is waited. In process 2, the value of the member lock of the lock data structure lock_data is set to FALSE. In step 710, in process 1, the execution state 203 of the own process in the process management table 117 is set to “interrupted”. In process 2, the contents of the register of the processor executing the own process are saved, and the address of the saved area is stored in the register save area 204 of the process management table 117. In process 3, the process number of the own process is deleted from the running process management table 116. In step 711, the procedure of the process switching 711 is executed in order to allocate another process in the “executable” state to the processor that has executed the own process. The details of the process switching 711 will be described later with reference to FIG. In step 712, the process returns to the caller of the lock acquisition 404.

FIG. 8 is a PAD diagram showing the process of acquiring a new lock 703. In steps 801 and 802, a TS which can execute reading and writing to the memory indivisiblely by one instruction
An instruction is used to set the value of the member lock of the lock data structure lock_data to true. Step 802 is
If the other processor is executing the instruction sequence in the dangerous area, the process waits until the execution of the dangerous area is completed. According to the TS instruction, steps 801 to 80
The processing up to the processing 3 of step 8 or the processing 3 of step 812 is guaranteed to be executed by only one processor.

At step 803, the member processor of the lock data structure lock_data specified by the first argument
Is determined to be -1 or not, and if -1 (the process is not assigned to a processor), the process proceeds to step 804; otherwise, the process proceeds to step 807. Step 8
At 04, it is determined whether or not the value of the flag flag of the second argument is a processor number (1 to N), and the processor number (1 to N) is determined.
If the value of the flag is not a processor number (−1), the process proceeds to step 806. At step 805, the processor number (1 to N), which is the value of the flag, is set to a member of the lock data structure lock_data.
Set to the value of processor. Then, the process proceeds to step 807.

In step 806, the processor number to which the own process is assigned is stored in the running process management table 1
The processor number is checked, and the processor number is set to the value of the member processor of the lock data structure lock_data.
The number of the processor corresponding to the cache in which the shared data currently exists is checked, and the processor number is determined by the member processo of the lock data structure lock_data.
May be set to the value of r. Then, the process proceeds to step 807.

In step 807, it is determined whether or not the value of the member anybody of the lock data structure lock_data is NO_PROCESS. If the value is NO_PROCESS (that is, if another process is not executing the instruction sequence of the dangerous area) 8
08, if the value is not NO_PROCESS (that is, if another process is executing the instruction sequence in the dangerous area), the process proceeds to step 812.

In step 808, in process 1, the value of the member anybody of the lock data structure lock_data is set to EXIST
_PROCESS. In process 2, the value of the member processor of the lock data structure lock_data is set to the assigned processor number 206 of the process management table 117. In process 3, the value of the member lock of the lock data structure lock_data is set to FALSE. In step 809, it is determined whether or not the value of the member processor of the lock data structure lock_data and the processor number to which the own process is assigned do not match. If the values do not match, the process proceeds to step 810; In step 810, in process 1, the execution state 203 of the own process in the process management table 117 is set to “executable”. In process 2, the contents of the register of the processor executing the own process are saved, and the address of the saved area is stored in the process management table 11.
7 in the register save area 204. In process 3, the process number of the own process is registered in the executable process list 118. In process 4, the running process management table 116
From the process number of the own process. Step 7
In step 11, in order to allocate another “executable” process to the processor that was executing the process,
The procedure of the process switching 711 is executed. The details of the process switching 711 will be described later with reference to FIG. Then, the process proceeds to step 811. Step 81
At 1, the process returns to the caller of the new lock acquisition 703.

In step 812, in process 1, the own process is registered in the member list of the lock data structure lock_data, and the execution of another process is waited for. In process 2, the value of the member processor of the lock data structure lock_data is set to the assigned processor number 206 of the process management table 117. In process 3, the value of the member lock of the lock data structure lock_data is set to FALSE. In step 813, in process 1, the execution state 203 of the own process in the process management table 117 is set to “interrupted”. In process 2, the contents of the register of the processor executing the own process are saved, and the address of the saved area is stored in the register save area 204 of the process management table 117. In process 3, the process number of the own process is deleted from the running process management table 116. In step 711, the procedure of the process switching 711 is executed in order to allocate another process in the “executable” state to the processor that has executed the own process. The detailed contents of this process switching 711 are shown in FIG.
1 will be described later. In step 814, the process returns to the caller of the new lock acquisition 703.

FIG. 9 is a flowchart showing the process of lock release 406.
It is an AD diagram. In step 901, new lock release 9
Execute procedure 01. The details of the new lock release 911 will be described later with reference to FIG. Step 90
In step 2, a lock data structure lock_data corresponding to the lock data identifier id of the argument is obtained. Step 90
In 3,904, the value of the member lock of the lock data structure lock_data is set to true by using a TS instruction that can execute reading and writing to and from the memory inseparably with one instruction. Step 904 is processing to wait for the execution of the dangerous area when the instruction sequence of the dangerous area is being executed. The TS instruction guarantees that the processes from step 905 to step 906 or step 908 to step 2 are executed by only one processor.

In step 905, it is determined whether or not the member list of the lock data structure lock_data is empty. If the member list is empty (that is, if no other process is waiting), the process proceeds to step 906. If not, the process proceeds to step 906. Go to step 908 (if another process is waiting).

In step 906, in process 1, NO_PROCESS is added to the value of the member flag of the lock data structure lock_data.
Set. In processing 2, the lock data structure lock_da
Set the value of the member lock of ta to FALSE. In step 907, the process returns to the caller of the lock release 406.

In step 908, in process 1, one waiting process is extracted from the member list of the lock data structure lock_data. In process 2, the value of the member lock of the lock data structure lock_data is set to FALSE. In step 909, in process 1, the execution state 203 of the extracted process in the process management table 117 is changed from "interrupted" to "executable". In process 2, the process number of the extracted process is registered in the executable process list 118. In process 3, the process returns to the caller of the lock release 406.

FIG. 10 is a PAD diagram showing processing of the new lock release 901. In step 901a, the processing 2 of step 808 of the lock acquisition 404 or step 81
The value of the assigned processor number 206 in the process management table 117 set in the process 2 of the step 2 is cleared. When the value of the assigned processor number 206 is cleared, the corresponding process can be assigned to an arbitrary processor. Step 901
At b, the process returns to the caller of the new lock release 901.

FIG. 11 is a PAD diagram showing the process switching process 711. In step 1003, one process is selected from the executable process list 118.
At this time, the process at the head of the executable process list may be selected, or the process with the highest priority may be selected by introducing a priority. Step 100
7, when step 1003 is executed again, a process other than the previously selected process is selected.

In step 1004, it is determined whether or not the assigned processor number 206 in the process management table 117 of the selected process is set. If it is set, the process proceeds to step 1005. If not, step 1009 is performed. Proceed to. In step 1005, it is determined whether or not the assigned processor number 206 and the number of its own processor (the processor executing the process switching 711) match. If they match, the process proceeds to step 1009, and does not match. Step 1007 in case
Proceed to. In Step 1007, Step 1003
Return to and select a process other than the previously selected process.

In step 1009, in the process 1, the selected process is deleted from the executable process list 118. In process 2, the execution state 203 of the selected process in the process management table 117 is changed from "executable" to "executing". In process 3, the contents are restored to the register of the own processor by the register save area 204 of the selected process in the process management table 117. In process 4, the number of the selected process is stored in the running process management table 11
Register in 6. In process 5, the process returns to the call source of the process switching 711.

The process switching 711 is also called when a timer interrupt or the like occurs. At that time, the processor receiving the timer interrupt generation
The contents of the register of the process being executed are saved, the execution state of the process is changed from "in execution" to "executable", and the process is registered in the executable process list, and then the process switch 711 is called.

The above multiprocessor computer system 1
According to the instruction sequence 505 for accessing the shared data,
Are interposed between the lock acquisition 404 and the lock release 406, and the processor 102 (1)-
By designating 102 (N), a process for accessing the shared data can be allocated to the designated processor. Therefore, the caches 103 (1) to 103 (103)
Useless data transfer between (N) is eliminated, and the execution efficiency of the entire system can be improved.

[0039]

According to the processor allocating method and the multiprocessor computer system of the present invention, a plurality of processes accessing shared data are allocated to the same processor, so that unnecessary data transfer between caches is eliminated and the entire system is executed. Efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a multiprocessor computer system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a process management table of the multiprocessor computer system of FIG. 1;

FIG. 3 is a configuration diagram of a process management table during execution of the multiprocessor computer system of FIG. 1;

FIG. 4 is an explanatory diagram of each procedure of lock initialization, lock acquisition, and lock release.

FIG. 5 is an exemplary diagram of a program instruction sequence including lock initialization, lock acquisition, and lock release procedures.

FIG. 6 is a PAD diagram showing a process of a lock initialization procedure.

FIG. 7 is a PAD showing a lock acquisition procedure.

FIG. 8 is a PAD diagram showing a process of a new lock acquisition procedure.

FIG. 9 is a PAD diagram showing processing of a lock release procedure.

FIG. 10 is a PAD diagram showing processing of a new lock release procedure.

FIG. 11 is a PAD showing processing of a process switching procedure;
FIG.

[Explanation of symbols]

101: multiprocessor computer system, 102: processor, 103: cache, 104: secondary storage device, 105: system bus, 106: main memory,
107: lock initialization procedure storage area, 108: lock acquisition procedure storage area, 109: lock release procedure storage area, 110: lock data storage area, 111: lock variable storage area, 112: lock acquisition flag storage area,
113: assigned processor number storage area, 114: standby process list, 116: running process management table, 11
7: process management table, 118: executable process list, 119: process switching procedure storage area, 40
2: Lock initialization procedure (command), 404: Lock acquisition procedure (command), 406: Lock release procedure (command).

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Kazuo Horikawa 890 Kashimada, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture 12 Information and Communication Development Division, Hitachi, Ltd. Address No. 12 Hitachi, Ltd.Information and Communication Development Headquarters

Claims (3)

[Claims] A processor allocation method in a multiprocessor computer system having a plurality of processors and caches respectively corresponding to the processors, wherein when a plurality of processes access shared data, the processes are allocated to the same processor. A processor allocation method characterized by the above-mentioned. 2. A processor allocation method in a multiprocessor computer system having a plurality of processors and caches respectively corresponding to the processors, wherein a mutual exclusion start instruction capable of designating a processor is arranged before a certain instruction sequence. After the instruction sequence, a mutual exclusion end instruction capable of canceling the designation of a processor is arranged, and when a processor is specified by the mutual exclusion start instruction, the mutual exclusion start instruction and the mutual exclusion instruction are designated by the specified processor. When the instruction sequence sandwiched between the exclusion end instructions is executed, and the processor is not specified in the mutual exclusion start instruction,
A processor allocation method, wherein the instruction sequence sandwiched between the mutual exclusion start instruction and the mutual exclusion end instruction is executed by an arbitrary processor. 3. In a multiprocessor computer system having a plurality of processors and caches respectively corresponding to the processors, when a processor is specified by a mutual exclusion start instruction, the specified processor starts the mutual exclusion. A multiprocessor computer system comprising: a processor assignment control unit for executing an instruction subsequent to the instruction and executing the mutual exclusion end instruction, and executing an instruction subsequent to the mutual exclusion end instruction by an arbitrary processor. .