WO2002048765A1 - Dispositifs optiques integres - Google Patents

Dispositifs optiques integres Download PDF

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Publication number
WO2002048765A1
WO2002048765A1 PCT/GB2001/005522 GB0105522W WO0248765A1 WO 2002048765 A1 WO2002048765 A1 WO 2002048765A1 GB 0105522 W GB0105522 W GB 0105522W WO 0248765 A1 WO0248765 A1 WO 0248765A1
Authority
WO
WIPO (PCT)
Prior art keywords
parts
feature
layer
interface
optically conductive
Prior art date
Application number
PCT/GB2001/005522
Other languages
English (en)
Inventor
Gregory Pandraud
Emma Jane Clarissa Dawnay
Original Assignee
Bookham Technology Plc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB0030442A external-priority patent/GB2370409A/en
Priority claimed from GB0106741A external-priority patent/GB0106741D0/en
Application filed by Bookham Technology Plc filed Critical Bookham Technology Plc
Priority to AU2002222205A priority Critical patent/AU2002222205A1/en
Publication of WO2002048765A1 publication Critical patent/WO2002048765A1/fr

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12083—Constructional arrangements
    • G02B2006/12104—Mirror; Reflectors or the like
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12083—Constructional arrangements
    • G02B2006/12107—Grating

Definitions

  • This invention relates to a method of fabricating integrated optical devices and, in particular, devices comprising a layer of silicon separated from a substrate by an insulating layer and to devices fabricated by the method.
  • SOI silicon-on-insulator
  • a method of fabricating an integrated optical device comprising an optically conductive layer separated from a substrate by an optical confinement layer comprising the steps of:
  • an integrated optical device on a silicon-on-insulator chip fabricated by such a method is provided.
  • an integrated optical device comprising an optically conductive layer separated from substrate by an optical confinement layer, the device having been formed from two parts bonded together at an interface, a first feature being provided at the interface by processing at least one of the two parts before the two parts are bonded together.
  • an integrated optical device fabricated by bonding together two wherein the two parts are bonded together at different crystallographic orientations. Bonding together two parts provides greater flexibility in the fabrication of an optical device as features can be formed in each part independently of features in the other part. One particular aspect of this is the crystallographic orientation of the two parts.
  • Figures 1A-1C are schematic diagrams illustrating steps of one embodiment of a method according to the present invention.
  • FIGS. 2A-2C, 3A-3C and 4A-4C are schematic drawings illustrating further embodiments of methods according to the present invention.
  • Figures 5 and 6 are schematic side views of two types of device that may be formed by such methods; and Figure 7 is a perspective view of two wafers being bonded together at different crystallographic orientations.
  • Figure 1 A shows a first wafer 1 comprising a substrate 2, e.g. of silicon, with a layer 3 of oxide, e.g. silicon dioxide, on the surface thereof.
  • a native oxide layer forms on silicon when exposed to air or any other oxygen containing environment and the thickness of this may be increased, e.g. to around 0.4-0.5 microns, by thermal oxidation.
  • Figure 1 B shows a second wafer 4 formed of silicon.
  • the second wafer 4 has been processed to form a feature on one face 4A thereof as indicated by the shaded region 5.
  • the face 4A is then bonded to the oxide layer 3 of the first wafer 1 as indicated in the Figure.
  • Direct wafer bonding generally involves preparation of the surfaces to be bonded to make them as smooth as possible and pressing the two surfaces together. Some form of thermal cycling may also be used to increase the bond strength. Once such process comprises the steps of:
  • Such bonding techniques are well known so will not be described further. Such techniques are capable of forming a very strong bond between two parts such that the interface is no longer detectable and the two parts have, in effect, become one. Other bonding techniques providing a similar result may also be used.
  • the silicon layer 6 formed by the second wafer 4 may be further processed, e.g. to reduce its thickness, form further features therein and/or polish its surface.
  • Figure 1 C illustrates a case in which the thickness of the silicon layer 6 has been reduced until the feature 5 is exposed on the outer surface of the layer 6.
  • the device illustrated in Figure 1 C could, in some cases, be fabricated in the conventional manner, i.e. by processing a silicon-on-insulator chip from the outer surface of the silicon layer but, as will be explained further below, the method described above enables features or devices to be formed which would be impossible, or very difficult, to form by conventional methods and/or which can be formed more easily or with greater accuracy than is possible by conventional methods. For instance, it will be appreciated that if the silicon layer 6 is not reduced in thickness to the extent shown in Figure 1 C, the feature 5 will be buried in the silicon layer 6, i.e. beneath the surface thereof. Such buried features are difficult to fabricate by conventional methods.
  • the feature 5 may take many forms. In one form, it may comprise a hole or recess which, in the final product contains a fluid, either a gas or liquid, for example air. In another case, the feature 5 may be a doped region. In a further case, it may comprise some other material e.g. a polymer or different semi-conductor material, or any combination of the above.
  • the feature 5 may also take many shapes (and need not be a simple rectangular shape as shown) depending on the nature of the component to be formed thereby.
  • Figures 2A-2C illustrate the steps of a method in which the first wafer 1 is processed to form a feature on a surface 1A thereof as indicated by the shaded region 7 in Figure 2A.
  • a silicon wafer 4 is then bonded to the surface 1 A as illustrated in Figure 2B.
  • the thickness of the silicon layer 6 formed by the wafer 4 may then be reduced, as shown in Figure 2C.
  • a feature is pre-formed in the first wafer 3, which carries the oxide layer 3, before the two wafers are bonded together.
  • the feature 5 may be formed in just the oxide layer 3 and/or may be formed in the substrate 2 beneath the oxide layer 3 as shown in Figure 2.
  • Features may also be pre-formed in both of the two wafers 1 , 4 prior to the wafers being bonded together.
  • the features in the respective wafers may be designed to be aligned with each other but in other cases this may not be so and they may be independent of each other.
  • FIG. 1 illustrates a method in which the interface between the two parts being bonded together is between the oxide layer 3 and the silicon layer 6.
  • the interface may be at other positions within the device.
  • Figures 3A to 3C illustrate a method in which the interface is within the silicon layer.
  • An SOI wafer 8 (which may be fabricated by forming an oxide layer 9 on the substrate 10 and then growing an epitaxial layer of silicon 11 on the oxide layer 9 or by forming an oxide layer 9 on the substrate 10, bonding a silicon wafer to the oxide layer and reducing this silicon layer 11 to the required thickness) is processed to form a feature 12 in the surface 11A of the silicon layer 11 as shown in Fig 3A.
  • a second silicon wafer 13 is then bonded to the surface 11 A of the silicon layer 11 of the first wafer.
  • the second silicon wafer 13 may also be processed to form a feature 14 in the surface 13A thereof prior to the surfaces 11A and 13A being bonded together.
  • the thickness of the silicon layer 15 formed by the combination of the silicon layer 11 and wafer 13 is reduced to the required level.
  • the features 12 and 14 are thus formed within the silicon layer 15 as shown in Figure 3C. It will be appreciated that a feature need not be formed in both wafers prior to bonding but in only one of the wafers, either layer 11 or wafer 13.
  • the feature(s) may also, if desired, extend to the oxide layer 9 and/or to the surface 15A of the silicon layer 15.
  • Figures 4A to 4C illustrate a method in which the interface is between the substrate and the oxide layer.
  • a silicon wafer 16 is processed to form a feature 17 in a surface 16A thereof as shown in Figure 4A.
  • a second silicon wafer 18 with an oxide layer 19 formed thereon is then bonded to the surface 16A of the first wafer as shown in Figure 4B. Once the two wafers have been bonded together, the thickness of the silicon layer 20 formed by the second wafer 18 is reduced to the required level.
  • the feature 17 is thus formed in the substrate 16 beneath the oxide layer 19.
  • the feature 17 may, if desired, extend from the oxide layer 19 to the underside 16A of the substrate.
  • a further feature may, if desired, be formed in the surface of the second wafer 18 bonded to the first wafer 16 prior to bonding the wafers together.
  • the feature(s) formed in the wafer(s) prior to bonding may take a variety of forms. As mentioned, they may comprise one or more holes or recesses etched into the surface which are filled with air or some other fluid to define one or more components in the silicon layer. They may also comprise doped areas or areas where another material, e.g. polymer or a different semiconductor material, has been deposited or they may comprise any combination of such elements. Such holes or recesses may thus be filled with material of a different refractive index ,than the surrounding material and, each hole or a plurality of holes may be shaped or configured to act as an optical component, e.g. a lens or prism. Alternatively, the holes may define an optical component in the remaining areas of material therebetween or the holes and the remaining material may together form an optical component.
  • the holes or recesses may thus be filled with material of a different refractive index ,than the surrounding material and, each hole or a plurality of holes may be shaped or configured to act as an optical component, e.
  • a significant advantage of the methods described is that different parts of an optical device may be fabricated independently of each other, i.e. the processing steps used to fabricate features in one wafer can be carried out entirely independently of processing steps used to fabricate features in the other wafer before the two wafers are bonded together.
  • This increases the choice of processing techniques which may be used in each case and, in particular, enables each of the features to be fabricated to a degree of accuracy greater than would normally be possible if the features were all fabricated on a single wafer.
  • the features pre-formed on the wafers prior to bonding the wafers together may be buried within the final device. However, they may also be formed so as to extend to an outer surface of the optically conductive layer and/or of the substrate or the thickness of the optically conductive layer and/or the substrate may be reduced until the feature is accessible from an outer surface thereof.
  • the optically conductive layer and/or the substrate may be processed after the wafers have been bonded together to provide one or more connections between an outer surface of the device and one or more features buried therein.
  • Such a connection may comprise an optical and/or on an electrical connection and may take a variety of forms. It may, for instance, comprise one or more holes or recesses (filed with air or some other fluid) etched in the device, doped areas or areas filled or partially filled with other material or any combination thereof.
  • the methods described above can be used to form a wide variety of devices which will not be discussed here although some basic devices or elements which may be formed in this way will be described below.
  • the feature formed at the interface between the two bonded wafers may, for example comprise a waveguide, e.g. extending in a direction substantially parallel to the plane of the interface.
  • Figure 5 shows a schematic side view of a waveguide 21 formed in a silicon layer 22 separated from a substrate 23 by an oxide layer 24.
  • the waveguide 21 may comprise an elongate region having a refractive index differing from that of the surrounding material, e.g. a doped region or a region of different material to the surrounding material, or an elongate region one or more sides of which are defined by elongate holes or channels within the material.
  • a hole or recess may also be formed in the silicon layer 22 with a reflective facet 25 positioned to re-direct light received from the waveguide 21 , in this case out of the chip or to a component (not shown) on the surface of the chip.
  • the hole or recess may also be elongate, e.g. in the form of a trench, and arranged to re-direct light received from a plurality of waveguides.
  • the features formed at the interface between the two bonded wafers may have a periodic structure so as to act as a grating for receiving light incident upon the device or directing light out of the device.
  • Figure 6 shows a schematic side view of a waveguide 26 formed in a silicon layer 27 separated from a substrate 28 by an oxide layer 29.
  • Part of the waveguide 26 is formed with a periodic structure 30 as shown.
  • the periodic structure 30 may take many forms which provide a periodicity in the refractive index of the waveguide along its length. It may, for instance, comprise alternating regions of silicon and holes (filled with air or other material) or alternating regions having different dopant levels or any other periodic structure known in the field which can be fabricated by the method described above.
  • light incident upon the chip or from a device ' (not shown) mounted on the chip, received by the grating formed by the periodic structure 30 is received by the waveguide 26 and transmitted along the waveguide.
  • both of the devices shown in Figures 5 and 6 can be operated in either direction, i.e. for receiving light into a waveguide in the device or transmitting light from the waveguide in the device.
  • Figure 7 illustrates a further advantage of fabricating a device by bonding together two parts.
  • the crystallographic material of the wafer has the same crystallographic orientation throughout.
  • SOI silicon-on-insulator
  • a crystalline material such as silicon is dependent on the crystallographic orientation of the material, e.g. because wet etch processes tends to follow crystallographic planes within the material or because the accuracy of fabrication is dependent upon crystallographic orientations, e.g. epitaxial growth.
  • Some devices may require features which are ⁇ preferably formed at different crystallographic orientation but which, nevertheless, need to be formed at specific orientations relative to each other.
  • By constructing a device as described above so that parts thereof are in different crystallographic orientations it can be arranged that each feature is fabricated at the preferred crystallographic orientation but that the relative orientation of the features can be independently selected.
  • one or more of the features may be fabricated in the respective parts prior to bonding the parts together, or the features may be fabricated after the parts have been bonded together.
  • the two parts may be bonded together at any angle relative to each other but, typically, the crystallographic orientations of the two parts may be arranged at 45 degrees or 90 degrees to each other.
  • Figure 7 shows two silicon wafers 41 , 42, each wafer having a flat 41A, 42A which corresponds to a given crystallographic direction, e.g. ⁇ 100 > direction.
  • the wafers are bonded together so that flats 41 A and 42A are at 45 degrees to other.
  • a first feature 43 which is preferably formed perpendicular to the ⁇ 100 > direction is formed in the first wafer 41.
  • a second feature 44 which preferably formed at an angle of 45 degrees to the ⁇ 100 > direction is formed in the second wafer 42, yet by bonding the wafers together at 45 degrees to each other, the two features can be fabricated at a selected orientation to each other, in this case parallel to each other.
  • Feature 43 may be a feature formed by wet etching in a silicon substrate formed by wafer 41
  • feature 44 may be formed by epitaxial growth in an optically conducting layer of silicon formed by wafer 42.
  • Such chips comprise an optically conductive silicon layer separated from a substrate, which is also usually of silicon, by an insulating layer, such as an oxide, typically silicon dioxide.
  • the term 'insulating layer' is derived from the initial use of SOI chips for the fabrication of electronic integrated circuits. When such chips are used for fabrication of optical integrated circuits, this layer acts as an optical confinement layer, i.e. it serves to confine optical modes within the optically conductive silicon layer due to it either not being optically conductive or having a higher refractive index than the optically conductive silicon layer. Whilst the use of silicon as the optically conductive layer and the use of silicon dioxide as the optical confinement layer is preferred, it will be appreciated that the methods described above may also be suitable for fabricating integrated optical circuits in which the optically conductive layer and/or the optical confinement layer are formed of other materials.
  • Two or more parts may, for instance, be bonded side-by-side to the same wafer on three or more parts may be bonded together in a stack.
  • One or more further features may thus be formed at the interface between these parts by processing at least one of the respective parts prior to bonding them together.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un dispositif optique intégré comprenant une couche optiquement conductrice (6), séparée d'un substrat (2) par une couche de confinement optique (3), ce procédé consistant à former le dispositif en reliant deux parties séparées (1, 4) par leur interface (4A), et à former une première caractéristique (5) à l'interface (4A) par traitement d'au moins une (4) des deux parties avant de les (1, 4) relier ensemble. Le procédé convient particulièrement à la fabrication de dispositifs silicium sur isolant, la caractéristique (5) étant disposée en retrait de la surface extérieure de ces dispositifs. Le procédé permet aussi de relier les deux parties (1, 4) dans des orientations cristallographiques différentes.
PCT/GB2001/005522 2000-12-14 2001-12-14 Dispositifs optiques integres WO2002048765A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002222205A AU2002222205A1 (en) 2000-12-14 2001-12-14 Integrated optical devices

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB0030442A GB2370409A (en) 2000-12-14 2000-12-14 Integrated optical devices
GB0030442.8 2000-12-14
GB0106741.2 2001-03-16
GB0106741A GB0106741D0 (en) 2001-03-16 2001-03-16 Integrated optical devices

Publications (1)

Publication Number Publication Date
WO2002048765A1 true WO2002048765A1 (fr) 2002-06-20

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WO (1) WO2002048765A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1378777A3 (fr) * 2002-07-02 2005-02-16 Omron Corporation Dispositif de guide d'ondes optiques, procédé de fabrication de ce dispositif et dispositif de communication optique
US7013055B2 (en) 2002-07-02 2006-03-14 Omron Corporation Optical waveguide device, manufacturing method thereof, and optical communication apparatus
EP1659430A1 (fr) * 2003-03-28 2006-05-24 NHK Spring Co., Ltd. Composant de circuit a guide d'onde optique et procede de production
US7203387B2 (en) 2003-09-10 2007-04-10 Agency For Science, Technology And Research VLSI-photonic heterogeneous integration by wafer bonding
WO2007111085A1 (fr) 2006-03-29 2007-10-04 Sumitomo Osaka Cement Co., Ltd. Dispositif à guide d'ondes optiques

Citations (6)

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Publication number Priority date Publication date Assignee Title
GB2230616A (en) * 1989-03-30 1990-10-24 British Telecomm Silicon bipolar phase modulator
US5210801A (en) * 1990-04-03 1993-05-11 Commissariat A L'energie Atomique Environmentally protected integrated optical component and its production process
EP0567051A1 (fr) * 1992-04-21 1993-10-27 Matsushita Electric Industrial Co., Ltd. Dispositif optique à guide d'onde et procédé de fabrication
EP0953853A2 (fr) * 1998-05-01 1999-11-03 Shin-Etsu Handotai Company Limited Matériau multicouche et dispositif ayant une fonction optique
US5986331A (en) * 1996-05-30 1999-11-16 Philips Electronics North America Corp. Microwave monolithic integrated circuit with coplaner waveguide having silicon-on-insulator composite substrate
FR2779835A1 (fr) * 1998-06-11 1999-12-17 Centre Nat Rech Scient Dispositif de diffraction de lumiere enfoui dans un materiau

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2230616A (en) * 1989-03-30 1990-10-24 British Telecomm Silicon bipolar phase modulator
US5210801A (en) * 1990-04-03 1993-05-11 Commissariat A L'energie Atomique Environmentally protected integrated optical component and its production process
EP0567051A1 (fr) * 1992-04-21 1993-10-27 Matsushita Electric Industrial Co., Ltd. Dispositif optique à guide d'onde et procédé de fabrication
US5986331A (en) * 1996-05-30 1999-11-16 Philips Electronics North America Corp. Microwave monolithic integrated circuit with coplaner waveguide having silicon-on-insulator composite substrate
EP0953853A2 (fr) * 1998-05-01 1999-11-03 Shin-Etsu Handotai Company Limited Matériau multicouche et dispositif ayant une fonction optique
FR2779835A1 (fr) * 1998-06-11 1999-12-17 Centre Nat Rech Scient Dispositif de diffraction de lumiere enfoui dans un materiau

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
CHOUTEAU S ET AL: "OPTOELECTRONIC MICROSWITCH ON SOI BASED STRUCTURE", 1995 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS. TUCSON, OCT. 3 - 5, 1995, PROCEEDINGS OF THE ANNUAL SOS/SOI TECHNOLOGY CONFERENCE. (FROM 1991 PROCEEDINGS OF THE INTERNATIONAL SOI CONFERENCE.) SILICON-ON-INSULATOR TECHNOLOGY AND DEVICES, NEW YORK,, 3 October 1995 (1995-10-03), pages 40 - 41, XP000590645, ISBN: 0-7803-2548-6 *
MASZARA ET AL.: "Bonding of silicon wafers for silicon-on-insulator", JOURNAL OF APPLIED PHYSICS, vol. 64, no. 10, 15 November 1988 (1988-11-15), pages 4943 - 4950, XP002190825 *
PELISSIER S ET AL: "FABRICATION OF BURIED CORRUGATED WAVEGUIDES BY WAFER DIRECT BONDING", JOURNAL OF LIGHTWAVE TECHNOLOGY, IEEE. NEW YORK, US, vol. 18, no. 4, April 2000 (2000-04-01), pages 540 - 545, XP000989277, ISSN: 0733-8724 *

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1378777A3 (fr) * 2002-07-02 2005-02-16 Omron Corporation Dispositif de guide d'ondes optiques, procédé de fabrication de ce dispositif et dispositif de communication optique
US7013055B2 (en) 2002-07-02 2006-03-14 Omron Corporation Optical waveguide device, manufacturing method thereof, and optical communication apparatus
EP1777560A2 (fr) * 2002-07-02 2007-04-25 Omron Corporation Dispositif à guide d'ondes optique, son procédé de fabrication, et appareil de communication optique
EP1777560A3 (fr) * 2002-07-02 2008-08-27 Omron Corporation Dispositif à guide d'ondes optique, son procédé de fabrication, et appareil de communication optique
EP1659430A1 (fr) * 2003-03-28 2006-05-24 NHK Spring Co., Ltd. Composant de circuit a guide d'onde optique et procede de production
EP1659430A4 (fr) * 2003-03-28 2008-10-15 Omron Tateisi Electronics Co Composant de circuit a guide d'onde optique et procede de production
US7349614B2 (en) 2003-09-10 2008-03-25 Agency For Science, Technology And Research VLSI-photonic heterogeneous integration by wafer bonding
US7203387B2 (en) 2003-09-10 2007-04-10 Agency For Science, Technology And Research VLSI-photonic heterogeneous integration by wafer bonding
WO2007111085A1 (fr) 2006-03-29 2007-10-04 Sumitomo Osaka Cement Co., Ltd. Dispositif à guide d'ondes optiques
EP2015112A1 (fr) * 2006-03-29 2009-01-14 Sumitomo Osaka Cement Co., Ltd. Dispositif a guide d'ondes optiques
EP2015112A4 (fr) * 2006-03-29 2009-06-03 Sumitomo Osaka Cement Co Ltd Dispositif a guide d'ondes optiques
US8391651B2 (en) 2006-03-29 2013-03-05 Sumitomo Osaka Cement Co., Ltd. Optical waveguide device
US8396334B2 (en) 2006-03-29 2013-03-12 Sumitomo Osaka Cement Co., Ltd. Optical waveguide device

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