WO2002043144A1 - Structure d'element de liaison et procede de fabrication de ce dernier - Google Patents

Structure d'element de liaison et procede de fabrication de ce dernier Download PDF

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Publication number
WO2002043144A1
WO2002043144A1 PCT/US2001/043215 US0143215W WO0243144A1 WO 2002043144 A1 WO2002043144 A1 WO 2002043144A1 US 0143215 W US0143215 W US 0143215W WO 0243144 A1 WO0243144 A1 WO 0243144A1
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WIPO (PCT)
Prior art keywords
metal
pad
bonding pad
interconnect
dielectric
Prior art date
Application number
PCT/US2001/043215
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English (en)
Inventor
Bin Zhao
Original Assignee
Conexant Systems, Inc.
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Publication date
Priority claimed from US09/716,350 external-priority patent/US6740985B1/en
Application filed by Conexant Systems, Inc. filed Critical Conexant Systems, Inc.
Publication of WO2002043144A1 publication Critical patent/WO2002043144A1/fr

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    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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Definitions

  • the present invention is in the field of integrated circuit fabrication. More particularly, the invention is in the field of bonding pad and support structures for integrated circuits using copper and low dielectric constant materials.
  • the drive to fabricate faster IC (Integrated Circuit) chips is in large part focused on improving the speed ofthe IC chip interconnect while maintaining or improving other aspects of IC chip performance such as, low power consumption, low noise, and long term reliability and while maintaining or improving the manufacturing cost.
  • Interconnect delay is directly proportional to the product of interconnect resistance and the capacitance driven by the interconnect.
  • the capacitance ofthe interconnect is directly proportional to the dielectric constant ("k") ofthe dielectric that insulates the interconnect from other interconnect or other circuits ofthe IC chip. As such, reducing the dielectric constant ofthe dielectric results in a reduction ofthe interconnect capacitance and a reduction in the interconnect delay.
  • damascene is derived from the ancient inlaid metal artistry originated in Damascus. According to the damascene process, a trench or canal is cut into the dielectric and then filled with metal. Figures 1A through ID help describe an overview ofthe damascene process used to fabricate copper interconnect.
  • insulating layer 102 (for example, silicon dioxide) is formed on a substrate 104, which usually contains circuitry and may contain other interconnection levels. To help with the patterning of copper by the damascene process, layer 102 should have a uniform thickness and be as flat as possible. An ideally flat insulating layer 102 is shown in Figure 1 A.
  • FIG. IB shows a cross-section of layer 102 after patterning to create two trenches, wide trench 106 and narrow trench 108. These trenches are formed by removing a top portion of layer 102 using photolithography and a suitable anisotropic etch technique, such as reactive ion etching, which are known in the art. These trenches are where copper interconnect conductors should be laid in. Moreover, insulator 107 is to provide insulation between the copper interconnect to be laid in trench 106 and the copper interconnect to be laid in trench 108. Referring to Figure IC, copper film 112 is shown as having been deposited over insulating layer 102.
  • a metal barrier layer such as tantalum (Ta) or tantalum nitride (TaN) is deposited over insulating layer 102.
  • Copper film 1 12 may, for example, be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), PVD followed by reflow, or electroplating.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • PVD physical vapor deposition
  • electroplating electroplating
  • copper film 112 is deposited to a depth such that trenches 106 and 108 are completely filled with copper.
  • the unwanted portions of copper film 1 12 for example the portion that is shown as covering insulator barrier 107, must be removed.
  • Figure ID shows a wide inlaid copper conductor 114 and a narrow inlaid copper interconnect 116 remaining in trenches 106 and 108, respectively, after polishing to remove the unwanted portions of copper film 1 12.
  • Polishing is preferably accomplished by chemical-mechanical polishing (CMP), wherein the semiconductor wafer and/or a polishing pad are rotatably mounted and brought into contact with each other under rotation.
  • CMP chemical-mechanical polishing
  • a slurry providing both abrasive and chemically reactive components is supplied, typically to the pad, during polishing.
  • the abrasive component is typically comprised of finely ground colloidal silica or alumina particles.
  • the chemically reactive component is typically diluted acid and/or hydrogen peroxide, with the remainder ofthe slurry comprised of deionized water.
  • the slurry composition and polishing conditions e.g. rotational velocity, polish force, temperature
  • the conducting films i.e. the deposited copper film and the metal barrier layer
  • the insulating layer 30:1 being a typical ratio
  • FIG. 1 One drawback ofthe CMP process, however, is illustrated in Figure ID.
  • the top surface of narrow copper interconnect 1 16 is shown as slightly “dished” but substantially co-planar with the upper surface of insulating layer 102.
  • wide copper interconnect 114 is shown as severely dished.
  • the dishing phenomenon, such as that shown in wide interconnect 114 results in an uneven profile in the interconnect layer which is harmful to the fabrication process of subsequent layers in the IC chip.
  • sections of a wide conductor, such as wide conductor 114 may be completely removed from the trench during polishing, leaving the trench bottom exposed. This total absence of any metal at the central parts of a wide metal conductor is undesirable since, for example, it causes an increase in the resistance ofthe metal interconnect and also reduces the long term reliability ofthe IC chip.
  • An additional problem caused by the dishing phenomenon is that vias that are supposed to make electrical connection between a metal layer on top ofthe wide conductor and the wide conductor may not reach the shallow parts ofthe wide conductor since the shallow parts have too little metal left and are lower than the remaining portions ofthe wide interconnect.
  • vias from an overlaying metal layer are designed to be long enough to reach the surface of an underlying metal interconnect, the vias over a wide interconnect are too short to reach the "dished" portions ofthe wide interconnect.
  • the dishing during the CMP process may be substantially reduced by having "dielectric fillers" in wide trenches such as trench 106.
  • dielectric fillers in wide trenches such as trench 106.
  • experimentation with specific conducting and insulating materials and a desired CMP process is required to determine the minimum line width that is subject to severe dishing and as such would require dielectric fillers to reduce or eliminate such dishing.
  • this width may vary from several microns to tens of microns.
  • a typical bonding pad which has a width of between 60 to 100 microns is clearly wide enough to be subject to dishing as a result ofthe CMP process. Accordingly, dielectric fillers to reduce or eliminate dishing are conventionally needed for copper bonding pads formed by a damascene process.
  • Figures 2A and 2B illustrate use of dielectric fillers with two slightly different configurations.
  • Figure 2A is a top view of a copper bonding pad 230.
  • Dielectric fillers shaped as long rectangular strips (as viewed from the top ofthe bonding pad) are distributed within copper bonding pad 230.
  • An example of such rectangular strip dielectric fillers is referred to by numeral 232 in Figure 2A.
  • Figure 2B is a top view of a copper bonding pad 240.
  • Dielectric fillers shaped as squares are distributed within copper bonding pad 240.
  • An example of such square dielectric fillers is referred to by numeral 242 in Figure 2B.
  • FIG. 2C A side view of copper bonding pad 230 in Figure 2A along the line marked as 2C (which is the same as a side view of copper bonding pad 240 in Figure 2B along the line marked as 2C) is shown in Figure 2C.
  • Figure 2C shows insulating layer 202 (corresponding to insulating layer 102 in Figures 1 A through ID) which rests on substrate 204 (corresponding to substrate 104 in Figures 1A through ID).
  • Trench 206 in Figure 2C corresponds to trench 106 in Figures 1A through ID while trench 208 in Figure 2C corresponds to trench.108 in Figures 1A through ID.
  • Dielectric fillers 252 in Figure 2C are cross- sections of dielectric fillers 232 in Figure 2A (or dielectric fillers 242 in Figure 2B).
  • Dielectric fillers 252 in Figure 2C are located between metal segments 254 in Figure 2C. Although not apparent from Figure 2C, metal segments 254 are electrically connected as shown in Figures 2A and 2B. In other words, metal segments 254 are part ofthe same bonding pad 230 in Figure 2A (or bonding pad 240 in Figure 2B). As can be seen from Figure 2C, narrow conductor 216 (which corresponds to narrow conductor
  • wide conductor 214 shows only slight dishing.
  • wide conductor 214 (corresponding to pad 230 in Figure 2A or pad 240 in Figure 2B) also shows slight dishing in metal segments 254 as shown in Figure 2C.
  • the reduced dishing of wide conductor 214 in Figure 2C as compared with wide conductor 114 in Figure ID is due to the existence of dielectric fillers 252.
  • Dielectric fillers 252 cause metal segments 254 to behave as narrow conductor 216 as concerns the CMP process. Accordingly, the dishing effect in metal segments 254 becomes less severe as is the case for a narrow conductor such as conductor 216.
  • dielectric fillers in copper bonding pads reduces or eliminates the severe dishing problem that would otherwise exist, the dielectric fillers actually impair some ofthe performance characteristics ofthe copper bonding pads. For example, dielectric fillers lead to veiy poor adhesion to the bond wires which are typically made of gold or aluminum. Moreover, since some ofthe bonding pad is covered by dielectric fillers (which are insulators), the electrical connection between the bond wire and the bonding pad is also impaired. Further, dielectric fillers are also poor thermal conductors and as such reduce the thermal conductivity ofthe copper bonding pad.
  • low-k dielectric materials are used in combination with copper interconnect (in a damascene process) to achieve a reduction in interconnect capacitance.
  • low-k dielectric materials further complicate the design of copper bonding pads.
  • Low-k dielectric materials which underlie the copper bonding pad have low mechanical strength. Due to the force applied to attach the bond wire to the bonding pad, low-k materials below the bonding pad may experience cracks. These cracks may cause immediate damage to the neighboring circuits on the IC chip. Alternatively, cracks that are too small for immediate damage may grow and cause long term reliability problems in the IC chip. Therefore, the poor mechanical strength of low-k materials must somehow be circumvented in copper chips using copper bonding pads.
  • the present invention is an improved bonding pad and support structure and method for their fabrication.
  • the invention's bonding pad and support structure overcome a serious need in the art by providing sufficient mechanical support and strength for the bonding pad, good thermal conductivity, strong electrical connection with bond wires, and good adhesion to bond wires while being more tolerant to the potential dishing problem existing in damascene and CMP processing.
  • the invention uses a copper bonding pad directly supported by a copper via pad structure, the copper via pad structure having substantially the same geometry and dimensions as the copper bonding pad.
  • the combination ofthe copper bonding pad along with the support from the copper via pad structure results in an increase in effective thickness ofthe bonding pad. Due to this effective increase in the bonding pad thickness, the bonding pad is more tolerant to the potential dishing problem caused by the CMP process. Because ofthe greater tolerance ofthe invention's bonding pad to the CMP process, there is no need for dielectric fillers that are otherwise used to prevent or reduce dishing. Moreover, since dielectric fillers are not used in the invention's bonding pad, the bonding pad's adhesion to bond wires, the electrical connection between the bonding pad and the bond wires, and the bonding pad thermal conductivity are all significantly improved.
  • various metal pad structures and via pad structures are used below the via pad structure directly supporting the copper bonding pad.
  • the various metal pad structures are comprised of alternating segments of interconnect metal and dielectric fillers.
  • the various via pad structures are comprised of alternating segments of via metal and dielectric fillers.
  • the alternating segments of interconnect metal and dielectric fillers and the alternating segments of via metal and dielectric fillers prevent or reduce the potential dishing problem that otherwise exists in damascene and CMP processing.
  • the alternating segments of interconnect metal and dielectric fillers and the alternating segments of via metal and dielectric fillers are arranged such that there are a number of columns of solid metal support below the bonding pad.
  • FIGS. 1 A through ID show an overview of conventional damascene and CMP processes.
  • Figures 2A through 2C show the conventional use of dielectric fillers in order to reduce potential dishing of wide interconnect areas undergoing a CMP process.
  • Figures 3 A and 3B illustrate two recent copper bonding pads and their respective support structures.
  • Figure 4 illustrates the invention's copper bonding pad and support structure.
  • Figure 5 shows the top view ofthe alternating interconnect metal segments and dielectric fillers in metal pad structure 422 of Figure 4.
  • Figure 6 shows the top view ofthe alternating via metal segments and dielectric fillers in via pad structure 420 of Figure 4.
  • Figure 7 shows the top view ofthe alternating interconnect metal segments and dielectric fillers in metal pad structure 418 of Figure 4.
  • Figure 8 shows the top view ofthe alternating via metal segments and dielectric fillers in via pad structure 416 of Figure 4.
  • Figure 9 shows the top view ofthe alternating interconnect metal segments and dielectric fillers in metal pad structure 414 of Figure 4.
  • Figure 10 shows the top view ofthe via pad structure 412 of Figure 4.
  • Figure 11 shows the top view of bonding pad 410 of Figure 4.
  • Figure 12 shows an overlay of the top views of structures 422, 420, 418, 416, and 414 of Figure 4.
  • the present invention is an improved bonding pad and support structure and method for their fabrication.
  • the principles of the invention, as defined by the claims appended herein, can obviously be applied beyond the specifically described embodiments ofthe invention described herein.
  • certain details have been left out in order to not obscure the inventive aspects ofthe invention. The details left out are within the knowledge of a person of ordinary skill in the art.
  • copper bonding pad 330 rests on low-k dielectric 332.
  • Copper bonding pad 330 is the top interconnect metal layer in an exemplary four interconnect metal layer IC chip using copper as the interconnect metal in all the four interconnect metal layers.
  • copper bonding pad 330 is patterned out ofthe fourth interconnect metal layer.
  • Low-k dielectric 332 is grown or deposited on top of silicon dioxide layer 304.
  • Silicon dioxide layer 304 is grown on top of a silicon or other semiconductor substrate. The substrate is not shown in Figure 3 A.
  • a passivation layer 331 covers the surface ofthe structure shown in Figure 3A. The passivation layer is used to, among other things, prevent damage to the underlying semiconductor circuits and is typically a stack of silicon nitride and silicon dioxide layers.
  • Reference column 340 in Figure 3 A is for the purpose of illustration only and it shows four levels of metal and their respective vias stacked on top of each other. Reference column 340 is used as a guide for the purpose of illustrating the various layers of metal and vias present in the IC chip containing bonding pad 330. Reference column 340 shows top interconnect metal layer 321 which is also referred to as "M4." The top interconnect metal layer, i.e. M4, is the same layer in which bonding pad 330 is located. Directly below top interconnect metal layer 321 in reference column 340 is via 322. Via 322 is a via used for connecting top interconnect metal layer (i.e. M4) to the interconnect metal layer directly below which is the third interconnect metal layer (also referred to as "M3"). Via 322 is thus also referred to as Via (M4/M3).
  • the third interconnect metal layer (i.e. M3) is fabricated directly below the top interconnect metal layer.
  • interconnect metal layer three is referred to by numeral 323.
  • Via 324 is a via used for connecting the third interconnect metal layer (i.e. M3) to the interconnect metal layer directly below which is the second interconnect metal layer (also referred to as "M2"). Via 324 is thus also referred to as Via (M3/M2).
  • the second interconnect metal layer (i.e. M2) is fabricated directly below the third interconnect metal layer.
  • interconnect metal layer two is referred to by numeral 325.
  • via 326 Directly below the second interconnect metal layer 325 in reference column 340 is via 326.
  • Via 326 is a via used for connecting the second interconnect metal layer (i.e. M2) to the interconnect metal layer directly below which is the first interconnect metal layer (also referred to as "Ml" in the present invention). Via 326 is thus also referred to as Via (M2/M1).
  • the first interconnect metal layer (i.e. Ml) is fabricated directly below the second interconnect metal layer M2.
  • interconnect metal layer one is referred to by numeral 327.
  • contact 328 Directly below the first interconnect metal layer 327 in reference column 340 is contact 328.
  • Contact 328 can be used for connecting the first interconnect metal layer (i.e. Ml) to the layer directly below Ml .
  • the layer directly below the first interconnect metal layer (which layer is not shown in Figure 3A) is, for example, silicon substrate, polysilicon, or an active region of silicon.
  • no dielectric fillers have been used in copper bonding pad 330. Since no dielectric fillers have been used in copper bonding pad 330, some dishing occurs as shown in Figure 3A.
  • An arrow referred to by numeral 350 in Figure 3A symbolizes the force that is applied to bonding pad 330 during the bonding process.
  • low-k materials where k designates the value ofthe dielectric constant
  • dielectric material 332 which supports copper bonding pad 330 has a low dielectric constant.
  • low-k materials which are used in copper IC chips have poor mechanical strength.
  • cracks would develop in the low-k material 332.
  • Some ofthe cracks may develop immediately and some may develop later on. In any event, the cracks cause an immediate damage to the circuits in the IC chip or cause a long term reliability problem by causing damage after some time has passed.
  • low-k dielectric material 332 also exhibits poor thermal conductivity.
  • the poor thermal conductivity results in an increase in the temperature ofthe semiconductor chip. It is well known in the art that an increase in the temperature ofthe semiconductor chip causes various problems such as an increase in propagation delays in the semiconductor material, an increase in electromigration in metal interconnect, an undesirable change in the trigger point of various logic gates, as well as other problems.
  • bonding pad 330 has relatively good adhesion to bond wires, bonding pad 330 does not have adequate mechanical support from low-k dielectric 332 to withstand force 350 applied during bonding of bond wires. Further, as stated above, the structure supporting bonding pad 330 in Figure 3A has a poor thermal conductivity.
  • copper bonding pad 360 rests on low-k dielectric 392.
  • copper bonding pad 360 is the top interconnect metal layer in an exemplary four interconnect metal layer IC chip using copper as the interconnect metal in all the four interconnect metal layers.
  • Low-k dielectric 392 is deposited or grown on top of silicon dioxide layer 394.
  • Silicon dioxide layer 394 is grown on top of a silicon or other semiconductor substrate. The substrate is not shown in Figure 3B.
  • a passivation layer 361 covers the surface ofthe structure shown in Figure 3B.
  • Reference column 380 in Figure 3B is for the purpose of illustration only and it shows four levels of metal and their respective vias stacked on top of each other.
  • Reference column 380 is used as a guide for the purpose of illustrating the various layers of metal and vias present in the IC chip containing bonding pad 360.
  • Reference column 380 shows top interconnect metal layer 341 which is also referred to as "M4.”
  • the top interconnect metal layer, i.e. M4 is the same layer in which bonding pad 360 is located.
  • Via 342 is a via used for connecting top interconnect metal layer (i.e. M4) to the interconnect metal layer directly below which is the third interconnect metal layer (also referred to as "M3").
  • Via 342 is thus also referred to as Via (M4/M3).
  • the third interconnect metal layer (i.e. M3) is fabricated directly below the top interconnect metal layer.
  • interconnect metal layer three is referred to by numeral 343.
  • Via 344 is a via used for connecting the third interconnect metal layer (i.e. M3) to the interconnect metal layer directly below which is the second interconnect metal layer (also referred to as "M2"). Via 344 is thus also referred to as Via (M3/M2).
  • the second interconnect metal layer (i.e. M2) is fabricated directly below the third interconnect metal layer.
  • interconnect metal layer two is referred to by numeral 345.
  • via 346 is a via used for connecting the second interconnect metal layer (i.e. M2) to the interconnect metal layer directly below which is the first interconnect metal layer (also referred to as "Ml" in the present invention). Via 346 is thus also referred to as Via (M2 M1).
  • the first interconnect metal layer (i.e. Ml) is fabricated directly below the second interconnect metal layer M2.
  • interconnect metal layer one is referred to by numeral 347.
  • contact 348 can be used for connecting the first interconnect metal layer (i.e. Ml) to the layer directly below Ml .
  • the layer directly below the first interconnect metal layer (which layer is not shown in Figure 3B) is, for example, silicon substrate, polysilicon, or an active region of silicon.
  • metal pad structure 374 consists of alternating segments of interconnect metal layer three (M3) and dielectric fillers. As shown in Figure 3B, each segment of interconnect metal layer three (M3) in metal pad structure 374 is designated as "M3.” Each interconnect metal segment M3 is separated by dielectric fillers designated as "D" (standing for "dielectric"). Metal pad structure 374 has the same size as bonding pad 360. However, unlike bonding pad 360, dielectric fillers are used in metal pad structure 374.
  • vias 373 are merely 1.0 micron in width and cannot provide adequate mechanical support for bonding pad 360. Vias 373 are used around the periphery of bonding pad 360 to primarily provide primarily electrical connection, and secondarily thermal contact, between bonding pad 360 and structure 374. Directly below the edges of metal pad structure 374 are vias 375. Below vias 375 there is metal pad structure 376. Metal pad structure 376 consists of alternating segments of interconnect metal layer two (M2) and dielectric fillers.
  • M2 interconnect metal layer two
  • each segment of interconnect metal layer two in metal pad structure 376 is designated as "M2.” Each interconnect metal segment M2 is separated by dielectric fillers designated as "D.”
  • Metal pad structure 376 has the same size as bonding pad 360. However, unlike bonding pad 360, dielectric fillers are used in metal pad structure 376. It is noted that in the copper bonding pad configuration shown in Figure 3B, vias 375 are merely 1.0 micron in width and cannot provide adequate mechanical support for metal pad structure 374 and bonding pad 360. Vias 375 are used around the periphery of metal pad structure 374 to primarily provide primarily electrical connection, and secondarily thermal contact, between metal pad structure 374 and structure 376. Immediately below the edges of structure 376 are vias 377.
  • Metal pad structure 378 consists of alternating segments of interconnect metal layer one (Ml) and dielectric fillers. As shown in Figure 3B, each segment of interconnect metal layer one in metal pad structure 378 is designated as "Ml.” Each metal segment Ml is separated by dielectric fillers designated as "D.” Metal pad structure 378 has the same size as bonding pad 360. However, unlike bonding pad 360, dielectric fillers are used in metal pad structure 378. It is noted that in the copper bonding pad configuration shown in Figure 3B, vias 377 are merely 1.0 micron in width and cannot provide adequate mechanical support for metal pad structures 376, 374, and bonding pad 360. Vias 377 are used around the periphery of metal pad structure 376 to primarily provide primarily electrical connection, and secondarily thermal contact, between metal pad structure 376 and structure 378.
  • metal pad structure 378 rests on silicon dioxide layer 394.
  • Metal pad structure 378 can be electrically connected to active semiconductor circuits or devices existing below silicon dioxide layer 394 through a number of contacts.
  • the substrate or circuits below silicon dioxide layer 394 are not shown in Figure 3B.
  • no dielectric fillers have been used in copper bonding pad 360. Since no dielectric fillers have been used in copper bonding pad 360, some dishing occurs as shown in Figure 3B. However, as stated above, due to the recent improvements in the CMP process, the dishing is not severe enough to create a hole in the central parts of bonding pad 360.
  • bonding pad 360 without any dielectric fillers as shown in Figure 3B.
  • other problems existing in the structure supporting bonding pad 360 make the use ofthe bonding pad configuration shown in Figure 3B unattractive. Some of these problems are discussed below.
  • low-k materials are used in copper IC chips in order to help reduce signal propagation delays in the chip.
  • dielectric material 392 which supports copper bonding pad 360 and structures 374 and 376 has a low dielectric constant.
  • cracks would develop in the low-k material 392.
  • Some of the cracks may develop immediately and some may develop later on. In any event the cracks cause an immediate damage to the circuits in the IC chip or cause a long term reliability problem.
  • low-k dielectric material 392 also exhibits poor thermal conductivity. The poor thermal conductivity results in an increase in the temperature ofthe semiconductor chip. It is well known in the art that an increase in the temperature ofthe semiconductor chip causes various problems that were discussed above.
  • bonding pad structure shown in Figure 3B is preferable to the bonding pad structure shown in Figure 3 A
  • the bonding pad structure of Figure 3B is still not satisfactory due to the fact that only a few narrow vias are used to provide mechanical support for bonding pad 360 and for structures 374 and 376.
  • bonding pad 360 does not receive adequate mechanical support from structures 374, 376, and 378 to withstand force 390 applied during bonding of bond wires.
  • structures 374 and 376 are themselves inadequately supported by few narrow vias 375 and 377 and by low-k dielectric material 392.
  • the structures supporting bonding pad 360 in Figure 3B, i.e. structures 374, 376, and 378 do not have high thermal conductivity since these structures must dissipate heat through low-k dielectric material 392 which in turn has poor thermal conductivity.
  • Bonding pad and support structure 400 ofthe present invention is also referred to as a "composite structure" in the present application.
  • substrate 450 is shown as supporting the entire bonding pad and support structure 400.
  • Substrate 450 can be silicon or other semiconductor. Active semiconductor circuits and devices existing on substrate 450 are not shown in Figure 4 to preserve simplicity.
  • Grown on top of substrate 450 is a layer of insulator 432 which is typically silicon dioxide. Silicon dioxide 432 is grown or deposited on substrate 450 according to methods well known in the art. With the exception of copper bonding pad 410 which is not covered, a passivation layer 411 covers the surface of bonding pad and support structure 400.
  • Reference column 440 in Figure 4 is for the purpose of illustration only and it shows four levels of metal and their respective vias stacked on top of each other.
  • Reference column 440 is used as a guide for the purpose of illustrating the various layers of metal and vias present in the IC chip containing bonding pad and support structure 400 ofthe present invention. However, it is manifest that the invention can be practiced in a fabrication process using greater than four interconnect metal layers or fewer than four interconnect metal layers.
  • Reference column 440 shows top interconnect metal layer 461.
  • the top interconnect metal layer in the present invention is also referred to as "M4.”
  • the top interconnect metal layer, i.e. M4 is the same layer in which bonding pad 410 is located. Directly below top interconnect metal layer 461 in reference column 440 is via 462.
  • Via 462 is a via used for connecting top interconnect metal layer (i.e. M4) to the interconnect metal layer directly below which is the third interconnect metal layer (also referred to as "M3" in the present invention). Via 462 is thus also referred to as Via (M4/M3).
  • the third interconnect metal layer (i.e. M3) is fabricated directly below the top interconnect metal layer.
  • interconnect metal layer three is referred to by numeral 463.
  • via 464 Directly below the third interconnect metal layer 463 in reference column 440 is via 464.
  • Via 464 is a via used for connecting the third interconnect metal layer (i.e. M3) to the interconnect metal layer directly below which is the second interconnect metal layer (also referred to as "M2" in the present invention). Via 464 is thus also referred to as Via (M3/M2).
  • the second interconnect metal layer (i.e. M2) is fabricated directly below the third interconnect metal layer.
  • interconnect metal layer two is referred to by numeral 465.
  • Via 466 is a via used for connecting the second interconnect metal layer (i.e. M2) to the interconnect metal layer directly below which is the first interconnect metal layer (also referred to as "Ml" in the present invention). Via 466 is thus also referred to as Via (M2/M1).
  • the first interconnect metal layer (i.e. Ml) is fabricated directly below the second interconnect metal layer M2.
  • interconnect metal layer one is referred to by numeral 467.
  • contact 468 can be used for connecting the first interconnect metal layer (i.e. Ml) to the layer directly below Ml which is substrate 450.
  • metal pad structure 422 is fabricated immediately above silicon dioxide layer 432.
  • Metal pad structure 422 comprises alternating interconnect metal layer one segments and dielectric fillers.
  • the alternating interconnect metal layer one segments and dielectric fillers are marked, respectively, as "Ml” and "D” in metal pad structure 422.
  • Figure 5 shows top view 500 of metal pad structure 422 ofthe present invention.
  • Metal pad structure 422 shown in Figure 4 is in effect a cross-section view of top view 500 along dashed line 422 in Figure 5.
  • the non-hatched areas 502 in Figure 5 correspond to the interconnect metal layer one segments in structure 422 in Figure 4 (each segment being marked as "Ml").
  • the hatched areas 504 in Figure 5 correspond to dielectric fillers marked as "D" in metal pad structure 422 of Figure 4. It is noted that metal pad structure 422 is fabricated simultaneously with fabrication of interconnect metal layer one. Referring to Figure 5, it is apparent that interconnect metal layer one segments 502 are electrically connected to each other since all the non-hatched areas in top view 500 correspond to areas where interconnect metal layer one exists in metal pad structure 422 of Figure 4. However, the cross-section along the dashed line 422 in Figure 5 is taken at a point where the interconnect metal segments appear to be unconnected, as they also appear to be unconnected in metal pad structure 422 in Figure 4. In fact (and as apparent in Figure 5), interconnect metal layer one segments in structure 422 of Figure 4 are electrically connected as shown in top view 500 in Figure 5.
  • via pad structure 420 is fabricated immediately above metal pad structure 422.
  • Via pad structure 420 is essentially a large via having geometry and dimensions that are substantially the same as the geometry and dimensions of bonding pad 410.
  • Via pad structure 420 includes via metal segments connecting the interconnect metal layer two segments in metal pad structure 418 to the interconnect metal layer one segments in metal pad structure 422.
  • Via pad structure 420 in fact comprises alternating segments of via metal and dielectric fillers. However, the alternating segments of via metal and dielectric fillers in via pad structure 420 are not apparent from Figure 4.
  • Figure 6 shows top view 600 of via pad structure 420 ofthe present invention.
  • Via pad structure 420 shown in Figure 4 is in effect a cross-section view of top view 600 along dashed line 420 in Figure 6.
  • the cross- hatched areas 602 in Figure 6 correspond to via metal segments in structure 420 in Figure 4.
  • the hatched areas 604 in Figure 6 correspond to dielectric fillers. It is noted that via pad structure 420 is fabricated simultaneously with fabrication of vias connecting interconnect metal layer two to interconnect metal layer one.
  • top view 600 in Figure 6 is taken at a point where there is a via metal segment as opposed to where there is a dielectric filler segment. Accordingly, only a via metal segment is shown in structure 420 in Figure 4. Moreover, it is apparent from top view 600 in Figure 6 that via metal segments 602 are electrically connected to each other since all the cross-hatched areas in top view 600 correspond to areas where via metal exists in via pad structure 420 of Figure 4.
  • metal pad structure 418 is fabricated immediately above via pad structure 420.
  • Metal pad sfructure 418 has geometry and dimensions that are substantially the same as the geometry and dimensions of bonding pad 410.
  • Metal pad structure 418 in fact comprises alternating segments of interconnect metal layer two and dielectric fillers. However, the alternating segments of interconnect metal layer two and dielectric fillers in metal pad structure 418 are not apparent from Figure 4.
  • Figure 7 shows top view 700 of metal pad structure 418 ofthe present invention.
  • Metal pad structure 418 shown in Figure 4 is in effect a cross-section view of top view 700 along dashed line 418 in Figure 7.
  • Non-hatched areas 702 in Figure 7 correspond to interconnect metal layer two segments in structure 418 in Figure 4.
  • Hatched areas 704 in Figure 7 correspond to dielectric fillers. It is noted that metal pad structure 418 is fabricated simultaneously with fabrication of interconnect metal layer two.
  • cross-section 418 in top view 700 in Figure 7 is taken at a point where there is an interconnect metal layer two segment as opposed to where there is a dielectric filler segment.
  • interconnect metal layer two segments 702 are electrically connected to each other since all the non-hatched areas in top view 700 correspond to areas where interconnect metal layer two exists in metal pad structure 418 of Figure 4. It is pointed out that as apparent from top view 700 in Figure 7 and top view 600 in Figure 6, in the present embodiment ofthe invention, the orientation of interconnect metal layer two segments 704 is the same as the orientation of via metal segments 604. In other words, in the present embodiment ofthe invention, interconnect metal layer two segments 704 are parallel to (and in fact aligned with) via metal segments 604.
  • interconnect metal layer two segments 704 can in fact be perpendicular to via metal segments 604. Indeed, interconnect metal layer two segments 704 can assume any angle of orientation with, respect to via metal segments 604 without departing from the scope ofthe present invention.
  • via pad structure 416 is fabricated immediately above metal pad structure 418.
  • Via pad structure 416 comprises alternating via metal segments and dielectric fillers. The alternating via metal segments and dielectric fillers are marked, respectively, as “V2" and "D” in via pad structure 416.
  • Figure 8 shows top view 800 of via pad structure 416 ofthe present invention. Via pad structure 416 shown in Figure 4 is in effect a cross-section view of top view 800 along dashed line 416 in Figure 8.
  • the cross-hatched areas 802 in Figure 8 correspond to the via metal segments in structure 416 in Figure 4 (each segment being marked as "V2").
  • the hatched areas 804 in Figure 8 correspond to dielectric fillers marked as "D" in via pad structure 416 of Figure 4. It is noted that via pad sfructure 416 is fabricated simultaneously with fabrication of vias connecting interconnect metal layer three to interconnect metal layer two.
  • via metal segments 802 are electrically connected to each other since all the cross-hatched areas in top view 800 correspond to areas where via metal exists in via pad structure 416 of Figure 4. However, the cross-section along the dashed line 416 in Figure 8 is taken at a point where the via metal segments appear to be unconnected, as they also appear to be unconnected in via pad structure 416 in Figure 4. In fact (and as apparent in Figure 8), via metal segments in structure 416 of Figure 4 are electrically connected as shown in top view 800 in Figure 8. As shown in the invention's bonding pad and support structure 400 in Figure 4, metal pad structure 414 is fabricated immediately above via pad structure 416. Metal pad structure 414 comprises alternating interconnect metal layer three segments and dielectric fillers.
  • FIG. 9 shows top view 900 of metal pad structure 414 ofthe present invention.
  • Metal pad structure 414 shown in Figure 4 is in effect a cross-section view of top view 900 along dashed line 414 in Figure 9.
  • the non-hatched areas 902 in Figure 9 correspond to the interconnect metal layer three segments in structure 414 in Figure 4 (each segment being marked as "M3").
  • the hatched areas 904 in Figure 9 correspond to dielectric fillers marked as "D” in metal pad structure 414 of Figure 4. It is noted that metal pad structure 414 is fabricated simultaneously with fabrication of interconnect metal layer three.
  • interconnect metal layer three segments 902 are electrically connected to each other since all the non-hatched areas in top view 900 correspond to areas where interconnect metal layer three exists in metal pad structure 414 of Figure 4. However, the cross- section along the dashed line 414 in Figure 9 is taken at a point where the interconnect metal segments appear to be unconnected, as they also appear to be unconnected in metal pad structure 414 in Figure 4. In fact (and as apparent in Figure 9), interconnect metal layer three segments in structure 414 of Figure 4 are electrically connected as shown in top view 900 in Figure 9.
  • interconnect metal layer three segments 904 are the same as the orientation of via metal segments 804.
  • interconnect metal layer three segments 904 are parallel to (and in fact aligned with) via metal segments 804.
  • interconnect metal layer three segments 904 may be perpendicular to via metal segments 804.
  • interconnect metal layer three segments 904 can assume any angle of orientation with respect to via metal segments 804 without departing from the scope ofthe present invention.
  • via pad structure 412 is fabricated immediately above metal pad structure 414.
  • Via pad structure 412 is essentially a large via having geometry and dimensions that are substantially the same as the geometry and dimensions of bonding pad 410.
  • Via pad structure 412 consists of only via metal and no dielectric fillers.
  • Figure 10 shows top view 1000 of via pad structure 412 ofthe present invention.
  • Via pad structure 412 shown in Figure 4 is in effect a cross-section view of top view 1000 along dashed line 412 in Figure 10.
  • the cross-hatched area 1002 in Figure 10 (which occupies the entire via pad structure) corresponds to via metal in structure 412 in Figure 4. It is noted that via pad structure 412 is fabricated simultaneously with fabrication of vias connecting interconnect metal layer four to interconnect metal layer three.
  • bonding pad 410 is the topmost structure in bonding pad and support structure 400 of Figure 4.
  • Bonding pad 410 typically has a square geometry with dimensions of sixty to one hundred microns on each side. The exact geometry and dimensions of bonding pad 410 can obviously vary without departing from the scope ofthe present invention.
  • bonding pad 410 is connected to metal pad structure 414.
  • Bonding pad 410 consists entirely of interconnect metal layer four and no dielectric fillers.
  • top view 1100 for fabricating bonding pad 410 is shown.
  • Bonding pad 410 shown in Figure 4 is in effect a cross-section view of top view 1100 along dashed line 410 in Figure 11.
  • the non-hatched area 1102 in Figure 1 1 consists of interconnect metal layer four. It is noted that bonding pad 410 is fabricated simultaneously with fabrication of interconnect metal layer four.
  • bonding pad and support structure 400 is implemented in an IC chip using copper for interconnect metal layers, copper as via metal as well as a copper bonding pad 410.
  • all the various interconnect metal layers one, two, three, and four in bonding pad and support structure 400 are made of copper, or substantially of copper.
  • all the dielectric fillers in structures 422, 420, 418, 416, and 414 consist of low-k dielectrics.
  • Examples of low-k dielectrics that can be utilized as dielectric fillers in structures 422, 420, 418, 416, and 414 are: porous silica (with a dielectric constant of 1.2 to 2.3), fluorinated amorphous carbon (with a dielectric constant of 2.0 to 2.6), fluoro-polymer (with a dielectric constant of 1.9 to 2.), parylene (with a dielectric constant of 2.2 to 2.9), polyarylene ether (with a dielectric constant of 2.6 to 2.8), silsesquioxane (with a dielectric constant of 2.5 to 3.0), fluorinated silicon dioxide (with a dielectric constant of 3.2 to 3.6), and diamondlike carbon (with a dielectric constant of 2.4 to 2.8).
  • porous silica with a dielectric constant of 1.2 to 2.3
  • fluorinated amorphous carbon with a dielectric constant of 2.0 to 2.6
  • fluoro-polymer with a dielectric constant of 1.9 to 2.
  • dielectrics have a dielectric constant below the widely used dielectrics silicon dioxide (having a dielectric constant of approximately 4.0) and silicon nitride (having a dielectric constant of approximately 7.0).
  • the preferred process for fabricating copper chips is a damascene process accompanied by the CMP process. Due to the CMP process, dishing occurs in bonding pad 410 as shown in Figure 4. However, it is noted that a via pad structure (i.e. via pad structure 412 in Figure 4) exists under the entire bonding pad 410. In the preferred embodiment ofthe invention, via pad structure 412 has substantially the same geometry and dimensions and bonding pad 410.
  • interconnect metal layer four from which bonding pad 410 is fabricated is typically between 0.2 microns and 1.0 microns thick
  • the via metal directly below in via pad structure 412 has a typical thickness of between 0.3 and 1.0 microns. Accordingly, via pad structure 412 significantly adds to the effective thickness of bonding pad 410. Due to the increase in the effective thickness of bonding pad 410, the dishing that occurs in bonding pad 410 as a result ofthe CMP process is not severe enough to create a hole in bonding pad 410. Accordingly, via pad structure 412 existing under bonding pad 410 is an added assurance that the dishing problem would not be severe enough to require dielectric fillers in bonding pad 410. As such, no dielectric fillers are used in bonding pad 410.
  • bonding pad 410 preserves the adhesiveness of bond wires to bonding pad 410, increases thermal conductivity of bonding pad 410, and results in a stronger electrical connection between bond wires and bonding pad 410.
  • CMP process is utilized at each stage of fabrication and patterning of copper interconnect metal layer in a copper IC chip and not merely at the final stage of patterning the top copper interconnect metal layer.
  • a damascene process is used to lay interconnect metal (i.e. copper) into a trench (or into a trench having dielectric fillers therein).
  • the in-laid copper then undergoes chemical and mechanical polishing as explained above.
  • metal pad structure 414 (alternating interconnect metal layer three segments and dielectric fillers), via pad structure 416 (alternating via metal segments and dielectric fillers), metal pad structure 418 (alternating interconnect metal layer two segments and dielectric fillers), via pad structure 420 (alternating via metal segments and dielectric fillers), and metal pad structure 422 (alternating interconnect metal layer one segments and dielectric fillers) all utilize dielectric fillers.
  • the use of alternating interconnect metal segments and dielectric fillers, or alternating via metal segments and dielectric fillers, in the structures below via pad structure 412 results in prevention of dishing in those structures.
  • dielectric fillers in bonding pad 410 would have caused a severe disadvantage in that the use of dielectric fillers would have reduced the adhesiveness of bond wires to bonding pad 410.
  • adhesion to bond wires is not a requirement for the structures below via pad structure 412
  • that particular disadvantage ofthe dielectric fillers i.e. the causing of a reduction in adhesiveness to bond wires, would not be a factor for structures 414, 416, 418, 420, and 422 which are located below via pad structure 412.
  • the advantages of dielectric fillers such as the causing of an even profile for the structures below via pad structure 412 outweigh their potential disadvantages since a reduction of adhesion to bond wires is no longer a factor.
  • the present invention utilizes dielectric fillers in structures 414, 416, 418, 420, and 422 which are located below via pad structure 412.
  • top view 500 corresponds to the alternating segments of interconnect metal layer one and dielectric fillers in metal pad structure 422 in Figure 4
  • top view 600 corresponds to the alternating via metal segments and dielectric fillers in via pad structure 420 of Figure 4
  • top view 700 corresponds to the alternating segments of interconnect metal layer two and dielectric fillers in structure 418 of Figure 4
  • top view 800 corresponds to the alternating via metal segments and dielectric fillers in structure 416 of Figure 4
  • top 900 corresponds to the alternating segments of interconnect metal layer three and dielectric fillers in structure 414 of Figure 4.
  • These top views, i.e. top views 500, 600, 700, 800, and 900 all correspond to the structures located directly below via pad structure 412 and were shown in Figures 5, 6, 7, 8, and 9, respectively.
  • top views 500, 600, 700, 800, and 900 illustrates the composition of various columns in bonding pad and support structure 400 of Figure 4.
  • the vertical-hatched areas indicate an overlay of areas in metal pad structures and via pad structures which result in a column having metal only.
  • the vertical-hatched areas indicate columns where only interconnect metal and via metal are present and are connected together in a vertical column of solid metal. Therefore, looking down from via pad structure 412, there is a continuous column of solid metal all around the four sides of via pad structure 412 as shown in Figure 12. This continuous column of solid metal around the four sides of via pad structure 412 is pointed to by numerals 1202 in
  • An example of one of these sixteen discontinuous columns of solid metal is referred to by numeral 1208 in Figure 12.
  • the columns of solid metal support referred to by numeral 1208 are also supported by silicon dioxide layer 432 ( Figure 4).
  • the remaining columns in Figure 12 are discontinuous columns having either dielectric fillers only or discontinuous columns comprising dielectric fillers, interconnect metal, and via metal.
  • An example of one of these twenty five discontinuous columns is referred to by numeral 1204 in Figure 12.
  • FIG. 12 there are forty discontinuous columns comprising dielectric fillers, interconnect metal, and via metal. These forty discontinuous columns are shown as dotted areas in Figure 12.
  • An example of one of these forty discontinuous columns is referred to by numeral 1206 in Figure 12.
  • bonding pad 410 has a continuous column of solid metal support around all sides of bonding pad 410 as well as, in this exemplary embodiment, sixteen internal and discontinuous columns of solid metal support.
  • areas 1202, 1208, and 1206 in Figure 12 correspond to columns of solid metal support or columns where there is some support from metal.
  • the mechanical and thermal support provided for bonding pad 410 is made up either entirely of columns of solid metal or of columns of interconnect metal, via metal, and dielectric.
  • the phrase "columns of solid metal” refers to columns where there is copper metal interconnect and copper via metal. Because ofthe significant solid metal support provided for bonding pad 410 by the continuous column consisting of only copper metal interconnect and copper via metal (i.e. continuous column 1202 in Figure 12) as well as the significant solid metal support provided by the discontinuous columns consisting of only copper metal interconnect and copper via metal (i.e. the sixteen discontinuous columns 1208 in Figure 12), the mechanical and thermal characteristics of bonding pad 410 are significantly improved. Unlike the present copper bonding pad structures, bonding pad and support structure 400 ofthe present invention has a solid metal support at many locations of thereof.
  • This solid metal support results in a marked improvement in thermal conductivity ofthe invention's bonding pad 410.
  • all the columns of solid metal used under bonding pad 410 are in fact great thermal conductors.
  • the prior art bonding pad structures must dissipate heat primarily through layers of low-k dielectrics which have poor thermal conductivity.
  • the invention's bonding pad's improved thermal conductivity results in an improved operation ofthe semiconductor circuits present in the IC chip.
  • Another advantage of existence of a number of columns of solid metal support is the improved mechanical support provided for bonding pad 410.
  • low-k dielectric materials have poor mechanical strength and may crack during the bonding process.
  • the prior art bonding pad structures rest primarily on layers of low-k dielectrics which exhibit poor mechanical support.
  • the addition of a continuous solid metal column all around the four sides of bonding pad 410 along with a number of internal and discontinuous solid metal columns result in a significant improvement in the mechanical strength ofthe invention's bonding pad 410 during the bonding process.
  • the improved mechanical strength ofthe invention's bonding pad 410 results in an improved yield and reliability ofthe IC chip.
  • bonding pad and support structure 400 ofthe present invention is that the continuous solid metal support referred to by numeral 1202 in Figure 12 effectively provides a solid wall or a solid metal seal around all sides of bonding pad and support structure 400.
  • the solid metal seal created by continuous solid metal support 1202 prevents any cracks developed in the dielectric below bonding pad 410 to propagate to semiconductor circuits and devices located outside the solid metal seal created by continuous solid metal support 1202.
  • the semiconductor circuits and devices neighboring bonding pad and support structure 400 are isolated from any cracks that may develop in the dielectric below bonding pad 410 during the bonding process.
  • interconnect metal layer two segments 704 can in fact be perpendicular to via metal segments 604 ( Figure 6). Indeed, interconnect metal layer two segments 704 can assume any angle of orientation with respect to via metal segments 604 without departing from the scope ofthe present invention. Moreover, it is apparent to those skilled in the art that in other embodiments ofthe invention interconnect metal layer three segments 904 ( Figure 9) may also be perpendicular to via metal segments 804 ( Figure 8). In fact, interconnect metal layer three segments 904 can assume any angle of orientation with respect to via metal segments 804 without departing from the scope ofthe present invention.
  • the orientation of interconnect metal segments in their respective metal pad structures and the orientation of via metal segments in their respective via pad structures can be modified, the present invention is still applicable. The reason is that even when orientation ofthe interconnect metal segments and via metal segments are modified, the modification can be such that columns of solid metal support under bonding pad 410 still exist.
  • the invention's bonding pad 410 is particularly suitable for an IC chip using copper as interconnect metal and via metal and damascene and CMP processes. Because via pad structure 412 is laid out below the entire area of bonding pad 410, the invention's bonding pad 410 has additional support from the solid metal pad constituting via pad structure 412. Because of this additional metal support from via pad structure 412, the invention's bonding pad 410 is more tolerant to dishing.
  • bonding pad 410 has been effectively increased by the addition of via pad structure 412 under bonding pad 410. Accordingly, there is no possibility that a dielectric layer below bonding pad 410 and via structure 412 would be exposed as a result ofthe dishing problem during the CMP process. It is important not to expose any dielectric below the bonding pad since it would be difficult or impossible to bond wires to the bonding pad if any dielectric is exposed. It is noted that the invention's bonding pad and support structure 400 is intended to be implemented in a copper IC chip and as such the fabrication of bonding pad and support structure 400 is compatible with the general processing of a copper IC chip.
  • the fabrication ofthe invention's bonding pad and support structure 400 does not add any incompatibilities or complications in the processing ofthe copper IC chip. It is further noted that the above detailed description in the present application was directed to a specific embodiment ofthe present invention. However, the invention's principles are obviously applicable to a number of other embodiments ofthe present invention.
  • bonding pad 410 and via pad structure 412 will also include dielectric fillers. Use of dielectric fillers in bonding pad 410 and in via pad structure 412 would result in a reduction of dishing in bonding pad 410 and in via pad structure 412. When dielectric fillers are used in bonding pad 410, an aluminum layer can be deposited over bonding pad 410 in order to improve adhesion of bond wires to bonding pad 410.
  • the present embodiment ofthe invention was described in relation to a process having four layers of interconnect metal, the invention applies to a process having any number of interconnect metal layers. Specifically, the invention can be applied to a process having only two interconnect metal layers, only three interconnect metal layers, or five or more interconnect metal layers. Moreover, although the embodiment ofthe present invention described herein uses copper as the interconnect of choice for the bonding pad, the invention can be applied to a process where aluminum or some other metal is used in the bonding pad.
  • interconnect metal layer one various layers of interconnect metal, such as interconnect metal layer one, interconnect metal layer two, and interconnect metal layer three were made of copper.
  • these layers of interconnect metal may be made of other types of metals, such as aluminum, without departing from the scope ofthe present invention.
  • each ofthe interconnect metal layers in metal pad structures 422, 418, and 414 may be made of aluminum instead of copper.
  • the via metal used in via pad structures 420 and 416 is tungsten (instead of copper).
  • the dielectric fillers used by the present invention in the via pad structures are still useful and beneficial. By using dielectric fillers in via pad structures using tungsten several advantages are achieved.
  • the present invention's bonding pad and support structure 400 presents several advantages even when the interconnect metal layers are made of aluminum (as opposed to copper) and when the via metal is tungsten (as opposed to copper).
  • An aspect ofthe present invention described is the creation of columns having only interconnect metal and via metal to support the bonding pad.
  • the specific embodiment described in the present application illustrated a certain configuration of various alternating segments of interconnect metal and dielectric fillers, it is appreciated that the invention generally teaches columns of metal support for the bonding pad that are comprised of only via metal and interconnect metal.
  • the columns are metal support are not limited to the configurations disclosed in the specific embodiments described in the present application.
  • support structures having fewer or greater segments of interconnect metal, via metal, or dielectric fillers can be designed.
  • the alternating segments of interconnect metal, via metal, or dielectric fillers can be square, rectangular, circular, triangular, or of any other geometry and/or dimensions without departing from the principles ofthe present invention.
  • Bonding pads are typically square having dimensions of sixty microns up to one hundred microns on each side.
  • the principles ofthe invention can be applied to any bonding pad of any geometry and any dimension or in fact to any "wide" interconnect layer whether or not used as a bonding pad.
  • the invention's bonding pad and support structure overcome the serious need in the art by providing sufficient mechanical support and strength for the bonding pad, good thermal conductivity, strong electrical connection with bond wires, and good adhesion to bond wires while being more tolerant to the potential dishing problem existing in damascene and CMP processing.

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Abstract

L'invention concerne un élément de liaison en cuivre (422) directement supporté par une structure en cuivre par élément (420), cette structure possède quasiment la même géométrie et les mêmes dimensions que l'élément de liaison en cuivre (422). La combinaison de l'élément de liaison en cuivre (422) et de la structure en cuivre (420) par élément permet d'augmenter efficacement l'épaisseur de l'élément de liaison en cuivre. Grâce à cette augmentation efficace de l'épaisseur de l'élément de liaison, l'élément de liaison est plus tolérant aux éventuels problèmes de bombage entraînés par le procédé CMP. Des structures supplémentaires d'élément métallique et des structures par élément sont utilisés au-dessous de l'élément de liaison. Les structures supplémentaires d'élément métallique (422) et les structures par élément (420) comprennent des segments alternés de métal interconnecté (M3) et des agents de remplissage diélectriques (D) et des segments alternés par métal (M2) et des agents de remplissage diélectriques (D) respectivement.
PCT/US2001/043215 2000-11-20 2001-11-19 Structure d'element de liaison et procede de fabrication de ce dernier WO2002043144A1 (fr)

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US09/716,350 US6740985B1 (en) 1999-12-16 2000-11-20 Structure for bonding pad and method for its fabrication
US09/716,350 2000-11-20

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Cited By (2)

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EP1548815A1 (fr) * 2002-08-30 2005-06-29 Fujitsu Limited Dispositif a semi-conducteur et son procede de fabrication
US7692315B2 (en) 2002-08-30 2010-04-06 Fujitsu Microelectronics Limited Semiconductor device and method for manufacturing the same

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US6239386B1 (en) * 1994-07-19 2001-05-29 Tessera, Inc. Electrical connections with deformable contacts
US6313540B1 (en) * 1998-12-25 2001-11-06 Nec Corporation Electrode structure of semiconductor element
US6362531B1 (en) * 2000-05-04 2002-03-26 International Business Machines Corporation Recessed bond pad
US6365970B1 (en) * 1999-12-10 2002-04-02 Silicon Integrated Systems Corporation Bond pad structure and its method of fabricating
US6708088B2 (en) * 2001-04-24 2004-03-16 Fuji Jukogyo Kabushiki Kaisha Vehicle behavior control apparatus

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US6239386B1 (en) * 1994-07-19 2001-05-29 Tessera, Inc. Electrical connections with deformable contacts
US6313540B1 (en) * 1998-12-25 2001-11-06 Nec Corporation Electrode structure of semiconductor element
US6365970B1 (en) * 1999-12-10 2002-04-02 Silicon Integrated Systems Corporation Bond pad structure and its method of fabricating
US6198170B1 (en) * 1999-12-16 2001-03-06 Conexant Systems, Inc. Bonding pad and support structure and method for their fabrication
US6362531B1 (en) * 2000-05-04 2002-03-26 International Business Machines Corporation Recessed bond pad
US6708088B2 (en) * 2001-04-24 2004-03-16 Fuji Jukogyo Kabushiki Kaisha Vehicle behavior control apparatus

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1548815A1 (fr) * 2002-08-30 2005-06-29 Fujitsu Limited Dispositif a semi-conducteur et son procede de fabrication
EP1548815A4 (fr) * 2002-08-30 2005-09-28 Fujitsu Ltd Dispositif a semi-conducteur et son procede de fabrication
US7692315B2 (en) 2002-08-30 2010-04-06 Fujitsu Microelectronics Limited Semiconductor device and method for manufacturing the same
US8034703B2 (en) 2002-08-30 2011-10-11 Fujitsu Semiconductor Limited Semiconductor device and method for manufacturing the same
US8089162B2 (en) 2002-08-30 2012-01-03 Fujitsu Semiconductor Limited Semiconductor device and method for manufacturing the same

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