WO2002037571A1 - Small-scale structures - Google Patents

Small-scale structures Download PDF

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Publication number
WO2002037571A1
WO2002037571A1 PCT/GB2001/004793 GB0104793W WO0237571A1 WO 2002037571 A1 WO2002037571 A1 WO 2002037571A1 GB 0104793 W GB0104793 W GB 0104793W WO 0237571 A1 WO0237571 A1 WO 0237571A1
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WIPO (PCT)
Prior art keywords
small
scale element
layers
layer
gap
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Application number
PCT/GB2001/004793
Other languages
French (fr)
Inventor
Pier-John Anthony Sazio
Christopher John Bristow Ford
Douglas Paul
Neil Clement Greenham
Alexander Giles Davies
Per Johan Lundgren
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Cambridge University Technical Services Ltd
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Priority to AU2002210735A priority Critical patent/AU2002210735A1/en
Publication of WO2002037571A1 publication Critical patent/WO2002037571A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0895Tunnel injectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/88Tunnel-effect diodes
    • H01L29/882Resonant tunneling diodes, i.e. RTD, RTBD
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/20Organic diodes
    • H10K10/23Schottky diodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40Organic transistors
    • H10K10/46Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462Insulated gate field-effect transistors [IGFETs]
    • H10K10/491Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]

Definitions

  • This invention relates to the provision of structures incorporating small-scale elements, for example, in the nanometre scale.
  • a method of manufacturing a functional device structure comprising at a minimum the steps of: forming a first layer of material; forming a second layer of material on the first layer; forming a third layer of material on the second layer; and treating the layer structure such that in its simplest embodiment a gap is formed between the 1 ST and 3 RD layers, the size of the- gap being sufficient to have a component therein in use.
  • the method also comprises the step of placing a small- scale element near the gap.
  • the layers may be formed by one of a number of known manufacturing techniques, such as those used in the manufacture of CMOS devices.
  • the small-scale element may be held within the gap.
  • the at least two layers of material may be metallic or may be semiconductor material and may be heavily doped.
  • the gap may be a region where the physical, magnetic, optical, chemical, ' or other properties of which differ from these on either side of it.
  • the small-scale element may have a width of less than 20 ⁇ m, less than l ⁇ , less than 200nm, less than 50nm or less than 20nm.
  • the at least two layers may be separated by at least another layer that is formed from insulating material, such as silicon dioxide.
  • Oh ic contacts may be formed to the layers of semiconductor material.
  • the at least two layers, when they are formed of either metallic or semiconductor material may be arranged to act -as electrodes which contact the small-scale elements .
  • the small-scale elements may be configured such that the structure acts as resonant tunnelling diode, a transistor, a logic element or a memory element, for example.
  • Other possibilities include small-scale elements which have particular optical, magnetic, or chemical properties, or which have more complex functionality such as miniature integrated circuits .
  • the small-scale elements may be metallic or semiconductor nanoparticles, or molecules which may be conjugated, for example.
  • Appropriate anchors may be attached to, or- incorporated in, the small-scale elements to facilitate, for example, adhesion, electrical contact, or orientation.
  • These anchors may be the end-groups of specific molecules, which may be the small-scale elements themselves, or may be attached to the small-scale elements.
  • Other examples include mechanical or magnetic anchors.
  • The. structure may be stacked on top of one or more other such structures, to make a number of gaps.
  • the structures may be nested one inside another, by replacing one or more layers by a set of layers, to make extra contacts to the small-scale elements or to contact different small-scale elements.
  • the structure may be connected to conventional electronic circuitry on the same substrate, such as a MOSFET.
  • an electrical device comprising: a small-scale element of size less than 100 nm; and at least one electrode providing electrical contact to the small-scale element, the electrode being formed from a semiconducting material.
  • the semiconductor material may be highly doped.
  • Electrodes there may be two or more electrodes, in which case, one electrode may be metallic instead of semiconducting.
  • the energy levels, barriers, and binding to the semiconductor may be controlled by the usual methods of synthetic organic chemistry, for example using longer conjugated segments to lower energy levels. . .
  • More than one small-scale element may be assembled in parallel between any pair of electrodes, giving a larger overall device current and/or redundancy. Small-scale elements may be assembled between the electrodes in series, giving a structure with different current-voltage characteristics. If there are two semiconductor electrodes they may be either the same or different types.
  • the device may be based on injection of electrons from an n-type semiconductor or holes from a p-type semiconductor .
  • Figures 1 to 6 are schematic vies of examples of the present invention
  • Figure 7 is a diagram showing a molecular system configured to operate as a resonant tunnelling diode structure
  • Figure 8 is a schematic diagram of a small-scale element
  • Figure 9 is a scanning electron micrograph of an example of the present invention.
  • Figure 10 is a graph showing the current-voltage characteristics for each of the set of selectively etched MOSFET devices manufactured in accordance with the present invention. • ⁇
  • Figures 1 and 2 ( Figure 2 being a cross-section of Figure 1) show an example of the invention,- • a layered structure consisting of, in tis case, a semiconductor substrate 10 and two ohmic contacts 11, 12. Between these ohmic contacts 11, 12 are two substantially parallel electrodes 14 and a layer of an insulating material 13.
  • the electrodes 14 may be formed of a variety of materials depending on the electrical properties required. Generally they are formed of heavily doped (n-type or p-type) semiconductors such as Si or polysilicon, GaAs or InAs .
  • the two electrodes 14 may be formed of the same material or one may be a different semiconductor or a metallic electrode. Alternatively, they may be two semiconductor electrodes doped differently fro one another.
  • the layer 13 may be selectively etched, dissolved or otherwise partially removed to allow incorporation of a small-scale element or elements.
  • Selected layers of the structure may also be doped with either n-type or p-type impurities to achieve the desired properties.
  • a MOSFET-like layer structure Si substrate coated with Si0 2 and then polysilicon provides a suitable set of layers for selective etching of the insulating Si0 2 layer. This is compatible with standard CMOS processing .
  • a Silicon-On-Insulator (SOI) wafer may be used to provide the layer structure.
  • SOI wafers can be made by fusing together the surface oxide layers of two silicon wafers, a standard process called wafer bonding.
  • Small-scale elements 15 are held inside the gap 20 formed where the insulator layer 13 has been removed, between the two substantially parallel layers 14.
  • the size of this gap can be controlled precisely since it is determined mainly by the thickness of layer 13, which itself may be controlled with a precision comparable to an atomic layer thickness. This can be. done using standard deposition techniques.
  • deposition includes precipitation, coating or oxidation or other chemical or physical reaction from a solution, melt or fluid or the accumulation of material from evaporated or sputtered species.
  • the small-scale elements 15 are chosen, in this example, by their electrical, chemical, optical, magnetic or biological properties and are typically of 2-10 nm in diameter.
  • They may be semiconductor nanocrystals of II-VI or III-V semiconductors, for example, CdSe, CdS, InAs, InP; or conjugated molecules which rely on electron delocalisation along one or. more conjugated regions in order to conduct electricity; or complex carbon forms such as C 60 , carbon nanotubes and other Buckminsterfullerene derivatives.
  • More than one small-scale element 15 may be assembled in parallel to give a larger overall current or redundancy, for example.
  • the layered structure of the present invention can be used, along with appropriate small-scale element (s) to form any one of a number of electronic components such as a logic gate, memory element, diode etc.
  • the electrodes 14 may be selectively doped, for example by ion- implantation, only on either side of the gaps 20 where the insulator 13 has been removed.
  • the electrodes 14 may be modified to include a metallic layer between each electrode 14 and the layer 13 between them.
  • a metal may be incorporated on each silicon surface to form a suicide, before oxidation and wafer bonding.
  • the suicide surface could be designed to have a smaller depletion depth than that at the surface of silicon, with a smaller native oxide thickness, whilst providing a- reliable anchor for the nanoscale components.
  • FIG. 1 is one example of a device which may have electrodes formed from semiconductor material.
  • suitable nanoscale elements are semiconducting nanocrystals such as CdS or CdSe, or conducting molecules.
  • the spacing of the energy levels in the small-scale element should be larger than the Fermi energy in the electrodes, hence their size in- this example must typically be less than 100 nm.
  • suitable electrodes are, in this case Si, SiGe, GaAs, I As .
  • the small-scale element is separated from the two • ⁇ ⁇ • • - electrodes by tunnel barriers.
  • the tunnel barriers may be formed from insulating material- on the semiconductor electrodes, or engineered into the small-scale element itself, or a combination of both. This allows a hybrid 5 device composed of semiconductors and small-scale elements to behave as a resonant tunnelling diode (RTD) , exhibiting negative differential resistance (NDR) .
  • RTD tunnelling diode
  • NDR negative differential resistance
  • a quantised level in the small-scale element lines up with occupied conduction 0 band states in one of the semiconductor electrodes, and with empty conduction band states in the other electrode, leading to resonant tunnelling through that level.
  • the width in energy of the occupied conduction band states in the semiconductor (the distance from the bottom of the 5 conduction band to some point in the tail of the Fermi distribution) is small compared with that in a metal.
  • the bias may therefore be increased until the state in the small-scale element drops below the conduction band. It is then no longer resonant with states in the electrodes and 0 so tunnelling can no longer take place, thus decreasing the current and giving NDR. This assumes that the state in the small-scale element is separated from the next lowest state by more than the Fermi energy, so that the next state does not come onto resonance before the first has gone off 5 resonance. If this condition is satisfied, it may be possible to observe multiple NDR peaks, as each state passes through the conduction band.
  • the tunnel barrier may include a ligand on the surface of the nanocrystal, and/or a layer of molecules deposited on the semiconductor surface.
  • the ligand or molecule may be designed with 5 specific end-groups to facilitate binding of the nanocrystal to the semiconductor surface.
  • the ligand or molecule may be designed in order to optimise its tunnelling resistance, for example by exchanging the nanocrystal ligands with ones of different length, or by introducing conjugated units in order to reduce the height of the tunnelling barrier.
  • the quantised energy levels of a nanocrystal may be tuned by changing its size, through the quantum confinement effect, allowing the position of the NDR peak to be controlled and optimised for device applications.
  • Figure 3 shows one example configuration similar to that in figures 1 and 2, but incorporating an extra metal strip 19 which is deposited, for example by evaporation, on one edge of the structure.
  • the strip 19 has a break 21 formed therein where it passes over the gap 20.
  • the strip 19 provides, in this example, reliable anchoring and/or contacts for the small-scale element.
  • the layers 14 are formed of undoped semiconductor and the gap 20 is formed by selective etching to define the dimensions of a break 21 in the metal strip.
  • the small-scale element 15 is held.
  • This example may be adapted such that the layers 14 also act as ' electrodes insulated from the metal strip 19. This allows as many as four contacts to the small-scale element 15. Appropriate end groups on the small-scale elements could be used to ensure correct orientation.
  • Figure 4 shows a further example configuration where no selective etching has taken place and the insulating layer 13 between the semiconductor electrodes 14 is simply used to define the dimension across which the small-scale elements 15 will assemble.
  • This is similar to the example shown in Figures 1 and 2 except that there is no selective etching used to form the gap 20 which in this case simply exists because of the properties of the insulating layer 13 and the electrodes 14.
  • Figure 5 shows an example of the present invention, similar to that of Figure 3, with, in this example, a doped polysilicon gate 17 replacing the insulator layer 13 and with the layers 14 being insulating.
  • This example also comprises a metal strip 19 with break 21 within which there is a small-scale element close to the gate 17.
  • the gate 17 can be used to affect the properties of the small-scale elements .
  • Figure 6 shows a further example which is similar to that in figures 1 and 2, but which introduces an additional conducting gate layer 22 which is electrically isolated from the electrodes 14, but which may be connected to an additional ohmic contact elsewhere.
  • an additional conducting gate layer 22 which is electrically isolated from the electrodes 14, but which may be connected to an additional ohmic contact elsewhere.
  • a gap 20 (or break 21) fabricated as in one of the examples above ( Figures 1-6) may be immersed in a fluid.
  • This fluid may contain small- scale elements. The presence, or other properties of the elements or fluid, may be detected or measured when they are in close proximity to the gap 20 or break 21, using the structure.
  • a voltage may be applied between the electrodes 14 or 19 on either side of " the gap to produce an electric• field within the gap 20. This may polarise a small-scale element 15, such as a linear molecule or metal nanoparticle, so that it bridges the gap
  • the voltage may be oscillating at radio
  • the set of layers 14, 13 forming the gap structure may be repeated to form a stack of gaps 20, each gap containing one or more small-scale elements.
  • the small-scale elements 15 and layers 14, 13 need- not be the same in each set.
  • the small-scale elements 15 may in fact be small pieces of material containing one- or more devices, such as miniature integrated circuits, which may be fabricated in large quantities and then split up, immersed in a fluid to form, in this example, a colloidal suspension.
  • the width of the gap 20 may be chosen to be slightly greater than the thickness of the small-scale elements 15, so that the small-scale elements 15 may slot into the gaps.
  • each -small-scale element 15 may be incorporated on each -small-scale element 15 to cause them to become attached, with the desired orientation, to matching structures or coatings on some of the layers 14, 13 or 19, when they have slotted into a gap. This may enable the fabrication • of three-dimensional integrated circuits, without the need to fabricate each layer sequentially.
  • Figure "7 - is a diagrammatic representation of the structure of one of the small-scale elements 15 that may be employed in the examples of the present invention shown in the previous figures. It is a molecular system with precisely engineered length, operating as, in this example, a resonant tunnelling diode structure.
  • Figure 8 shows a generic small-scale element 15 to be held in the gap 20 or break 21 of any of the earlier examples of the present invention.
  • This small-scale element 15 may take the form of, for example, a conjugated molecule or CdSe nanocrystal with integral linker molecules.
  • Figure 9 shows a scanning electron micrograph of an example of the present invention as shown in any of the above schematic representations.
  • the micrograph shows a stack of alternating GaAs and AlAs layers in which the lOnm thick AlAs layers (dark bands) have been selectively etched as described with reference to, for example, Figure 1 above .
  • Figure 10 is a graph showing the current voltage characteristics for a set of selectively etched moss fit devices.
  • the substrate is of the n+ type, with 14 nm oxide gaps .
  • the dash-dotted curves show the devices before any etching, with the solid lines being after an HF-etch.
  • the dash-dotted lines show the characteristics of the devices after subsequent exposure to nanocrystals in toluene. When nanocrystals are present, the current below 4 volts is increased by up to 3 orders of magnitude, and NDR is visible.
  • Each device in the set shows similar features as one would expect for a selective etch which gives uniformity between devices.

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Abstract

A structure formed from at least two layers of material separated by at least another layer. The layers are formed and/or processed such that a gap is formed between the at least two layers. At least one small-scale element is within the gap. There is further provided a method of manufacturing a functional device structure. The method comprises the steps of forming a first layer of material; forming a second layer of material on the first layer; forming a second layer of material on the first layer; forming a second layer material on the second layer; and treating the layer structure such that in its simplest embodiment a gap is formed between the 1st and 3 rd layers, the size of the gap being sufficient to have a component therein in use.

Description

SMALL-SCALE STRUCTURES
This invention relates to the provision of structures incorporating small-scale elements, for example, in the nanometre scale.
It is well known that there has been a continued drive towards the provision of semiconductor structures of smaller and smaller scale. Recently there have been proposals to produce devices which have elements in the scale of nanometres. In terms of reduction of scale, nanometre-scale devices generally operate by tunnelling and are therefore highly sensitive to atomic-layer fluctuations in barrier thicknesses. This can result in variations from device to device that are unacceptable in terms of consistency of manufacture. Problems such as this have impeded the full exploitation of nanometre-scale devices. However, there is potential for production of molar quantities of such devices via chemical synthesis (with the resulting identical manufacture of each device) , and therefore such devices have extremely desirable potential benefits. In addition, there is the potential for such devices to be self-assembled by employing thermodynamically driven techniques. However, the provision of such devices brings with it particular problems in relation to the retention of and electrical contact with such devices so that their full benefit can be exploited.
Accordingly, there is a need to provide structures which can control the position of, and enable adequate contact with, small-scale elements so that their full potential can be realised.
According to the present invention there is provided a structure formed from at least two layers of material separated by at least another layer, the layers being formed and/or processed such that a gap is formed between the at least two layers; and at least one small-scale element within the gap. According to the present invention there is further provided a method of manufacturing a functional device structure, the method comprising at a minimum the steps of: forming a first layer of material; forming a second layer of material on the first layer; forming a third layer of material on the second layer; and treating the layer structure such that in its simplest embodiment a gap is formed between the 1ST and 3RD layers, the size of the- gap being sufficient to have a component therein in use.
The method also comprises the step of placing a small- scale element near the gap.
The layers may be formed by one of a number of known manufacturing techniques, such as those used in the manufacture of CMOS devices.
The small-scale element may be held within the gap.
The at least two layers of material may be metallic or may be semiconductor material and may be heavily doped. The gap may be a region where the physical, magnetic, optical, chemical,' or other properties of which differ from these on either side of it. The small-scale element may have a width of less than 20μm, less than lμ , less than 200nm, less than 50nm or less than 20nm.
The at least two layers may be separated by at least another layer that is formed from insulating material, such as silicon dioxide. Oh ic contacts may be formed to the layers of semiconductor material.
The at least two layers, when they are formed of either metallic or semiconductor material may be arranged to act -as electrodes which contact the small-scale elements .
The small-scale elements may be configured such that the structure acts as resonant tunnelling diode, a transistor, a logic element or a memory element, for example. Other possibilities include small-scale elements which have particular optical, magnetic, or chemical properties, or which have more complex functionality such as miniature integrated circuits .
The small-scale elements may be metallic or semiconductor nanoparticles, or molecules which may be conjugated, for example. Appropriate anchors may be attached to, or- incorporated in, the small-scale elements to facilitate, for example, adhesion, electrical contact, or orientation. These anchors may be the end-groups of specific molecules, which may be the small-scale elements themselves, or may be attached to the small-scale elements. Other examples include mechanical or magnetic anchors.
The. structure may be stacked on top of one or more other such structures, to make a number of gaps.
The structures may be nested one inside another, by replacing one or more layers by a set of layers, to make extra contacts to the small-scale elements or to contact different small-scale elements.
The structure may be connected to conventional electronic circuitry on the same substrate, such as a MOSFET.
According to the present invention there is also- provided an electrical device comprising: a small-scale element of size less than 100 nm; and at least one electrode providing electrical contact to the small-scale element, the electrode being formed from a semiconducting material.
The semiconductor material may be highly doped.
There may be two or more electrodes, in which case, one electrode may be metallic instead of semiconducting. In the case of the small-scale element being a molecule, the energy levels, barriers, and binding to the semiconductor may be controlled by the usual methods of synthetic organic chemistry, for example using longer conjugated segments to lower energy levels. . . More than one small-scale element may be assembled in parallel between any pair of electrodes, giving a larger overall device current and/or redundancy. Small-scale elements may be assembled between the electrodes in series, giving a structure with different current-voltage characteristics. If there are two semiconductor electrodes they may be either the same or different types.
The device may be based on injection of electrons from an n-type semiconductor or holes from a p-type semiconductor . Examples of the present invention will now be described with reference to the accompanying drawings, in which:
Figures 1 to 6 are schematic vies of examples of the present invention; Figure 7 is a diagram showing a molecular system configured to operate as a resonant tunnelling diode structure; . >•
Figure 8 is a schematic diagram of a small-scale element; Figure 9 is a scanning electron micrograph of an example of the present invention; and
Figure 10 is a graph showing the current-voltage characteristics for each of the set of selectively etched MOSFET devices manufactured in accordance with the present invention. • ■
Figures 1 and 2 (Figure 2 being a cross-section of Figure 1) show an example of the invention,- • a layered structure consisting of, in tis case, a semiconductor substrate 10 and two ohmic contacts 11, 12. Between these ohmic contacts 11, 12 are two substantially parallel electrodes 14 and a layer of an insulating material 13. The electrodes 14 may be formed of a variety of materials depending on the electrical properties required. Generally they are formed of heavily doped (n-type or p-type) semiconductors such as Si or polysilicon, GaAs or InAs . The two electrodes 14 may be formed of the same material or one may be a different semiconductor or a metallic electrode. Alternatively, they may be two semiconductor electrodes doped differently fro one another.
Between these two electrodes 14 is, in this example, a Iyer of an insulator material 13, typically Si02, SiC, AlGaAs, AlAs, GaN, or a dielectr4ic such as Ta205 or TaN. The layer 13 may be selectively etched, dissolved or otherwise partially removed to allow incorporation of a small-scale element or elements. Selected layers of the structure may also be doped with either n-type or p-type impurities to achieve the desired properties. In one example, a MOSFET-like layer structure (Si substrate coated with Si02 and then polysilicon) provides a suitable set of layers for selective etching of the insulating Si02 layer. This is compatible with standard CMOS processing . to integrate the structure with conventional . electronic components. In another example, a Silicon-On-Insulator (SOI) wafer may be used to provide the layer structure. Such wafers can be made by fusing together the surface oxide layers of two silicon wafers, a standard process called wafer bonding.
Small-scale elements 15 are held inside the gap 20 formed where the insulator layer 13 has been removed, between the two substantially parallel layers 14. The size of this gap can be controlled precisely since it is determined mainly by the thickness of layer 13, which itself may be controlled with a precision comparable to an atomic layer thickness. This can be. done using standard deposition techniques. The term deposition includes precipitation, coating or oxidation or other chemical or physical reaction from a solution, melt or fluid or the accumulation of material from evaporated or sputtered species. The small-scale elements 15 are chosen, in this example, by their electrical, chemical, optical, magnetic or biological properties and are typically of 2-10 nm in diameter. They may be semiconductor nanocrystals of II-VI or III-V semiconductors, for example, CdSe, CdS, InAs, InP; or conjugated molecules which rely on electron delocalisation along one or. more conjugated regions in order to conduct electricity; or complex carbon forms such as C60, carbon nanotubes and other Buckminsterfullerene derivatives. More than one small-scale element 15 may be assembled in parallel to give a larger overall current or redundancy, for example. The layered structure of the present invention can be used, along with appropriate small-scale element (s) to form any one of a number of electronic components such as a logic gate, memory element, diode etc.
If, for some materials, current leakage through the part of the insulating layer 13 which, remains in parallel with the small-scale element (s) is a problem, because of the proximity of the doped electrodes 14, then the electrodes 14 may be selectively doped, for example by ion- implantation, only on either side of the gaps 20 where the insulator 13 has been removed.
Furthermore the electrodes 14 may be modified to include a metallic layer between each electrode 14 and the layer 13 between them. For example, for the structure in Figures 1 and 2, a metal may be incorporated on each silicon surface to form a suicide, before oxidation and wafer bonding. The suicide surface could be designed to have a smaller depletion depth than that at the surface of silicon, with a smaller native oxide thickness, whilst providing a- reliable anchor for the nanoscale components.
The example of figures 1 and- 2 is one example of a device which may have electrodes formed from semiconductor material.. It will be appreciated that other configurations are possible. In this case, examples of suitable nanoscale elements are semiconducting nanocrystals such as CdS or CdSe, or conducting molecules. The spacing of the energy levels in the small-scale element should be larger than the Fermi energy in the electrodes, hence their size in- this example must typically be less than 100 nm. Examples of suitable electrodes are, in this case Si, SiGe, GaAs, I As . The small-scale element is separated from the two •■•- electrodes by tunnel barriers. The tunnel barriers may be formed from insulating material- on the semiconductor electrodes, or engineered into the small-scale element itself, or a combination of both. This allows a hybrid 5 device composed of semiconductors and small-scale elements to behave as a resonant tunnelling diode (RTD) , exhibiting negative differential resistance (NDR) . For an n-type semiconductor, at an appropriate bias, a quantised level in the small-scale element lines up with occupied conduction 0 band states in one of the semiconductor electrodes, and with empty conduction band states in the other electrode, leading to resonant tunnelling through that level. The width in energy of the occupied conduction band states in the semiconductor (the distance from the bottom of the 5 conduction band to some point in the tail of the Fermi distribution) is small compared with that in a metal. The bias may therefore be increased until the state in the small-scale element drops below the conduction band. It is then no longer resonant with states in the electrodes and 0 so tunnelling can no longer take place, thus decreasing the current and giving NDR. This assumes that the state in the small-scale element is separated from the next lowest state by more than the Fermi energy, so that the next state does not come onto resonance before the first has gone off 5 resonance. If this condition is satisfied, it may be possible to observe multiple NDR peaks, as each state passes through the conduction band.
Again the electrodes may be made using the layer techniques described above. 0 In this example, in the case of a small-scale element being a semiconductor nanocrystal, the tunnel barrier may include a ligand on the surface of the nanocrystal, and/or a layer of molecules deposited on the semiconductor surface. The ligand or molecule may be designed with 5 specific end-groups to facilitate binding of the nanocrystal to the semiconductor surface. The ligand or molecule may be designed in order to optimise its tunnelling resistance, for example by exchanging the nanocrystal ligands with ones of different length, or by introducing conjugated units in order to reduce the height of the tunnelling barrier. The quantised energy levels of a nanocrystal may be tuned by changing its size, through the quantum confinement effect, allowing the position of the NDR peak to be controlled and optimised for device applications.
Figure 3 shows one example configuration similar to that in figures 1 and 2, but incorporating an extra metal strip 19 which is deposited, for example by evaporation, on one edge of the structure. The strip 19 has a break 21 formed therein where it passes over the gap 20. The strip 19 provides, in this example, reliable anchoring and/or contacts for the small-scale element. In this embodiment the layers 14 are formed of undoped semiconductor and the gap 20 is formed by selective etching to define the dimensions of a break 21 in the metal strip. In this example it is within the break 21 that the small-scale element 15 is held. This example may be adapted such that the layers 14 also act as ' electrodes insulated from the metal strip 19. This allows as many as four contacts to the small-scale element 15. Appropriate end groups on the small-scale elements could be used to ensure correct orientation.
Figure 4 shows a further example configuration where no selective etching has taken place and the insulating layer 13 between the semiconductor electrodes 14 is simply used to define the dimension across which the small-scale elements 15 will assemble. This is similar to the example shown in Figures 1 and 2 except that there is no selective etching used to form the gap 20 which in this case simply exists because of the properties of the insulating layer 13 and the electrodes 14. Figure 5 shows an example of the present invention, similar to that of Figure 3, with, in this example, a doped polysilicon gate 17 replacing the insulator layer 13 and with the layers 14 being insulating. This example also comprises a metal strip 19 with break 21 within which there is a small-scale element close to the gate 17. The gate 17 can be used to affect the properties of the small-scale elements .
Figure 6 shows a further example which is similar to that in figures 1 and 2, but which introduces an additional conducting gate layer 22 which is electrically isolated from the electrodes 14, but which may be connected to an additional ohmic contact elsewhere. In this case there are three conducting layers 14, 22 in close proximity around the gap. This allows two or three electrical contacts to be made to each small-scale element 15, with one or zero any other contacts respectively being capacitively coupled to it, to act as a gate if required.
In a further example, a gap 20 (or break 21) fabricated as in one of the examples above (Figures 1-6) may be immersed in a fluid. This fluid may contain small- scale elements. The presence, or other properties of the elements or fluid, may be detected or measured when they are in close proximity to the gap 20 or break 21, using the structure. In one example, a voltage may be applied between the electrodes 14 or 19 on either side of " the gap to produce an electric• field within the gap 20. This may polarise a small-scale element 15, such as a linear molecule or metal nanoparticle, so that it bridges the gap
20 and changes the current flowing across the gap. In another example, the voltage may be oscillating at radio
frequencies, creating photons of a specific energy, and the dissipation in the associated electrical circuit will depend on the presence of the small-scale element 15. For example, if the energies are matched, a transition between quantised energy levels in the small-scale element 15 may occur upon absorption of a photon, leading to increased dissipation in the . resonant electrical circuit, which may be detected electrically and used to indicate the type of small-scale element present. In a further example, the set of layers 14, 13 forming the gap structure may be repeated to form a stack of gaps 20, each gap containing one or more small-scale elements. The small-scale elements 15 and layers 14, 13 need- not be the same in each set. Thus a three-dimensional array of devices may be formed, optionally connected to each other or to associated conventional circuit elements (MOSFETs etc) . In one example, the small-scale elements 15 may in fact be small pieces of material containing one- or more devices, such as miniature integrated circuits, which may be fabricated in large quantities and then split up, immersed in a fluid to form, in this example, a colloidal suspension. The width of the gap 20 may be chosen to be slightly greater than the thickness of the small-scale elements 15, so that the small-scale elements 15 may slot into the gaps. Specific molecules or other key-like structures may be incorporated on each -small-scale element 15 to cause them to become attached, with the desired orientation, to matching structures or coatings on some of the layers 14, 13 or 19, when they have slotted into a gap. This may enable the fabrication of three-dimensional integrated circuits, without the need to fabricate each layer sequentially. Figure "7 -is a diagrammatic representation of the structure of one of the small-scale elements 15 that may be employed in the examples of the present invention shown in the previous figures. It is a molecular system with precisely engineered length, operating as, in this example, a resonant tunnelling diode structure.
Figure 8 shows a generic small-scale element 15 to be held in the gap 20 or break 21 of any of the earlier examples of the present invention. This small-scale element 15 may take the form of, for example, a conjugated molecule or CdSe nanocrystal with integral linker molecules.
Figure 9 shows a scanning electron micrograph of an example of the present invention as shown in any of the above schematic representations. The micrograph shows a stack of alternating GaAs and AlAs layers in which the lOnm thick AlAs layers (dark bands) have been selectively etched as described with reference to, for example, Figure 1 above .
Figure 10 is a graph showing the current voltage characteristics for a set of selectively etched moss fit devices. The substrate is of the n+ type, with 14 nm oxide gaps . The dash-dotted curves show the devices before any etching, with the solid lines being after an HF-etch. The dash-dotted lines show the characteristics of the devices after subsequent exposure to nanocrystals in toluene. When nanocrystals are present, the current below 4 volts is increased by up to 3 orders of magnitude, and NDR is visible.
Each device in the set shows similar features as one would expect for a selective etch which gives uniformity between devices.

Claims

1. A method manufacturing a functional device structure, the method comprising the steps of : forming a first layer of material; forming a second layer of material on the first layer; forming a third layer of material on the first layer; forming a third layer of material on the second layer; and treating the layer structure such that in its simplest embodiment a gap is formed between the 1st and 3rd layers,
• the size of the gap being insufficient to have a component therein in use; and placing a small-scale element near the gap.
2. The method of claim 1, wherein layers are formed by techniques used in the manufacture of CMOS devices.
3. The method of claims 1 or 2, wherein the small-scale element is held within the gap.
4. The method of claims 1 to 3 , wherein at least two layers of material are metallic.
5. The method of claim 4 , wherein at least two layers are arranged to act as electrodes which contact the small-scale element .
6. The method of any of claims 1 to 5 wherein the gap is a region where the physical, magnetic, optical, chemical, differ from those on either side of it.
7. The method of any of claims 1 to 7, wherein the small- scale element has a width of less than 20μm.
8. The method of any of claims 1 to 7, wherein the small scale element has a width of less than lμm.
9. The method of any of claims 1 to 7 , wherein the small scale element has a width of less than 200nm.
10. The method of any of claims 1 to 7, wherein the small scale element has a width of 50nm.
11. The method of any of claims 1 to 7, wherein the small scale element has a width of less than 20nm.
12. The method of any of claims 1 to 11, wherein the at least two layers, are separated, by another layer that is formed from insulating material such as silicon dioxide.
13. The method of any of claims 1 to 12, wherein the structure acts as one of a resonant tunnelling diode, a transistor, a logic element or a memory element.
14. The method of any of claims 1 to 13 , wherein the small-scale element is a metallic or semiconductor nanoparticle, or molecules which are conjugated.
15. The method of any of claims 1 to 14, wherein anchors are attached to, or incorporated in, the small-scale element .
16. The method of claim 15, wherein the anchors are the end-groups of specific molecules, the small-scale element itself.
17. A structure formed from at least two layers of material separated by at least another layer, the layers being formed and/or processed such that a gap is formed between the at least two layers; and at least one small-scale element within the gap.
18. The structure of claims 17, wherein the small-scale element is held within the gap.
19. The structure of claims 17 td 18, wherein at least two layers of material are metallic.
20. The structure of claim 19, wherein at' least two layers are arranged to act as electrodes which contact the small- scale element .
21. The structure of any of claims 17 to 20, wherein the gap is a region wherein the physical, magnetic, optical, chemical, differ from those on either side of it.
22. The structure of any of claims 17 to 21, wherein the small-scale element has a width of less than 20μm.
23. The structure of any of claims 17 to 21, wherein -the small-scale element has a width of less than lμ .
24. The structure of any of claims 17 to 21, wherein the small-scale element has a width of less than 20Onm.
25. The method of any of claims 17 to 21, wherein the small-scale element has a width of less than 50nm..
26. The method of any of claims 17 to 21, wherein the small-scale element has a width of less than 20nm.
27. The structure of any. of claims 17 to 26, wherein the at least two layers are separated by another layer that is formed from insulating material such as silicon dioxide.
28. The structure of any of claims 17 to 27, wherein the structure acts as one of a resonant tunnelling diode, a transistor, a logic element or a memory element..
29. The structure of any of claims 17 to 28, wherein the small-scale element is a metallic or semiconductor nanoparticle, or molecules which are conjugated.
30. The structure of any of claims 17 to 29, wherein anchors are attached to, or incorporated in, the small- scale element.
31. The structure of claim 30, wherein the anchors are the end-groups of specific molecules, or the small-scale element itself.
32. A structure according to any of claims 17 to 32, wherein the structure is connected to conventional electronic ci-rcuitry on the same substrate.
33. A device comprising plural structures according to any of claims 17 to 32 are stacked on top of one or more other such structures, to make a number of gaps.
34. A device comprising plural structures according to any of claims 17 to 32 nested one inside another, by replacing one or more layers by a set of layers.
35. An electrical device comprising: a small-scale element of size less than 100 nm; and at least one electrode providing electrical contact to the small-scale element, the electrode being formed from a semiconducting material .
36. The device of claim 35, wherein the semiconductor material is highly doped.
37. The device of claim 35 or claim 36, wherein there are two or more electrodes.
38. The device of claim 37, wherein one electrode is metallic .
PCT/GB2001/004793 2000-10-30 2001-10-30 Small-scale structures WO2002037571A1 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1547970A2 (en) * 2003-12-23 2005-06-29 Hewlett-Packard Development Company, L.P. Fabrication of Nano-object array
EP1630127A1 (en) * 2004-08-31 2006-03-01 STMicroelectronics S.r.l. Method for realising a hosting structure of nanometric elements
US7456508B2 (en) 2004-08-31 2008-11-25 Stmicroelectronics S.R.L. Hosting structure of nanometric elements and corresponding manufacturing method
US7834344B2 (en) 2004-08-31 2010-11-16 Stmicroelectronics S.R.L. Nanometric structure and corresponding manufacturing method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619476A (en) * 1994-10-21 1997-04-08 The Board Of Trustees Of The Leland Stanford Jr. Univ. Electrostatic ultrasonic transducer
WO1997046267A1 (en) * 1996-06-03 1997-12-11 Gore Enterprise Holdings, Inc. Materials and methods for the immobilization of bioactive species onto biodegradable polymers
US5725729A (en) * 1994-09-26 1998-03-10 The Charles Stark Draper Laboratory, Inc. Process for micromechanical fabrication

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5725729A (en) * 1994-09-26 1998-03-10 The Charles Stark Draper Laboratory, Inc. Process for micromechanical fabrication
US5619476A (en) * 1994-10-21 1997-04-08 The Board Of Trustees Of The Leland Stanford Jr. Univ. Electrostatic ultrasonic transducer
WO1997046267A1 (en) * 1996-06-03 1997-12-11 Gore Enterprise Holdings, Inc. Materials and methods for the immobilization of bioactive species onto biodegradable polymers

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MOLVA E ET AL: "MICROGUN-PUMPED SEMICONDUCTOR LASER", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 62, no. 8, 22 February 1993 (1993-02-22), pages 796 - 798, XP000338604, ISSN: 0003-6951 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1547970A2 (en) * 2003-12-23 2005-06-29 Hewlett-Packard Development Company, L.P. Fabrication of Nano-object array
EP1547970A3 (en) * 2003-12-23 2005-11-16 Hewlett-Packard Development Company, L.P. Fabrication of Nano-object array
EP1630127A1 (en) * 2004-08-31 2006-03-01 STMicroelectronics S.r.l. Method for realising a hosting structure of nanometric elements
US7432120B2 (en) 2004-08-31 2008-10-07 Stmicroelectronics S.R.L. Method for realizing a hosting structure of nanometric elements
US7456508B2 (en) 2004-08-31 2008-11-25 Stmicroelectronics S.R.L. Hosting structure of nanometric elements and corresponding manufacturing method
US7834344B2 (en) 2004-08-31 2010-11-16 Stmicroelectronics S.R.L. Nanometric structure and corresponding manufacturing method
US7952173B2 (en) 2004-08-31 2011-05-31 Stmicroelectronics S.R.L. Nanometric device with a hosting structure of nanometric elements

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