WO2002033642A1

WO2002033642A1 - Circuit configuration for producing a ratio and for producing an output signal corresponding to said ratio

Info

Publication number: WO2002033642A1
Application number: PCT/DE2000/003650
Authority: WO
Inventors: Tobias Tyroller
Original assignee: Siemens Aktiengesellschaft
Priority date: 2000-10-17
Filing date: 2000-10-17
Publication date: 2002-04-25

Abstract

The invention relates to a circuit configuration that comprises a first generator (1) controlled by a first input signal (U1) for producing a first clock signal (T1), a second generator (2) controlled by a second input signal (U2) for producing a second clock signal (T2), and a counter (3) mounted downstream of the first generator (1) that can be reset via a counter reset signal and that emits a binary word corresponding to its counter reading. A register (4) is disposed downstream of the counter (3) and adopts the binary word in response to a register load signal and provides the digital output signal (R). The counter reset signal and the register load signal are produced from the second clock signal (T2) of the generator (2) that is connected to the counter (3) and the register (4).

Description

description

Circuit arrangement for ratio formation and for generating an output signal corresponding to the ratio

The invention relates to a circuit arrangement for forming the ratio of two analog input signals and for generating a digital output signal corresponding to the ratio of the two input signals.

Circuit arrangements of this type are implemented, for example, by means of special analog-digital converters and are known, for example, from U. Tietze, Ch. Schenk, Semiconductor Circuit Technology, 9th edition, 1990, pages 784 to 790. This also as an analog-digital converter according to the single slope

Methods or arrangements designated by the dual slope method generally have a counter, an oscillator as a timer, at least one comparator and an integrator or instead a sawtooth generator. In both cases, however, an input signal is set in relation to a fixed reference voltage.

Particularly in applications in automotive technology, such as impact detection, however, it is necessary to relate two changing input signals in relation. For this reason, the ratio formation on the analog side, for example by logarithmization, subtraction and subsequent delogarithmization, or by digital circuits requiring some computation, has generally been implemented so far. In this case, those which only have a variable input signal were used as analog-digital converters. In both cases, however, the implementation effort is relatively high. The object of the invention is therefore to provide a circuit arrangement of the type mentioned at the outset in which less effort is required.

The object is achieved by a circuit arrangement according to claim 1. Refinements and developments of the inventive concept are the subject of subclaims.

It is an advantage of the invention that the use of a special analog-digital converter principle that allows the ratio formation of two variable input signals does not require any additional effort for the ratio formation. Instead of forming a ratio either before the analog-to-digital converter or after the analog-to-digital converter - as before - the ratio is now created by the analog-to-digital converter itself. Thus, two analog input signals are set in a simple manner in relation to one another, the digital output value being proportional to the ratio of the two input signals.

This is achieved in a circuit arrangement for forming the ratio of two analog input signals and for generating a digital output signal corresponding to the ratio of the two input signals by a first generator controlled by the first of the two input signals for generating a first clock signal with a first clock frequency dependent on the first input signal and one by the second of the two input signals controlled second generator for generating a second clock signal with a second clock frequency dependent on the second input signal. A counter connected to the first generator emits a binary word corresponding to its counter reading and can be reset by means of a counter reset signal. When a register load signal occurs, a register connected to the counter takes over the binary word and sets the digital output ready signal, the counter reset signal and the register load signal being generated from the second clock signal of the second generator connected to the counter and register.

The second generator is preferably followed by a frequency divider with a specific divider factor and / or the register is a subtractor (6), which subtracts the digital output signal (R) to divide the divider factor (x) from the output value of the register (4).

Furthermore, the two generators can have the same transmission ratios of the respective clock frequency to the respective input signal. This is advantageous because identical generators are easier to use, i. H. can be produced with a low tolerance to one another, this relative tolerance essentially determining the overall tolerance of the circuit arrangement.

Finally, the counter reset signal and the register load signal are generated in succession in such a way that the meter reading is first transferred to the register and then the counter is reset.

The invention is explained in more detail below with reference to the exemplary embodiments shown in the figures of the drawing. It shows :

FIG. 1 shows a first preferred embodiment of a circuit arrangement according to the invention,

Figure 2 shows a second preferred embodiment of a circuit arrangement according to the invention and

FIG. 3 shows a third preferred embodiment of a circuit arrangement according to the invention. In the embodiment shown in Figure 1, an input signal - an input voltage Uτ_ - a controllable

Generator - a voltage controlled oscillator (VCO) 1 - supplied, the output of which is connected to the counter input of a counter 3. The reset input of counter 3 is connected to the output of a generator controlled by a further input signal - an input voltage U2 - a voltage-controlled oscillator (VCO) 2. The counter 3 is in turn followed by a register 4 which, driven by the voltage-controlled oscillator 2, takes over the counter readings of the counter 3 and outputs it as a digital output signal R. The circuit arrangement shown in FIG. 1 is designed for an input voltage U _] _ which is substantially greater than the input voltage U2. Depending on the input voltages Uι_, U2, the voltage-controlled oscillators 1, 2 generate clock signals Tτ_, T2, the clock frequency f ^, f2 of which is, for example, directly proportional to the respective input signal. Furthermore, both voltage-controlled oscillators 1, 2 are identical, so that:

(1) f _x = kU _{1 #}

(2) f ₂ = kU ₂ .

Here, k is a proportionality constant that is identical for both voltage-controlled oscillators 1, 2.

The counter 3 counts the clocks of the clock signal T _x in the time interval between two clocks of the clock signal T ₂ . The digital Output signal R thus behaves as follows at the time intervals ^Δt l and ^Δt 2:

(3) R = Δt ₂ / Δt ₁ = fχ / f ₂ = kU! / KU ₂ = U; ι_ / U ₂

The embodiment according to FIG. 2 emerges from the embodiment shown in FIG. 1 in that the second controlled oscillator 2 is followed by a frequency divider 5 which has a division factor x and consequently divides the frequency f ₂ by division factor x. With appropriate

Values for the divider factor x can be achieved such that suitable ranges of the input voltages Uτ_, U ₂ with identical voltage-controlled oscillators 1, 2 come to be in approximately the same order of magnitude (Uι «U ₂ ) • For the digital output signal R this results:

(4) R = f ₁ / (f ₂ / x) = x- (U3./U2)

The counter 3 thus counts the clocks of the clock signal Tι_ in the time interval between two clocks of the clock signal T2 divided in frequency by the divider factor x.

The embodiment shown in FIG. 3 is evident from the embodiment shown in FIG. 2 in that the register 4 is followed by a digital subtractor 7.

This subtracts the division factor x from the counter reading stored in register 4. The digital output signal R is thus calculated as follows:

(5) R = (f ₁ / (f ₂ / x)) - x = (x / U ₂ ) (Uχ-U ₂ )

For the purpose of a safe transfer of the meter reading into the register 6 it can be provided that the transfer is carried out first and then the reset is delayed of the counter 3. This can be done, for example, by means of a delay element 7 connected upstream in the reset input of the counter 3 (as shown in FIG. 3).

As can be seen from the exemplary embodiments, the ratio formation of two variable input signals and an analog-digital conversion in one are achieved according to the invention, so that no additional effort is necessary. Instead of forming a ratio either before the analog-to-digital converter or after the analog-to-digital converter - as before - the relationship is now formed in the analog-to-digital conversion.

Claims

claims

1. Circuit arrangement for forming the ratio of two analog input signals (Ui _. U ₂₎ and for generating a digital output signal (R) corresponding to the ratio of the two input signals (Uχ _/ U ₂ ) with a first generator controlled by the first of the two input signals (Uτ_ U ₂₎ (1) for generating a first clock signal (T] _) with a first clock frequency (f _] _) dependent on the first input signal (U _] _), a second generator (2. ₂₎ controlled by the second of the two input signals (Uτ_ U ₂₎ ) for generating a second clock signal (T ₂₎ with one of the second input signal (U ₂₎ dependent second clock frequency (f _2), a first generator (1) downstream counter (3) which can be reset via a payer jerk set signal and a outputs a binary word corresponding to its counter reading, a register (4) connected downstream of the counter (3), which takes over the binary word and the digital output when a register load signal occurs provides signal (R), the number reset signal and the register load signal being generated from the second clock signal (T) of the second generator (2) connected to the counter (3) and register (4).

2. Circuit arrangement according to claim 1, in which the second generator (2) is followed by a frequency divider (5) with a specific divider factor (x).

3. Circuit arrangement according to claim 1 or 2, in which the register (4) is followed by a subtractor (6) which subtracts the divisor factor (x) from the output value of the register (4) to give the digital output signal (R).

4. Circuit arrangement according to claim 1, 2 or 3, wherein the two generators (1, 2) have the same transmission ratios of the respective clock frequency () to the respective input signal.

5. Circuit arrangement according to claim 1, 2, 3 or 4, in which • the number reset signal is generated according to the register load signal.