WO2002029887A3 - One-step etch processes for dual damascene metallization - Google Patents
One-step etch processes for dual damascene metallization Download PDFInfo
- Publication number
- WO2002029887A3 WO2002029887A3 PCT/US2001/026998 US0126998W WO0229887A3 WO 2002029887 A3 WO2002029887 A3 WO 2002029887A3 US 0126998 W US0126998 W US 0126998W WO 0229887 A3 WO0229887 A3 WO 0229887A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- resist layer
- dual damascene
- dielectric layer
- etch processes
- layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method for forming a dual damascene structure, employs the steps of forming a dielectric layer (14), patterning a first resist layer (16) on the dielectric layer to form a via pattern (26) and patterning a second resist layer (28) to form a line pattern (38) in communication with the via pattern formed on the first resist layer wherein the first resist layer includes exposed portions adjacent to the via pattern. The first resist layer, the second resist layer and the dielectric layer are etched such that the dielectric layer has a via (40) formed therein which gets deeper during the etching process. The dielectric layer has a trench (42) formed therein in communication with the via which gets deeper after the exposed portions of the first resist layer are consumed by the etching process.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US67582700A | 2000-09-29 | 2000-09-29 | |
US09/675,827 | 2000-09-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002029887A2 WO2002029887A2 (en) | 2002-04-11 |
WO2002029887A3 true WO2002029887A3 (en) | 2003-02-06 |
Family
ID=24712121
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2001/026998 WO2002029887A2 (en) | 2000-09-29 | 2001-08-30 | One-step etch processes for dual damascene metallization |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2002029887A2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10233209A1 (en) * | 2002-07-22 | 2004-02-05 | Infineon Technologies Ag | Irradiating resist during the production of integrated switching arrangement comprises forming radiation-sensitive resist layer arrangement after producing layer to be structured and irradiating the resist layer arrangement |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5173442A (en) * | 1990-07-23 | 1992-12-22 | Microelectronics And Computer Technology Corporation | Methods of forming channels and vias in insulating layers |
US5369061A (en) * | 1992-06-16 | 1994-11-29 | Sony Corporation | Method of producing semiconductor device using a hydrogen-enriched layer |
-
2001
- 2001-08-30 WO PCT/US2001/026998 patent/WO2002029887A2/en active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5173442A (en) * | 1990-07-23 | 1992-12-22 | Microelectronics And Computer Technology Corporation | Methods of forming channels and vias in insulating layers |
US5369061A (en) * | 1992-06-16 | 1994-11-29 | Sony Corporation | Method of producing semiconductor device using a hydrogen-enriched layer |
Non-Patent Citations (2)
Title |
---|
"METHOD TO CONTROL DEPTH OF ETCHING", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 35, no. 3, 1 August 1992 (1992-08-01), pages 29 - 30, XP000326155, ISSN: 0018-8689 * |
"METHOD TO INCORPORATE THREE SETS OF PATTERN INFORMATION IN TWO PHOTO-MASKING STEPS", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 32, no. 8A, January 1990 (1990-01-01), pages 218 - 219, XP000082778, ISSN: 0018-8689 * |
Also Published As
Publication number | Publication date |
---|---|
WO2002029887A2 (en) | 2002-04-11 |
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