WO2002029587A2 - Distributing data to multiple destinations within an asynchronous circuit - Google Patents
Distributing data to multiple destinations within an asynchronous circuit Download PDFInfo
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- WO2002029587A2 WO2002029587A2 PCT/US2001/027212 US0127212W WO0229587A2 WO 2002029587 A2 WO2002029587 A2 WO 2002029587A2 US 0127212 W US0127212 W US 0127212W WO 0229587 A2 WO0229587 A2 WO 0229587A2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/23—Pc programming
- G05B2219/23289—State logic control, finite state, tasks, machine, fsm
Definitions
- the present invention relates to the design of digital circuits. More specifically, the present invention relates to a method and an apparatus for asynchronously distributing data to multiple destinations within a digital circuit.
- Finite state machines are familiar to every designer of computer equipment. They are easy to describe and generally easy to implement. Such a machine can be in any one of a number of "states". Most implementations use a set of "state flip-flops" to hold the present state of the finite state machine.
- each state there are a set of conditions that will cause the finite state machine to change from that state to some other state.
- the conditions examined in each state may be unique to that state or shared with other states.
- the state to which the device changes depends on the state it is in, the conditions examined in that state, and which conditions are TRUE.
- a simple up-down counter is a finite state machine. Its states are the finite number of count values that it can hold. The conditions examined in each state are "count up” and "count down". The up-down counter advances from its present state to the next higher count value when it gets the "count up” condition and advances to the next lower count value when it finds the "count down” condition. Depending on the design it may have a highest state in which it can only count down or a lowest state in which it can only count up or both.
- Finite state machines typically use externally-clocked flip-flops to hold their state. Logic elements examine the conditions pertinent to the present state, and upon the arrival of each external clock pulse, set or clear selected clocked flip-flops to establish the next state.
- the design of such externally-clocked finite state machines is relatively easy, because all flip-flops change, if at all, only in response to the same external clock signal. Thus, for example, it is acceptable to change the state of several flip-flops at once, for example as happens in a binary counter when the "carry" passes through several stages, returning them all to the "zero" state. Were the flip-flops of the counter not clocked externally, the process of changing several flip-flops might cause the counter for a short interval to assume one or more intermediate states outside the proper binary sequence.
- ripple counters some simple finite state machines, including binary counters are often built without an external clock for their flip-flops.
- the state flip-flops that hold the count each act independently.
- the flip-flop holding each bit of the count changes its state in response to changes from "one" to "zero” in the flip-flop that holds the bit representing half its value.
- ripple counters when a six bit ripple counter changes from 001111 to 010000, it will momentarily assume the states 001110, 001100, 001000, 010000 in rapid succession even though they are out of sequence. It is well known to those familiar with ripple counters that one must exercise care in their application because such FALSE states appear in their flip-flops, albeit for very short intervals of time.
- finite state machines For finite state machines of any complexity, the simplicity of externally-clocked flip-flops is much preferred.
- One aspect of all finite state machines involves the mapping of the allowed states of the machine onto the possible states of the flip-flops that retain the state. Such a mapping is called the "state encoding" used for the finite state machine because it defines the meaning of each possible state of the flip-flops. The encoding may also rule out certain combinations of flip-flop states as outside the range permitted for that finite state machine.
- finite state machines use a "one-out-of-N" encoding in which only one state flip-flop is “set” for each state. This encoding rules out the state with no state flip-flops set as well as all states with more than one state flip-flop set. With the one-out-of-N encoding, each change of state sets the state flip-flop associated with the new state and clears the state flip-flop associated with the old state.
- the one-out-of-N state encoding though simple, is impractical for finite state machines with large numbers of states.
- a second simple state encoding is a binary state encoding.
- each state is defined by a binary combination of state flip-flops that are set and that are clear.
- the binary encoding permits all combinations.
- This encoding is suitable for some finite state machines such as the binary counter already mentioned. It has the problem, however, that some state changes may require simultaneously setting many state flip-flops and clearing many others. The need to change many state flip-flops simultaneously renders binary encoding unsuitable for some applications.
- Designers have learned to choose encodings suitable to the needs of each particular application. Finite state machines use complex logic elements to control the set and clear functions of individual flip-flops. These conditions cause "transitions" in the state of the finite state machine.
- CMOS complementary metal oxide semiconductor
- CMOS circuits electrical capacitance can serve a state-holding function that previously had to be done with logic elements formed into flip-flops.
- DRAM dynamic random access memory
- the electrical charge stored on a tiny capacitor serves to record each bit of information.
- the charge on any wire can also serve to store information.
- Dynamic circuits depend for their operation on the retention of information in electrical charges on wires. Dynamic circuits are possible in CMOS because the control input of a CMOS transistor, the "gate" of the transistor, operates on charge rather than current. An electric charge placed on the gate of a transistor will continue to condition the behavior of the transistor for a relatively long period until the charge gradually "leaks" off. Note that a fundamental building block for a dynamic circuit is a distributor that distributes data from a single source to a number of destinations.
- the present invention uses such dynamic charge storage as the basis for a variety of finite state machines. It notes that charge placed on a CMOS conductor that connects to a number of transistor gates will condition those gates, and continue to do so for a relatively long time. Instead of storing the state of a finite state machine in a collection of state flip-flops, the present invention stores the state of a finite state machine on a set of state conductors, using the capacitive charge on those conductors to hold the state.
- a state conductor can be distributed geometrically over a wide area. It can be extended to whatever length is desired, turn corners or branch as needed, and can connect together as many components as desired.
- To change the state of a state flip-flop requires bringing the output of the transition logic to the state flip-flop.
- a state transition wire connects from the state transition logic to the state flip-flop.
- to change the charge on a state conductor requires only that the state conductor be driven to the new state from anywhere along its length. The state conductor will automatically communicate the new state throughout its length.
- CMOS technology a state conductor will retain its charge state for a relatively long time. If the state must be retained indefinitely, a small “keeper” can be attached to the wire. Such a keeper gently drives the wire towards its most positive state if it is already positive and gently drives it towards its most negative state if it is already negative.
- the keeper is sufficiently weak that it is unable to resist the intentional state changes imposed by operation of the finite state machine, but just strong enough to counteract the tiny leakage currents and the effects of electrical "noise” that might otherwise disturb the charge stored on the conductor and thus improperly change its state.
- N- type and P-type drive their outputs in different directions.
- One or more N-type drive transistors connected anywhere along the length of a state conductor can drive it to the "LO" state, and likewise one or more P-type drive transistors connected anywhere along the state conductor can drive it to the "HI” state. Because the drains of these drive transistors each contribute capacitance to the conductor, attaching them to the conductor actually increases the ability of the conductor to store charge, thus enhancing its ability to retain state!
- N-type or P-type drive transistors can be attached to the state conductor to condition it properly.
- the conductor goes to the LO state in response to any N-type drive transistor anywhere along its length.
- the conductor goes to the HI state in response to any P-type drive transistor anywhere along its length.
- State conductors will often accommodate more than one N-type and more than one P-type drive transistor.
- N-type drive transistors and the P-type drive transistors for a single state conductor must never act simultaneously. Simultaneous drive by both types of drive transistors would represent a logical conflict, some attempting to make the state conductor HI and some attempting to make it LO. Were such conflict to occur, two bad things would happen. First, excess current would flow from the power supply to ground, consuming energy unnecessarily. Second, the charge left on the conductor might be uncertain, it not having been certain which should prevail, the N-type drive transistors, yielding the LO state, or the P-type drive transistors, yielding the HI state.
- Each state transition will occur when one or more N-type drive transistors connected to a particular state conductor act or one or more P-type drive transistors connected to that state conductor act.
- N-type drive transistors connected to a particular state conductor act or one or more P-type drive transistors connected to that state conductor act.
- P-type drive transistors connected to that state conductor act.
- several state conductors might change state at the same time, some driven by N-type drive transistors and others by P-type drive transistors, as required by the design.
- CMOS circuits a principle consumption of energy is to charge and discharge the capacitance of wires.
- the amount of energy consumed for an action, charging or discharging a wire involves the capacitance of the wire which depends, of course, on its length.
- the power consumed depends on how many charge and discharge cycles happen per unit of time and upon the length of the wires thus charged or discharged.
- the wires that carry the external clock connect to each of the state flip-flops. These clock wires charge and discharge each clock cycle, whether or not the state of the machine changes.
- the transition wires that deliver transition commands to the flip-flops extend from the sources of the conditions to the state flip-flop. The transition wires charge and discharge in response to the transition logic. Each transition wire assumes one state before its transition can occur and returns to a neutral state after its transition, two changes per transition.
- the wires that report the state of the state flip-flop must extend from the state flip-flop to whatever circuits require knowledge of its state. These state flip-flop output wires change once per state transition.
- CMOS finite state machine In a CMOS finite state machine according to the present invention, however, the situation is quite different.
- the present invention in contrast to systems using state flip-flops, the present invention extends the state conductor to the state transition logic rather than having a separate wire connecting the state transition logic to the state flip-flop.
- the length of wire required to extend the state conductor to the state transition logic is never longer that the transition wire would have been, and may be much shorter because it need run only from the transition logic to the nearest part of the existing state conductor. Moreover, this wire charges or discharges only once for each state transition rather than twice, thus saving energy.
- the present invention uses only one wire, the state conductor, for both purposes. Drive transistors connected anywhere along the length of the state conductor change its state as needed. This reduction in complexity reduces both the total amount of wire required to implement the finite state machine and the energy consumed as it operates.
- One embodiment of the present invention provides a system that asynchronously distributes data to a plurality of destinations within a digital circuit.
- the system monitors asynchronous control signals associated with the destinations, wherein a given asynchronous control signal indicates that a given destination is free to receive the data item.
- the system forwards the data item to the destination asynchronously without waiting for a system clock signal, and also changes an asynchronous control signal associated with the destination to indicate that the destination is not free to receive a subsequent data item.
- the system uses a keeper circuit coupled to each asynchronous control signal to hold the asynchronous control signals at a stable value.
- the system changes the asynchronous control signal by generating a pulse to change the asynchronous control signal. (This pulse can be generated through a cycle of logical inversions.)
- the system additionally updates the asynchronous control signals so that the plurality of destinations receive successive data items in round-robin order.
- the system additionally updates the asynchronous control signals so that the data item is communicated to a destination specified by an address associated with the data item.
- the system communicates the data item by passing the data item through a pipeline, wherein each stage in the pipeline is coupled with a specific destination.
- the system updates the asynchronous control signals so that the two destinations receive successive data items in alternating order.
- the system forwards the data item from the given destination to a downstream location.
- the system also changes an asynchronous control signal associated with the given destination to indicate that the given destination is again free to receive a subsequent data item.
- the plurality of asynchronous control signals propagate between a plurality of pulse circuits that operate a plurality of pass gates, which route the data item to the destinations.
- each pulse circuit includes a first input and a second input that receive asynchronous control signals, and each pulse circuit is configured to fire a pulse to open an associated pass gate when the first input and the second input are both asserted.
- the plurality of pass gates includes, a first pass gate that is configured to receive the data item, and a plurality of destination pass gates that are coupled with the plurality of destinations.
- the plurality of pulse circuits includes, a first pulse circuit that is configured to control the first pass gate, and a plurality of destination pulse circuits that are configured to control the plurality of destination pass gates.
- the plurality of asynchronous control signals are coupled between the plurality of pulse circuits so as to control the plurality of pass gates, and to thereby control distribution of the data item to the plurality of destinations.
- FIG. 1 illustrates an asynchronous circuit that holds state information on a conductor in accordance with an embodiment of the present invention.
- FIG. 2 illustrates an asynchronous circuit that holds state information on a conductor and includes a self-resetting NAND gate in accordance with another embodiment of the present invention.
- FIG. 3 illustrates an asynchronous circuit that controls two conductors in accordance with an embodiment of the present invention.
- FIG. 4A illustrates another asynchronous circuit that holds state information on a conductor in accordance with an embodiment of the present invention.
- FIG. 4B presents another representation of the circuit illustrated in FIG. 4A in accordance with an embodiment of the present invention.
- FIG. 5 illustrates an asynchronous circuit that controls a short first-in-first-out
- FIFO circuit that branches in accordance with an embodiment of the present invention.
- FIG. 6 illustrates several symbols and their corresponding circuits in accordance with an embodiment of the present invention.
- FIG. 7A illustrates an alternator circuit in accordance with an embodiment of the present invention.
- FIG. 7B illustrates registers associated with the alternator circuit in FIG. 7A in accordance with an embodiment of the present invention.
- FIG. 8 illustrates a round robin circuit in accordance with an embodiment of the present invention.
- FIG. 9 illustrates a data conditional circuit using a NAND gate form in accordance with an embodiment of the present invention.
- FIG. 10 illustrates a data conditional circuit using a self-resetting form in accordance with an embodiment of the present invention.
- FIG. 11 illustrates a demand merge circuit in accordance with an embodiment of the present invention.
- FIG. 12 illustrates a low is full form of a FIFO circuit in accordance with an embodiment of the present invention.
- FIG. 13 presents a timing diagram of input-limited operation of the FIFO circuit from FIG. 12 in accordance with an embodiment of the present invention.
- FIG. 14 presents a timing diagram of output- limited operation of the FIFO circuit from FIG. 12 in accordance with an embodiment of the present invention.
- FIG. 15 presents a timing diagram of maximum throughout operation of the FIFO circuit from FIG. 12 in accordance with an embodiment of the present invention.
- FIG. 16 illustrates a high is full form of a FIFO circuit in accordance with an embodiment of the present invention.
- FIG. 17 presents a timing diagram of input- limited operation of the FIFO circuit from FIG. 16 in accordance with an embodiment of the present invention.
- FIG. 18 presents a timing diagram of output-limited operation of the FIFO circuit from FIG. 16 in accordance with an embodiment of the present invention.
- FIG. 19 presents a timing diagram of maximum throughput operation of the
- FIG. 16 FIFO circuit from FIG. 16 in accordance with an embodiment of the present invention.
- FIG. 20 illustrates a conditional branch circuit in accordance with an embodiment of the present invention.
- FIG. 21 illustrates a conditional merge circuit in accordance with an embodiment of the present invention.
- FIG. 22 illustrates an address-based distributor circuit in accordance with an embodiment of the present invention.
- FIG. 23 A illustrates a pulse circuit in accordance with an embodiment of the present invention.
- FIG. 23B is a schematic diagram of a pulse circuit in accordance with an embodiment of the present invention.
- FIG. 24A illustrates a pulse circuit that supports conditional branching in accordance with an embodiment of the present invention.
- FIG. 24B is a schematic diagram of a pulse circuit that supports conditional branching in accordance with an embodiment of the present invention.
- the present invention can involve four parts: one or more state conductors, at least two drive transistors connected to each state conductor, one or more condition inputs, and one or more pulse-generating circuits.
- a pulse generating circuit is associated with each state transition of the finite state machine. Each pulse circuit may use as its inputs any of the condition inputs and any of the state conductors. Each pulse circuit generates a pulse when it detects a certain set of values on its inputs. The pulse thus generated activates N-type or P-type drive transistors to drive one or more of the state conductors as required for the particular design, thus causing the desired change in state.
- any or all of the state conductors may have a "keeper" attached to prevent slow discharge of the electric charge placed on it by the drive transistors activated by the pulse circuits.
- Said keeper must be weak enough to avoid interfering with the actions of the drive transistors.
- a keeper circuit can be implemented as a weak driver in the form of two inverters connected together in series with an input and an output coupled to the same state conductor.
- the voltage level that is present on the conductor is reinforced by the driver circuit.
- the strength of the driver is limited so that a stronger drive circuit can easily change the voltage level on the conductor in spite of the keeper circuit.
- the pulse circuits used in the present invention activate the drive transistors long enough to change reliably the charge on the state conductors and thus to change the state of the finite state machine. However, the drive action ceases promptly enough to avoid interfering with opposing drive initiated by some other pulse circuit.
- the timing of the pulse circuits in the present invention is important.
- Various circuit forms are possible, some faster than others. In general timing must be more carefully considered for faster circuits than in slower ones.
- the present invention uses pulse-generating circuits to cause state transitions, it is free of an external clock signal. This freedom makes it applicable to a variety of self-timed or asynchronous circuits such as pipelines and First In First Out register circuits called FIFOs. A variety of such circuits are illustrated in the disclosure that follows.
- this external clock signal can be treated as one of the condition inputs to the pulse circuits. Including an external clock signal as a condition input can ensure that the state conductors change state only at times specified by the external clock signal.
- the pulse generating circuit consists primarily of a logical AND function.
- This logical AND function combines the conditions necessary for the state changing event that it represents.
- the logical AND function may be implemented in any of a number of forms, including using NAND gates or NOR gates, as will be explained later.
- the pulse generating circuit contains a number of inverters serving a number of functions. First, the inverters place input conditions into the correct logical sense relative to the logical AND function. Second, the inverters place the output of the logical AND function in the correct logical sense to activate the N-type or P-type drive transistors. Third, the inverters provide short delays to ensure correct timing of the pulse. And fourth, the inverters provide electrical amplification to reduce the input current requirement of certain inputs.
- One aspect of the present invention involves careful choice of the size of the transistors in these inverters, the size of the transistors in the logical AND function, and the size of the drive transistors connected to the state conductors.
- the onset of the pulse occurs when the last input to the AND function becomes TRUE, causing the output of the AND function to change.
- this change initiates the state transition because it activates one or more of the state conductor drive transistors, changing the state of the finite state machine as required.
- the AND logic output may activate the drive transistors directly, or indirectly through one or more inverters.
- An important aspect of the present invention is that one or more of the state conductors changed by a pulse-generating circuit are themselves inputs to the AND function in that circuit. Shortly after the pulse generating circuit initiates the pulse, the selected drive transistor changes the state of the state conductor. This, in turn, renders at least one input to the AND function FALSE, terminating the pulse. Thus, completion of the state transition initiated by the pulse generating circuit serves to terminate the pulse that initiated the state transition. It is important to control carefully the time between onset and termination of the pulse. The pulse must last long enough to change reliably the state of all the state conductors that it drives.
- the pulse must terminate promptly enough to avoid interfering with the actions of such other pulse circuits.
- the duration of the pulse is set by the number of inverters associated with the logical AND function and the width of the transistors in the circuit.
- the loop may also include extra inverters before or after the AND function as required.
- This logical feedback loop has a characteristic response time that depends on the number and width of the transistors involved in the loop. Groups of pulse generating circuits used for the various transitions of a finite state machine will work best together if their characteristic action times are chosen to avoid mutual interference. Design of circuits built according to the present invention involves choosing the proper number of inverters to include in each such cycle of logical inversions and the width of the transistors throughout the loop. Given a suitable choice of inverters and transistor sizes, finite state machines built using the present invention can operate at very high speeds.
- a major advantage of the present invention is its ability to combine the actions of several pulse circuits on a single state conductor.
- the state conductor can extend to the locations most convenient for the pulse circuits that drive it. Near each pulse circuit a suitable N-type or P-type drive transistor drives the state conductor to its new state. Thus, the pulse circuit's output signal need extend only a short distance from the pulse circuit to the drive transistor.
- any of several pulse circuits is equally able to change the state of the state conductor via its own drive transistor.
- the pulse control logic itself ensures that the drive action for one state change terminates before the drive action for a subsequent state change begins.
- the state change logic must avoid initiation of two conflicting state transitions at the same time.
- FIG. 1 This specification presents a number of embodiments for the AND function in accordance with the present invention.
- One form, shown in FIG. 1, uses a series stack of two or more N-type drive transistors connected directly to the state conductor. The AND function and the drive transistor operation are combined. Of course P-type drive transistors might also be used. When all such transistors conduct, they change the charge of the state conductor to make the chosen state transition.
- the state conductor itself serves as one input to the logical AND function, via inverters 104 and 106. Inverters 104 and 106 provide a short delay that, together with the time taken to charge or discharge the state conductor, sets the duration of the action pulse.
- the logic feedback loop comprised of inverters 104 and 106 and N-type drive transistor 108 involves three logical inversions, two in inverters 104 and 106, and one in N-type drive transistor 108 that is part of the stack of drive transistors. Of course, other numbers of logical inversions are possible. Note that the order of transistors 108 and 110 in FIG. 1 does not matter.
- the source of N-type transistor 108 can be coupled to ground
- the drain of N-type transistor 110 can be coupled to state conductor 102
- the source of N-type transistor 110 can be coupled to the drain of N-type transistor 108.
- state conditions signal 112 is coupled to the gate of a single N- type transistor 110.
- N-type transistors can be coupled in series to perform an AND operation for a number of separate state conditions.
- FIG. 2 illustrates this form with two series N-type transistors 212 and 214 but there might be more series transistors involved or P-type transistors might be used.
- the node 211 to which they connect changes to the LO state.
- This node is also connected to the gate of the drive transistor 216, which drives state conductor 218 towards the HI state.
- a separate mechanism involving inverters 204 and 206 and the P-type reset transistor 202 form a "reset loop" that returns node 211 to the HI state, terminating the pulse and shutting off the drive transistor 216. In this circuit, the timing of the reset loop must be carefully controlled because it sets the duration of the action pulse.
- the source of N-type transistor 212 can be coupled to ground, the drain of N-type transistor 214 can be coupled to node 211, and the source of N-type transistor 214 can be coupled to the drain of N-type transistor 212.
- One advantage of this self-resetting circuit is that a single such NAND function can serve several drive transistors. This permits a single pulse-generating circuit to change the state of several state conductors. At least one of the state conductors so driven is connected to one of the transistors in the series stack that does the AND logic function so that the desired action, namely changing the state of the state conductor, turns off the series stack. This turn off action prevents the series stack from interfering with the reset action of the reset loop and the reset transistor 202.
- a third form uses the more common form of NAND circuit often used in other CMOS logic circuits. This form is illustrated in FIG. 3.
- the NAND circuit consists of the series N-type transistors 312 and 314 and the parallel P-type transistors 306 and 308.
- the N-type and P-type can be interchanged if desired, creating what is commonly known as a NOR logic gate.
- the series transistors in the NAND gate initiate the pulse. When all of them conduct, the internal node 311 of the circuit becomes LO which, in turn, drives one or more state conductors 302 and 320.
- State conductor 302 is driven HI by drive transistor 304; state conductor 320 is driven LO by drive transistor 318; and state conductor 330 is driven LO by drive transistor 331. Note that state conductor
- circuit of FIG. 3 illustrates the NAND controlling three state conductors 302, 330 and 330, it could equally well control more or fewer state conductors by including separate drive transistors for each such conductor.
- the circuit of FIG. 2 can also accommodate additional state conductors by including for each a separate drive transistor like 216. To accommodate additional state conductors with the circuit of FIG. 1, we just duplicate the entire circuit for each such conductor. In the circuit of FIG. 3 there are two logic feedback loops that share the
- NAND gate Both of these involve state conductors whose state will change in response to the action of the pulse.
- state conductor 302 will go HI as a result of the pulse slightly before state conductor 320 goes LO, because the drive transistor 304 for state conductor 302 precedes inverter 310 in its logic feedback loop, whereas the drive transistor 318 for state conductor 320 follows the inverter 316 in its logic feedback loop.
- the two inputs to the NAND gate will both go FALSE nearly simultaneously.
- the widths of the two P-type transistors 306 and 308 are chosen so that either of them can return the output to the HI state alone. In this application, both will always act together, and so their widths can be chosen to make their combined action act in the desired time. This usually results in the widths of these transistors being less than would normally be considered proper.
- each of the circuits of FIGs. 1, 2 and 3 we see logic feedback loops involving three logical inversion functions. Ideally, each such feedback loop should act with very nearly the same delay. The reason for wishing to match these delays may be understood with reference to FIG. 4A.
- a first pulse circuit on the left and a second pulse circuit on the right together control the state of the state conductor 416.
- the first pulse circuit is shown as a NAND type, but any type might have been used.
- the second pulse circuit uses the drive transistors themselves to do the NAND function, but again any of the types might be employed.
- FIG. 4B shows the equivalent circuit of this arrangement.
- the inverters 418 and 421 produce outputs nearly identical.
- the NAND gate 428 acts as an inverter also, producing an output that is nearly identical to the output of inverter 420.
- the inputs to transistors 414 and 422 are nearly identical.
- FIGs. 4A and 4B represent a finite state that follows two simple rules. First, when state conductor 416 is LO and the other conditions 402 are TRUE, make the state conductor 416 HI. Second, when state conductor 416 is HI and the other conditions 426 are TRUE, make the state conductor 416 LO.
- FIG. 5 shows five state conductors and three pulse generating circuits.
- Each state conductor represents the state of a separate FIFO stage, where a FIFO stage can be in one of two states: EMPTY or FULL.
- the pulse generating circuits each act when the state conductor on their left is LO and the state conductor on their right is HI, or if there is more than one state conductor to the right, when all such state conductors are HI.
- this circuit forms the proper control for a short FIFO that branches from one input at the left to two outputs at the right. Repeating elements from this circuit in longer chains will form FIFO controls of any length; of course the branching feature may be omitted if desired, it's shown here for illustrative purposes. Recall that each pulse circuit responds when its left input is LO, i.e. the stage to its left is "FULL" and its right input is HI, i.e.
- the left pulse circuit uses a three- input NAND gate 508 to accommodate the three state conductors it uses for input. It drives both state conductors to its right via the two drive transistors 514 and 516. Moreover, the pulses from the pulse circuit can serve other uses. One such use is to condition the pass gates in latches that carry data through the FIFO. Each output labeled "to other uses for pulse" 515, 544, and 546 produces a positive pulse for each action of the corresponding pulse circuit in the FIFO control. These positive pulses are exactly what are needed to condition latches, not shown, to move data through the
- FIFO control systems for example, that have forward latency of six or eight or more gate delays and reverse latencies of four, six or eight or more gate delays. All such systems without limitation are included as special cases of the present invention.
- FIG. 6 shows several symbols and their corresponding circuits, all of which will be recognized as members of the family already described. Of course, such symbols could also represent circuits with a larger number of inverters as described above.
- each of the state conductors may have a small keeper attached.
- a keeper is just a pair of small back to back inverters that holds the state when no drive transistor acts to change it.
- Also not shown in the figure are separate drive transistors, often very small, that precondition the state of each state conductor to the proper initial state during system initialization.
- Each of these symbols represents the circuit associated with one state conductor.
- the symbols of FIG. 6 show various connections between the state conductor and the AND function central to the pulse circuit.
- the pulse circuit is represented by the box; the state conductors by lines connecting one box to another.
- Each such state conductor may carry a label such as "P" as shown in FIG. 6, or identifying numbers, like 722 in Figure 7A for example.
- Each box represents a pulse circuit with multiple state conductors.
- a NAND gate with one real input has several dots indicating zero or more additional inputs.
- each provides a separate input to this NAND gate or output from the NAND gate.
- the state conductor connects to the pulse circuit with an arrowhead, as seen in the upper two rows, the state conductor serves as an input to the NAND gate.
- the pulse circuit drives the state conductor, but without sensing the state conductor's state, as in the lower two rows of FIG. 6.
- a complete pulse circuit may connect to many state conductors, some with arrowheads and some without. Its AND function fires only when the state of the state conductors with arrowheads hold appropriate states. The AND function is insensitive to the states of state conductors drawn without arrowheads.
- a dark arrowhead indicates that just after initialization the state of that state conductor is such as to permit the AND function to fire.
- a light arrowhead indicates that just after initialization the state of that state conductor is such as to prevent the AND function from firing.
- the pulse circuit will fire when each state conductor associated with a light arrowhead has changed state an odd number of times since initialization and each dark arrowhead has changed state an even number of times since initialization.
- FIGs. 7A and 7B represent an "alternator".
- the lines in this drawing represent state conductors, the boxes represent pulse circuits.
- the state conductor 721 at the very left of the drawing initiates the action.
- state conductor 721 indicates FULL
- the pulse circuit 702 fires, rendering state conductor 721 EMPTY and state conductor 722 FULL.
- Now pulse circuit 704 can fire because it has two dark arrowheads, whereas pulse circuit 710 cannot fire because it has one light arrowhead.
- the firing of pulse circuit 704 renders state conductor 722 EMPTY and state conductor 724 FULL and permits pulse circuit 706 to fire.
- FIG. 7B shows a data path suitable for use with the control configuration of
- FIG. 7A Each box with an X represents a pass gate and the following triangle represents a "sticky buffer". Thus, each of the symbols represents a data latch or multiple data latches suitable for holding a parallel data "word" of many bits.
- the control signals for these latches come from the corresponding pulse circuits in FIG. 7A following the form of FIG. 5, "to other uses for pulse”. Through the actions of the pulse outputs of the control circuit of FIG 7B, data will move through this data path alternately on the upper and lower arms.
- Round Robin A similar circuit can deliver information sequentially to any number of outputs.
- the control circuit of FIG. 8 shows how. Here the sequence of operation involves pulse circuits in the sequence 804, 810, 816, 822, 804, 810, ... .
- FIGs. 7 and 8 are really circuit diagrams.
- the lines represent state conductors.
- the boxes represent the pulse circuits that control the transitions between states. The ability to change the state of a state conductor from anywhere along its length makes the diagrams meaningful because each pulse circuit block has access both to the state of the state conductor and the ability to change that state.
- the pulse circuits terminate their actions quickly enough so as not to interfere with each other given logically correct designs.
- some pulse circuits are connected via two parallel state conductors and some by only a single state conductor. Where there is a single state conductor with arrowheads on both ends, both pulse circuits examine its state, and when one fires, it changes the state of the state conductor to permit the other to fire. Where a state conductor connects one pulse circuit to another with an arrowhead only at one end, the pulse circuits thus connected will fire in the sequence indicated by the arrowheads. For example, in FIG. 7A the pulse circuits 704, 706, 710, and 712 must fire in that sequence. The light colored arrowhead at the right of 710 indicates that it cannot fire until after 706 has fired.
- the pulse circuit will operate only when that data bit carries a particular value.
- This behavior makes possible the data conditional branch circuit shown in FIG. 9.
- the logical AND function is split into two parts to obtain a total of three inputs.
- the first part comprises the two-input NAND gate 908, and the second part is the series stack of two N-type drive transistors 910 and 912 that can drive state conductor 924 to the LO state.
- the left input to NAND gate 908 indicates the state of state conductor 902, which makes NAND gate 908 responsive only when state conductor 902 is LO, indicating FULL.
- NAND gate 908 The right input to NAND gate 908 is state conductor 924, which makes NAND gate 908 responsive only when state conductor 908 is HI indicating EMPTY.
- the third input to the AND function is the "data in" signal delivered to the lower of the two N-type transistors 910 and 912 in the series drive stack.
- the two parts of the logical AND function act somewhat separately.
- the NAND gate 908 produces a pulse whenever the two state conductors 902 and 924 indicate the FULL-EMPTY condition. Its action always returns state conductor 902 to the EMPTY state via P-type drive transistor 906.
- the second part of the logical AND function namely the stack of two N-type transistors 910 and 912 acts only when the state condition is FULL-EMPTY and the data input value is also TRUE.
- state conductor 924 will be set to the FULL state only when a TRUE data input is present. If the data input 918 indicates FALSE, state conductor 924 will remain in the EMPTY state. Thus, the value of data input 918 determines whether or not this value is propagated further along the pipeline. The timing of this circuit deserves some consideration. Notice that the two nodes labeled 930 and 932 are driven by inverters 916 and 914 with common inputs.
- FIG. 9 shows a data conditional circuit using the NAND gate form of circuit
- FIG. 10 shows a similar data conditional circuit using the self-resetting form of circuit.
- the logical AND function appears in two parts.
- the first part is the series stack of two N-type transistors 1008 and 1010. It is connected to the left state conductor 1002 and upon acting will change its state to EMPTY.
- the second part of the logical AND function is the series stack of three N-type transistors 1012, 1014 and 1016. It is connected to the right state conductor 1030 via P-type drive transistor 1026 and upon acting will change the state of the right state conductor 1030 to FULL.
- FIG. 20 illustrates a branching section that includes two concurrent FIFO stages: a data-dependent branching stage and a simple FIFO stage.
- the simple FIFO stage formed by pulse circuits 2002 and 2006 propagates the data bit "D" that determines whether to branch to either Al 2004 or Bl 2008. Note that this FIFO is referred to as the "order" FIFO.
- Pulse circuit 2002 receives a data bit D from the data path (dotted lines). Its action depends on the value of that data bit. The general idea is that when the data bit is TRUE, the data values will pass to the upper output via pulse circuit 2004, and when the data bit is FALSE the data values will pass to the lower output via pulse circuit 2008. In both cases, the data bit passes on via the central pulse circuit 2006.
- Pulse circuit 2002 can fire only when its left state conductor 2001 indicates FULL, i.e..., that data are available at the left input to the circuit and all three of its right state conductors, 2010, 201 , and 2014 indicate EMPTY.
- the data bit D conditions the drive of the two output state conductors 2010 and 2014. If D is TRUE, state conductor 2010 changes state. If D is FALSE, state conductor 2014 changes state. In either case, state conductor 2012 changes state.
- FIG. 21 presents an implementation of merging stages that includes four concurrent pipeline stages: the last stage of pipeline A, called Stage A; the last stage of pipeline B, called Stage B; a stage that merges pipeline A and pipeline B, called Merge; and a stage called Control that determines which pipeline to retrieve the next data item from based upon the data value "D".
- pulse circuit 2104 Upon receiving an indication that data are available at its input, as signified by a change of state on state conductor 2124 to the FULL state, and space available at its output, pulse circuit 2104 fires. Depending on the value of the data bit D, it changes the state of either state conductor 2128 or state conductor 2130.
- Pulse circuits Al and B 1 (2108 and 2110 respectively) can fire only when three conditions all exist, as indicated by the three arrows in each. For example, pulse circuit 2108 will fire when the state conductor STAGE A indicates FULL, when the Control has chosen it, and when state conductor 2130 indicates that space is available
- pulse circuit 2104 will set only one of its two output state conductors
- state conductor 2132 is set to the state indicating FULL, enabling pulse circuit 2112 to pass the selected data forward.
- the circuit of FIG. 11 has two state conductors labeled 1102 and 1104 on the left. These are intended as inputs.
- the single state conductor 1106 on the right is an output that will serve either input on demand.
- NAND gates 1132 and 1108 At the left of the drawing are two NAND gates 1132 and 1108 that are cross- coupled to form a mutual exclusion element. If both inputs to one of these NAND gates are HI, its output will be driven LO and thus ensure that both inputs to the other NAND gate cannot both be HI. Thus, at any one time, one and only one of the outputs of these two NAND gates 1132 and 1108 can be LO. That, however, is not the whole story.
- the pair of NAND gates 1132 and 1108 may reach a balanced state in which their outputs lie at some intermediate voltage between HI and LO.
- Such "metastable" states are recognized by those skilled in the art. After a time the metastable state gives way to a state in which one output is HI and the other LO. How long it takes to exit from metastability depends on how closely in time the two inputs arrive and thus how nearly balanced is the initial metastable state of the two NAND gates.
- the logic of this circuit establishes the following logical AND condition for action by the upper and lower logical AND functions.
- the upper function will act if state conductor 1102 is HI and state conductor 1106 is LO and the lower function is guaranteed not to act.
- the guarantee can come either because state conductor 1104 is LO, or because the mutual exclusion element 1132 and 1108 has chosen otherwise.
- the lower AND function can act if state conductor 1104 is HI and state conductor 1106 is LO and the upper function is guaranteed not to act.
- Action by either the upper or lower half circuits accomplishes two things. First, it sets conductor 1106 to HI via P-type drive transistors 1144 or 1146 as the case may be. Second, it sets the chosen left state conductor 1102 or 1104 to LO via the series stack N-type drive transistors 1126 and 1128 or 1114 and 1112 as the case may be. This combination of actions is called “servicing the request.”
- FIGs. 12-19 illustrate the operation of a three-stage first- in-first-out (FIFO) register control circuit.
- FIGs. 12 and 16 there are four state conductors labeled W, X, Y, and Z.
- the NAND gate outputs carry labels A, B and C.
- Amplified pulses suitable for operating the latches of a data path are labeled AA, BB, and CC.
- the "LO is full" circuit form appears in FIG. 12.
- the state conductors W, X, Y and Z represent the full or empty state of successive stages in the control circuit for a FIFO.
- State conductor W represents the state of the input stage to the FIFO
- state conductor Z represents the state of the output stage of the FIFO.
- State conductors X and Y represent states of internal stages of the FIFO.
- the state conductors in this circuit represent the FULL state with a LO signal and the EMPTY state with a HI signal. We call this the "LO-is-FULL" state encoding.
- Data in this FIFO flows from left to right through latches 1202, 1206 and 1210 as well as through intervening logic circuits 1204 and 1208.
- Pulse outputs AA, BB and CC control latches 1202, 1206 and 1210, respectively.
- Each latch is transparent when its control signal is HI, and opaque otherwise.
- the circuit generates HI pulses of short duration on the latch drive outputs. These pulses are suitable for moving data through the latches of the FIFO data path.
- Three pulse circuits 1212, 1216 and 1217 appear in FIG. 12. Each consists of a NAND gate, three inverters, and one P-type and one N-type drive transistor. These drive transistors can drive the state conductors W, X, Y and Z. Note that although the state conductors X and Y appear short in FIG. 12, in actual use they may be quite long if the pulse circuits are far separated in space.
- Each of the pulse circuits responds when it detects that the state to its left is “FULL” and the state to its right is “EMPTY.” Using the chosen "LO-is-FULL” state encoding, this corresponds to a LO state conductor to its left and a HI state conductor to its right. It is easy to see that each NAND gate in FIG. 12 responds to this condition. Each NAND gate produces a LO output signal whenever it detects the FULL-EMPTY condition.
- the LO output from the NAND gate 1220 does three things. First, by using the P-type drive transistor 1221 to its left, it drives its left state conductor, X, to the HI state. Second, by using the inverter 1222 and the N-type drive transistor 1223 to its right, it drives the right state conductor, Y, to the LO state. And third, using the output inverter 1224, it produces a positive output on the latch drive wire BB. The outputs of the other NAND gates 1225 and 1231 act similarly.
- NAND gate 1220 to act, and thus ends the action period of the circuit.
- the drive transistors 1221 and 1223 switch off and the latch control output BB returns to the LO state returning the latches to their normal opaque condition.
- each row of the wave form diagram represents the actions of the signal at the part of the circuit correspondingly labeled.
- the wave form shown for state conductor W is partly dotted, as is the wave form for state conductor Z.
- the dotted part of these wave forms are caused by circuits (not shown in the figure) that serve to deliver input to the circuit shown and serve to accept output from it.
- the parts of the circuit shown in FIG. 12 start an action only when state conductor W goes LO, as shown with a dotted line, indicating that input data are available for the FIFO. Circuits not shown in FIG. 12 will drive state conductor W LO at suitable times. Other circuits not shown in FIG. 12 will drive state conductor Z HI at suitable times. For the purposes of illustration these input and output actions happen at different times in the different figures.
- the first set of wave fonns labeled "input limited” show the operation of the circuit for occasional inputs.
- the FIFO is initially EMPTY as indicated by the HI initial state of state conductors W, X, Y and Z.
- the input circuits not shown, drive state conductor W to the LO state, representing FULL, when new data are available.
- the FIFO control accepts each such input datum and passes it along to the FIFO output.
- state conductor W Shortly after state conductor W goes LO, indicating a new input, the output A of NAND gate 1225 goes LO also. This takes two gate delays, one for the inverter 1226 and one for NAND gate 1225 itself. One gate delay after signal A goes LO, the P-type drive transistor 1227 returns state conductor W to the HI state. Thus, state conductor W remains LO for only three gate delays. State conductor W appears to produce a series of LO pulses. Remember, however, that the leading edge of each such pulse, shown as the dotted descending line, is the result of the action of an N-type drive transistor, not shown. In contrast, only the trailing edge, which rises, is a result of the action of the first NAND gate
- the LO pulse on signal A produces a corresponding HI pulse on output AA, one gate delay later.
- This pulse makes the latches 1202 connected to output AA momentarily transparent and then returns them to their normal opaque state. During their moment of transparency, the latches will copy the input data to their outputs.
- the second pulse circuit 1216 with NAND gate 1220 provides a similar action.
- the wave forms B, BB and Y are similar to those of A, AA and X, but occur 4 gate delays later.
- the forward latency of this control circuit is four gate delays per stage.
- the forward latency shown in FIG. 13 applies only to the leading, i.e. falling, edge of the wave forms W, X, Y and Z.
- the rising edges of the wave forms on state conductors X and Y are the result of actions internal to each pulse circuit. Although they follow with the same delay in FIG. 13, they need not always do so.
- the final pulse circuit 1217 (with NAND gate 1231 producing signal C) drives state conductor Z to the LO state whenever data becomes available in the output stage of the FIFO. This action is shown as the solid part of wave form Z. Suitable circuits, not shown, drive state conductor Z HI again as each datum is removed from the output stage of the FIFO. In the next example we will see what happens if the removal signals are delayed.
- each signal carries a series of pulses.
- the outputs of the NAND gates, A, B and C are truly pulses, because whenever the output of a NAND gate goes LO, it acts to remove the inputs from the
- the pulses on signals AA, BB and CC are a direct result of the pulses on the output of the corresponding NAND gates.
- the pulses on the state conductors W, X, Y and Z are the result of a more complex interaction.
- the pulses on the state conductors are the result of each subsequent stage of the FIFO promptly removing data from its predecessor.
- the falling edges of state conductor X are the result of actions by the N-type drive transistor 1229 which is a part of the leftmost pulse circuit 1212.
- the rising edges of state conductor X are the results of actions by the P-type drive transistor 1221 which is a part of the center pulse circuit.
- wave forms W, X, Y and Z are predominantly HI indicating EMPTY. This indicates that the FIFO is usually EMPTY and awaits data from its input. Each input data element flows through the FIFO in a pattern of pulses as shown in the figure.
- the wave forms of FIG. 14 show the same circuit operating with its output data rate limited.
- the input device not shown, drives state conductor W LO, indicating FULL, as quickly as it can.
- the output device not shown, responsible for driving state conductor Z to the HI state, indicating EMPTY, is less prompt in its action.
- FIG. 14 shows two distinct intervals of operation separated by a dark dashed vertical line. Before the dark line is the “filling" interval during which the FIFO fills up. After the dark line is the “operating" interval during which the FIFO responds each time a data element is removed from it.
- the input and output actions, the dotted portions of wave forms W and Z occur in such a pattern as to create these two distinct intervals of operation.
- state conductor W presents the FIFO with four inputs in rapid succession; these are the four initial dotted descending transitions on state conductor W. However, the fifth such input must wait because the state conductor W remains LO for an extended period.
- FIFO gets three inputs in rapid succession, and state conductor Y, one stage later yet, gets two. These are indicated by the descending parts of their respective wave forms. State conductor Z gets only one input, as indicated by its first descending edge. It thereupon becomes FULL and remains so until the operating interval.
- each state conductor is LO, indicating FULL. Action now awaits removal of a data element from the FIFO.
- the first action in the operating interval is the first rising dotted line in wave form Z.
- the circuits, not shown, that create this rise thus indicate that the output of the FIFO has been received.
- the rise of state conductor Z indicates that the output stage of the FIFO is EMPTY, and may be refilled by actions of the rightmost pulse circuit. Because a data element already waits in the next to last stage of the FIFO, NAND gate 1231 can fire as indicated by wave form C going LO.
- NAND gate 1220 can act, producing a similar pulse on signal B.
- NAND gate 1225 can act, producing a similar pulse on signal A.
- wave form Y is a copy of wave form Z, but delayed by two gate delays.
- wave form X is similarly delayed two gate delays from wave form Y, and so on.
- NAND gate 1220 producing signal B, and the P-type drive transistor 1221 driving X.
- circuits of this type are, in effect, groups of ring oscillators coupled through the AND function offered by the NAND gates 1225, 1220 and 1231 that they share.
- FIGs. 13 and 14 we saw the state conductors waiting in a state appropriate to the actions of the FIFO, waiting in the EMPTY state in FIG. 13 and waiting in the FULL state in FIG. 14.
- FIG. 15 everything is operating as fast as possible and the state conductors spend half of the time FULL and half EMPTY. Because all parts are running at full speed, the state conductors act in the regular pattern shown.
- state conductor Y copies the pattern of state conductor X, four gate delays later, the forward latency. Of course, because the cycle is six gate delays long, state conductor
- X may be thought of as following Y by two gate delays, the reverse latency. It has long been known that the cycle time of an asynchronous FIFO is the sum of its forward and reverse latencies.
- FIGs. 1 and 2 can be combined to form the control for a first in first out (FIFO) circuit.
- FIFO first in first out
- the complete circuit for three stages of such a FIFO appears in FIG. 16.
- the state conductors are labeled W, X, Y and Z.
- This circuit uses the "HI is FULL" state encoding for its state wires, just the reverse of the previous circuit. Again each AND function should respond to the condition FULL-EMPTY, but this time that condition is indicated by the adjacent state conductors being in the HI-LO states.
- the AND function appears in two separate parts. One part consists of the NAND gate 1606 and the other part consists of the two series N-type drive transistors 1604 and 1605.
- a NAND gate also has two series N-type transistors inside it whose inputs are wired in parallel with the inputs to the two series drive transistors 1604 and 1605.
- the two series drive transistors 1604 and 1605 will likewise drive state wire X towards LO.
- FIG. 17 illustrates the operation of the FIFO control when responding to occasional inputs from the left. Initially all of the state signals, W, X, Y and Z are LO indicating EMPTY, because the FIFO is initially EMPTY.
- the dotted portions of wave form W are rising transitions caused by circuits not shown in the figure. Each corresponds to the arrival of a new data element at the input of the FIFO. It is easy to see from FIG. 17 that each such arrival causes the FIFO control to pass action from stage to stage from left to right. Notice that the signals A, B, and C are exactly like those of FIG. 13, as are the signals AA, BB, and CC.
- FIG. 18 shows the operation of the circuit in two distinct intervals of operation separated by a dark dashed vertical line. These, again, are the “filling interval” and the “operating interval.” During the filling interval successively fewer events reach successive stages of the FIFO as it fills. Notice that the state conductors X, Y, Z, and W are initially LO, indicating EMPTY. At the dark vertical line they are all HI, indicating FULL because the FIFO is now completely FULL. During the operating interval, the FIFO action is limited by the rate at which the output circuits, not shown, remove elements from the FIFO by driving state conductor Z to the LO state. Three cycles of such operation appear in FIG. 18. Notice that following each of them the stages act in succession from right to left. They are, of course, passing a "bubble" towards the input of the FIFO, making room for each entry to move forward and ultimately room for another entry to come in from the left.
- the "forward latency" of this circuit is four gate delays.
- the gates are inverter 1607, inverter 1608, the NAND gate 1606, and the P-type driver transistor 1610.
- the reverse latency of this circuit is two gate delays. We can count the gates involved in propagating a falling edge from state conductor Y to state conductor X.
- the gates are the inverter 1611 and the pair of series N-type transistors 1604 and 1605 that drive the state conductor X towards LO.
- the resulting wave forms look much like those of FIG. 15. Here, however, the state conductors are both inverted and one gate delay advanced from those of the earlier figure.
- the HI is FULL form has a number of advantages over the LO is FULL form.
- inverter 1612 and 1607 in FIG. 16 that both take inputs from the state conductor X may be far separated.
- the arbitration circuit of FIG. 11 replaces these two inverters with a mutual exclusion element and its anti-metastability gates.
- Various branch and merge circuits replace one or both of these inverters with NAND gates to combine the inputs from several converging paths.
- FIG. 22 illustrates an address-based distributor circuit in accordance with an embodiment of the present invention.
- This distributor circuit routes an incoming data item from an incoming data stream 2250 through a series of pass gates 2221-2228 and a series of sticky buffers 2231-2237 to one of a number of destination columns 2441- 2443 (see bottom portion of FIG. 22).
- data items passing through pass gates 2221-2228 also include addressing information specifying a destination for each if the data items. This addressing information can be decoded into one-hot form through a one-out-of-four decoder before passing through pulse circuits 2201-2204 in order to simplify the branching process.
- the column (destination) that the data item ultimately gets routed to depends upon an associated address, which selects one of A0, Al, A2 or A3. Note that the circuit illustrated in FIG. 22 is pipelined, so that multiple data items can propagate through the circuit at the same time in lock-step.
- Pulse circuits 2201-2203 are conditional branching units that are configured to fire along the C output if the S input of the pulse circuit receives a logical one value. Otherwise, the pulse circuit fires along the !C input. Note that when the address is decoded, only one of address lines A0, Al, A2 and A3 is asserted. Hence, the data item is only routed to one of columns 2440-2443.
- pulse circuit 2204 does not have to be a conditional branching unit, because if the data item is not destined for one of addresses A0, Al and A2, it must be destined for A3. Furthermore, note that pulse circuits 2211-2214 can be coupled with downstream circuits for each column.
- an indicator for a data item passes through conditional branching units 2201-2204 in pipelined fashion until it reaches a conditional branching unit with an S input that is asserted. At that point, the indicator is routed to one of the column pulse circuits 2211-2214. Note that as the indicator passes through pulse circuits 2201-2204 and 2211-2214, the pulse circuits cause the associated pass gates 2221-2228 to open, which routes the data items to the associated columns. Pulse Circuit
- FIG. 23 A illustrates a pulse circuit in accordance with an embodiment of the present invention.
- this circuit if state conductor 2342 indicates that a preceding stage is full, and if state conductor 2344 indicates that a downstream stage is empty, this circuit generates pulse signal 2345 to cause a corresponding pass gate to open in order to move an associated data item to the downstream stage.
- the circuit also drives state conductor 2344 to indicate that the downstream stage is full and drives state conductor 2342 to indicate that the preceding stage is empty.
- FIG. 23B A circuit implementation of this pulse circuit appears in FIG. 23B.
- the output of NAND gate 2300 goes LOW.
- This LOW signal is inverted through inverter 2302 to a HIGH signal, which activates pulse signal 2345 to open an associated pass gate.
- the LOW output from NAND gate 2300 is also applied to the gate of PMOS transistors 2306, which pulls state conductor 2342 to a HIGH value to indicate that the preceding stage is empty.
- NAND gate 2300 passes through inverter 2308 to cause NMOS transistors 2310 turn on, thereby pulling state conductor 2344 LOW to indicate that the downstream stage is full.
- both inputs to NAND gate 2300 go LOW at about the same time. This causes the output of NAND gate 2300 to go HIGH and the output of inverter 2302 to go LOW, which makes the associated pass gate opaque again, which marks the end of the pulse.
- FIG. 24A illustrates a pulse circuit that supports conditional branching in accordance with an embodiment of the present invention. This circuit functions in the same manner as the circuit illustrated in FIG. 23A, except that a signal 2448 on input S causes one of outputs !C or C to function as the next stage in the pipeline.
- FIG. 24B is a schematic diagram of this pulse circuit. The circuit illustrated in
- FIG. 24B operates in the same manner as the circuit illustrated in FIG. 24A, except that there are two connections to downstream stages 2444 and 2446, instead of one. One of these two connections is activated based upon the state of signal 2448 on input
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US09/676,430 | 2000-09-29 | ||
US09/676,430 US6420907B1 (en) | 2000-09-29 | 2000-09-29 | Method and apparatus for asynchronously controlling state information within a circuit |
US09/854,094 | 2001-05-11 | ||
US09/854,094 US6486709B2 (en) | 2000-09-29 | 2001-05-11 | Distributing data to multiple destinations within an asynchronous circuit |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US5511170A (en) * | 1993-08-02 | 1996-04-23 | Motorola, Inc. | Digital bus data retention |
US5818884A (en) * | 1993-10-26 | 1998-10-06 | General Datacomm, Inc. | High speed synchronous digital data bus system having unterminated data and clock buses |
US6005412A (en) * | 1998-04-08 | 1999-12-21 | S3 Incorporated | AGP/DDR interfaces for full swing and reduced swing (SSTL) signals on an integrated circuit chip |
-
2001
- 2001-08-30 AU AU2001286997A patent/AU2001286997A1/en not_active Abandoned
- 2001-08-30 WO PCT/US2001/027212 patent/WO2002029587A2/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5511170A (en) * | 1993-08-02 | 1996-04-23 | Motorola, Inc. | Digital bus data retention |
US5818884A (en) * | 1993-10-26 | 1998-10-06 | General Datacomm, Inc. | High speed synchronous digital data bus system having unterminated data and clock buses |
US6005412A (en) * | 1998-04-08 | 1999-12-21 | S3 Incorporated | AGP/DDR interfaces for full swing and reduced swing (SSTL) signals on an integrated circuit chip |
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