WO2002027498A3 - Systeme et procede d'identification et de gestion de donnees en flux - Google Patents
Systeme et procede d'identification et de gestion de donnees en flux Download PDFInfo
- Publication number
- WO2002027498A3 WO2002027498A3 PCT/US2001/030395 US0130395W WO0227498A3 WO 2002027498 A3 WO2002027498 A3 WO 2002027498A3 US 0130395 W US0130395 W US 0130395W WO 0227498 A3 WO0227498 A3 WO 0227498A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- cache
- streaming
- request
- cached
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/6028—Prefetching based on hints or prefetch instructions
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2001294856A AU2001294856A1 (en) | 2000-09-29 | 2001-09-27 | System and method for identifying and managing streaming-data |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/677,093 | 2000-09-29 | ||
US09/677,096 US6598124B1 (en) | 2000-09-29 | 2000-09-29 | System and method for identifying streaming-data |
US09/677,096 | 2000-09-29 | ||
US09/677,093 US6578111B1 (en) | 2000-09-29 | 2000-09-29 | Cache memory system and method for managing streaming-data |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002027498A2 WO2002027498A2 (fr) | 2002-04-04 |
WO2002027498A3 true WO2002027498A3 (fr) | 2003-01-23 |
Family
ID=27101706
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2001/030395 WO2002027498A2 (fr) | 2000-09-29 | 2001-09-27 | Systeme et procede d'identification et de gestion de donnees en flux |
Country Status (2)
Country | Link |
---|---|
AU (1) | AU2001294856A1 (fr) |
WO (1) | WO2002027498A2 (fr) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100217937A1 (en) * | 2009-02-20 | 2010-08-26 | Arm Limited | Data processing apparatus and method |
US8516230B2 (en) | 2009-12-29 | 2013-08-20 | International Business Machines Corporation | SPE software instruction cache |
US8522225B2 (en) | 2010-06-25 | 2013-08-27 | International Business Machines Corporation | Rewriting branch instructions using branch stubs |
US8631225B2 (en) | 2010-06-25 | 2014-01-14 | International Business Machines Corporation | Dynamically rewriting branch instructions to directly target an instruction cache location |
US20110320786A1 (en) | 2010-06-25 | 2011-12-29 | International Business Machines Corporation | Dynamically Rewriting Branch Instructions in Response to Cache Line Eviction |
US9459851B2 (en) | 2010-06-25 | 2016-10-04 | International Business Machines Corporation | Arranging binary code based on call graph partitioning |
US8856452B2 (en) | 2011-05-31 | 2014-10-07 | Illinois Institute Of Technology | Timing-aware data prefetching for microprocessors |
US9690710B2 (en) | 2015-01-15 | 2017-06-27 | Qualcomm Incorporated | System and method for improving a victim cache mode in a portable computing device |
CN114860785B (zh) * | 2022-07-08 | 2022-09-06 | 深圳云豹智能有限公司 | 缓存数据处理系统、方法、计算机设备和存储介质 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5546559A (en) * | 1993-06-07 | 1996-08-13 | Hitachi, Ltd. | Cache reuse control system having reuse information field in each cache entry to indicate whether data in the particular entry has higher or lower probability of reuse |
US5732242A (en) * | 1995-03-24 | 1998-03-24 | Silicon Graphics, Inc. | Consistently specifying way destinations through prefetching hints |
US5944815A (en) * | 1998-01-12 | 1999-08-31 | Advanced Micro Devices, Inc. | Microprocessor configured to execute a prefetch instruction including an access count field defining an expected number of access |
WO1999050752A1 (fr) * | 1998-03-31 | 1999-10-07 | Intel Corporation | Structure a antememoire partagee pour instructions temporelles et non-temporelles |
-
2001
- 2001-09-27 AU AU2001294856A patent/AU2001294856A1/en not_active Abandoned
- 2001-09-27 WO PCT/US2001/030395 patent/WO2002027498A2/fr active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5546559A (en) * | 1993-06-07 | 1996-08-13 | Hitachi, Ltd. | Cache reuse control system having reuse information field in each cache entry to indicate whether data in the particular entry has higher or lower probability of reuse |
US5732242A (en) * | 1995-03-24 | 1998-03-24 | Silicon Graphics, Inc. | Consistently specifying way destinations through prefetching hints |
US5944815A (en) * | 1998-01-12 | 1999-08-31 | Advanced Micro Devices, Inc. | Microprocessor configured to execute a prefetch instruction including an access count field defining an expected number of access |
WO1999050752A1 (fr) * | 1998-03-31 | 1999-10-07 | Intel Corporation | Structure a antememoire partagee pour instructions temporelles et non-temporelles |
Non-Patent Citations (1)
Title |
---|
"CONDITIONAL LEAST-RECENTLY-USED DATA CACHE DESIGN TO SUPPORT MULTIMEDIA APPLICATIONS", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 37, no. 2B, 1 February 1994 (1994-02-01), pages 387 - 389, XP000433887, ISSN: 0018-8689 * |
Also Published As
Publication number | Publication date |
---|---|
WO2002027498A2 (fr) | 2002-04-04 |
AU2001294856A1 (en) | 2002-04-08 |
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