ATE493704T1 - Verfahren und vorrichtung zur verwendung eines hilfsrechners zur befehlsvorausholung für einen hauptprozessor - Google Patents

Verfahren und vorrichtung zur verwendung eines hilfsrechners zur befehlsvorausholung für einen hauptprozessor

Info

Publication number
ATE493704T1
ATE493704T1 AT01966737T AT01966737T ATE493704T1 AT E493704 T1 ATE493704 T1 AT E493704T1 AT 01966737 T AT01966737 T AT 01966737T AT 01966737 T AT01966737 T AT 01966737T AT E493704 T1 ATE493704 T1 AT E493704T1
Authority
AT
Austria
Prior art keywords
executable code
processor
primary processor
instructions
assist
Prior art date
Application number
AT01966737T
Other languages
English (en)
Inventor
Shailender Chaudhry
Marc Tremblay
Original Assignee
Oracle America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oracle America Inc filed Critical Oracle America Inc
Application granted granted Critical
Publication of ATE493704T1 publication Critical patent/ATE493704T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Devices For Executing Special Programs (AREA)
AT01966737T 2000-09-08 2001-08-30 Verfahren und vorrichtung zur verwendung eines hilfsrechners zur befehlsvorausholung für einen hauptprozessor ATE493704T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US23145200P 2000-09-08 2000-09-08
PCT/US2001/041962 WO2002021268A2 (en) 2000-09-08 2001-08-30 Method and apparatus for using an assist processor to prefetch instructions for a primary processor

Publications (1)

Publication Number Publication Date
ATE493704T1 true ATE493704T1 (de) 2011-01-15

Family

ID=22869286

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01966737T ATE493704T1 (de) 2000-09-08 2001-08-30 Verfahren und vorrichtung zur verwendung eines hilfsrechners zur befehlsvorausholung für einen hauptprozessor

Country Status (9)

Country Link
US (1) US6681318B2 (de)
EP (1) EP1316015B1 (de)
JP (1) JP4808910B2 (de)
KR (1) KR100792320B1 (de)
CN (1) CN1207659C (de)
AT (1) ATE493704T1 (de)
AU (1) AU2001287222A1 (de)
DE (1) DE60143757D1 (de)
WO (1) WO2002021268A2 (de)

Families Citing this family (17)

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Publication number Priority date Publication date Assignee Title
EP1387259B1 (de) * 2002-07-31 2017-09-20 Texas Instruments Incorporated Zwischen-Prozessor Steuerung
US7155575B2 (en) * 2002-12-18 2006-12-26 Intel Corporation Adaptive prefetch for irregular access patterns
US20040186960A1 (en) * 2003-03-20 2004-09-23 Sun Microsystems, Inc. Computer processor data prefetch unit
CN100489813C (zh) * 2003-04-21 2009-05-20 智慧第一公司 可选择性撤回预取的方法
JP2006268487A (ja) * 2005-03-24 2006-10-05 Nec Corp エミュレーション装置及びエミュレーション方法、並びに、エミュレーションプログラム
US7472256B1 (en) 2005-04-12 2008-12-30 Sun Microsystems, Inc. Software value prediction using pendency records of predicted prefetch values
US8019947B2 (en) * 2005-10-19 2011-09-13 Intel Corporation Technique for thread communication and synchronization
KR101360221B1 (ko) * 2007-09-13 2014-02-10 삼성전자주식회사 인스트럭션 캐시 관리 방법 및 그 방법을 이용하는프로세서
FR2928753B1 (fr) 2008-03-14 2012-09-21 Pierre Fiorini Architecture de traitement informatique accelere.
CA2672337C (en) 2009-07-15 2017-01-03 Ibm Canada Limited - Ibm Canada Limitee Compiler instrumentation infrastructure to facilitate multiple pass and multiple purpose dynamic analysis
US8418156B2 (en) * 2009-12-16 2013-04-09 Intel Corporation Two-stage commit (TSC) region for dynamic binary optimization in X86
CN102117198B (zh) 2009-12-31 2015-07-15 上海芯豪微电子有限公司 一种分支处理方法
WO2011076120A1 (en) * 2009-12-25 2011-06-30 Shanghai Xin Hao Micro Electronics Co. Ltd. High-performance cache system and method
JP5541491B2 (ja) * 2010-01-07 2014-07-09 日本電気株式会社 マルチプロセッサ、これを用いたコンピュータシステム、およびマルチプロセッサの処理方法
GB2509765B (en) * 2013-01-15 2015-07-15 Imagination Tech Ltd Improved control of pre-fetch traffic
US10896130B2 (en) * 2016-10-19 2021-01-19 International Business Machines Corporation Response times in asynchronous I/O-based software using thread pairing and co-execution
US11755333B2 (en) 2021-09-23 2023-09-12 Apple Inc. Coprocessor prefetcher

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4991080A (en) 1986-03-13 1991-02-05 International Business Machines Corporation Pipeline processing apparatus for executing instructions in three streams, including branch stream pre-execution processor for pre-executing conditional branch instructions
DE68928937T2 (de) * 1988-12-27 1999-07-01 Fujitsu Ltd., Kawasaki, Kanagawa Steuerungssystem und -verfahren zum Instruction Fetch
US5392391A (en) 1991-10-18 1995-02-21 Lsi Logic Corporation High performance graphics applications controller
GB9426155D0 (en) 1994-12-23 1995-02-22 Univ Manchester Dual processor decoupling
US5787285A (en) 1995-08-15 1998-07-28 International Business Machines Corporation Apparatus and method for optimizing applications for multiple operational environments or modes
US5961631A (en) 1997-07-16 1999-10-05 Arm Limited Data processing apparatus and method for pre-fetching an instruction in to an instruction cache
US6205544B1 (en) 1998-12-21 2001-03-20 Intel Corporation Decomposition of instructions into branch and sequential code sections
US6415356B1 (en) * 2000-01-14 2002-07-02 Sun Microsystems, Inc. Method and apparatus for using an assist processor to pre-fetch data values for a primary processor
KR100463642B1 (ko) * 2003-03-06 2004-12-29 한국과학기술원 보조프로세서를 이용한 멀티미디어 처리를 위한 가속장치

Also Published As

Publication number Publication date
EP1316015A2 (de) 2003-06-04
KR100792320B1 (ko) 2008-01-07
JP2004517383A (ja) 2004-06-10
KR20030034172A (ko) 2003-05-01
WO2002021268A3 (en) 2002-06-06
WO2002021268A2 (en) 2002-03-14
AU2001287222A1 (en) 2002-03-22
EP1316015B1 (de) 2010-12-29
JP4808910B2 (ja) 2011-11-02
US20020095563A1 (en) 2002-07-18
US6681318B2 (en) 2004-01-20
DE60143757D1 (de) 2011-02-10
CN1466716A (zh) 2004-01-07
CN1207659C (zh) 2005-06-22

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