WO2002027474A1 - Execution d'une instruction combinee - Google Patents

Execution d'une instruction combinee Download PDF

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Publication number
WO2002027474A1
WO2002027474A1 PCT/GB2001/004301 GB0104301W WO0227474A1 WO 2002027474 A1 WO2002027474 A1 WO 2002027474A1 GB 0104301 W GB0104301 W GB 0104301W WO 0227474 A1 WO0227474 A1 WO 0227474A1
Authority
WO
WIPO (PCT)
Prior art keywords
instruction
values
result value
execution
random
Prior art date
Application number
PCT/GB2001/004301
Other languages
English (en)
Inventor
Nigel Paul Smart
Michael David May
Hendrik Lambertus Muller
Original Assignee
University Of Bristol
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University Of Bristol filed Critical University Of Bristol
Priority to AU2001290114A priority Critical patent/AU2001290114A1/en
Publication of WO2002027474A1 publication Critical patent/WO2002027474A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/08—Randomization, e.g. dummy operations or using noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H04L2209/125—Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations

Abstract

Procédé d'exécution d'un programme informatique afin d'effectuer une opération définie par une instruction informatique dudit programme sur un ensemble de valeurs, ce qui consiste, en une étape, à effectuer l'opération définie sur une première paire de valeurs sélectionnées de façon aléatoire dans ledit ensemble et à générer une valeur de résultat faisant ensuite partie dudit ensemble de valeurs. On répète ladite étape sur des paires successives de valeurs sélectionnées au hasard jusqu'à l'obtention d'une seule valeur de résultat, ce qui permet au profil d'exécution de ladite instruction informatique de différer lors de ces exécutions successives.
PCT/GB2001/004301 2000-09-27 2001-09-26 Execution d'une instruction combinee WO2002027474A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001290114A AU2001290114A1 (en) 2000-09-27 2001-09-26 Executing a combined instruction

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0023699.2 2000-09-27
GBGB0023699.2A GB0023699D0 (en) 2000-09-27 2000-09-27 Executing a combined instruction

Publications (1)

Publication Number Publication Date
WO2002027474A1 true WO2002027474A1 (fr) 2002-04-04

Family

ID=9900251

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2001/004301 WO2002027474A1 (fr) 2000-09-27 2001-09-26 Execution d'une instruction combinee

Country Status (3)

Country Link
AU (1) AU2001290114A1 (fr)
GB (1) GB0023699D0 (fr)
WO (1) WO2002027474A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2382672A (en) * 2001-10-31 2003-06-04 Alphamosaic Ltd Repeated instruction execution
EP1450234A2 (fr) * 2003-02-24 2004-08-25 Infineon Technologies AG Dispositif et procédé de détection de l'exécution anormale d'un programme d'application
WO2005029489A1 (fr) * 2003-09-25 2005-03-31 Samsung Electronics Co., Ltd. Appareil et procede de presentation de donnees multimedia combinees a du texte, et support d'enregistrement contenant un programme d'execution dudit procede
EP1576443A2 (fr) * 2002-12-24 2005-09-21 Trusted Logic Procede pour la securisation des systemes informatiques incorporant un module d interpretation de code

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0967544A2 (fr) * 1998-06-25 1999-12-29 Texas Instruments Incorporated Processeur de signaux numériques pour les données à longueur de bit grande
WO2000008542A1 (fr) * 1998-07-31 2000-02-17 Koninklijke Philips Electronics N.V. Machine de traitement de donnees pourvue de moyens d'obvier a des methodes d'analyses aux fins de la detection d'une valeur propre de secret
EP1006492A1 (fr) * 1998-11-30 2000-06-07 Hitachi, Ltd. Dispositif et carte à puce pour le traitement de données

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0967544A2 (fr) * 1998-06-25 1999-12-29 Texas Instruments Incorporated Processeur de signaux numériques pour les données à longueur de bit grande
WO2000008542A1 (fr) * 1998-07-31 2000-02-17 Koninklijke Philips Electronics N.V. Machine de traitement de donnees pourvue de moyens d'obvier a des methodes d'analyses aux fins de la detection d'une valeur propre de secret
EP1006492A1 (fr) * 1998-11-30 2000-06-07 Hitachi, Ltd. Dispositif et carte à puce pour le traitement de données

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2382672A (en) * 2001-10-31 2003-06-04 Alphamosaic Ltd Repeated instruction execution
GB2382672B (en) * 2001-10-31 2005-10-05 Alphamosaic Ltd Repeated instruction execution
EP1576443A2 (fr) * 2002-12-24 2005-09-21 Trusted Logic Procede pour la securisation des systemes informatiques incorporant un module d interpretation de code
EP1450234A2 (fr) * 2003-02-24 2004-08-25 Infineon Technologies AG Dispositif et procédé de détection de l'exécution anormale d'un programme d'application
EP1450234A3 (fr) * 2003-02-24 2006-10-04 Infineon Technologies AG Dispositif et procédé de détection de l'exécution anormale d'un programme d'application
WO2005029489A1 (fr) * 2003-09-25 2005-03-31 Samsung Electronics Co., Ltd. Appareil et procede de presentation de donnees multimedia combinees a du texte, et support d'enregistrement contenant un programme d'execution dudit procede

Also Published As

Publication number Publication date
AU2001290114A1 (en) 2002-04-08
GB0023699D0 (en) 2000-11-08

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