WO2002025862A2

WO2002025862A2 - Cryptographic encoder/decoder with segmentation and dynamically varying number bases

Info

Publication number: WO2002025862A2
Application number: PCT/US2001/028102
Authority: WO
Inventors: Richard Satterfield
Original assignee: Channel One Communications, Inc.
Priority date: 2000-09-22
Filing date: 2001-09-07
Publication date: 2002-03-28
Also published as: WO2002025862A3

Abstract

Plaintext data elements are converted into different values using a modifying function defined for number bases greater than or equal to 2 and less than or equal to 2M, whre M is the bit width of the data elements. The modifying function takes a data element and a mask element and breaks them up into varying size digits by binary shifting and these digits are combined using addition or subtraction resulting in an encrypted data element. For recovery of the plaintex, the modifications are applied in inverse order.

Description

A MULTIPLE NUMBER BASE ENCODER/DECODER

WITH SEGMENTATION AND DYNAMICALLY

VARYING NUMBER BASES

FIELD OF THE INVENTION The present invention relates to apparatus and methods for encryption and decryption wherein a ciphertext is generated. More particularly, the present invention is related to the use of symmetric private key encryption. Once the sender and receiver have exchanged key information, encryption of a message by the sender and decryption by the receiver is accomplished in a direct manner.

BACKGROUND OF THE INVENTION

In 1917 Neman created a telegraphic cipher system (U.S. patent o. 1,310,719; issued July 22, 1919) which used the addition of the value of a message character on a paper tape with another character on a looped key tape; the sum of the values was transmitted as the cipher character. It was soon recognized that the security of the method relied on very long key tapes. Later to eliminate excessively long key tapes, Morehouse (1918) connected two Neman telegraphic machines together employing two separate looped key tapes so that the output of the first modified the output of the second and this combined output encoded the message tape to create an enciphered message. These two loops had non equal lengths such that all the permutations of the char- acters on one would occur with all the characters on the other. Thus, two shorter tapes could mimic the employment of a single much larger tape. Mauborgne showed that the Morehouse system was cryptographically secure only when the key tape (or the permutation of two tapes) was comparable in length to the clear text to be encrypted and was used only one time. Any repetition of any kind of the key either within that mes- sage or its use to encrypt other messages would compromise the key tape. It was also shown that a ciphertext made using an encryption key the same size as the message it- self but consisting of coherent text could be broken, but not if the key were a collection of random characters.

Dr. Man Young Rhee, in his book Cryptography and Secure Communications (McGraw-Hill, 1994) states on page 12: "A cryptosystem which can resist any cryp- tanalytic attack, no matter how much computation is allowed is said to be unconditionally secure. The one time pad is the only unconditionally secure cipher in use. One of the most remarkable ciphers is the one-time pad in which the ciphertext is the bit-by-bit modulo-2 sum of the plaintext and a nonrepeating keystream of the same length. However, the one-time pad is impractical for most applications because of the large size of the nonrepeating key."

US patent 5,113,444 issued May 12, 1992 entitled "RANDOM CHOICE CIPHER SYSTEM AND METHOD" states "First random number strings are a relatively scarce commodity. Second, the receiver must have at hand exactly the same random number sequence the sender used or must be able to reproduce it. The first of these alternatives requires the sharing of ari enormous amount of key material. The sharing of an enormous amount of key material is impractical. The second alternative is impossible." The first and second conclusions to these statements are inaccurate. Statistical analysis of the sampling of digital sources (specifically 16 bit sound files) shows that random or arbitrary numbers or bytes are readily available in the digi- tal/computer environment. This ready availability of random numbers is contrary to the teachings and opinions of those skilled in the art as well as those expert in the art of cryptography.

Another prevailing view of those skilled in cryptography is that a pseudorandom number series has an inherent weakness because the formula that generated the series may be reconstructed by others to predict the series.

US Patent 5,113,444, entitled "RANDOM CODING CIPHER SYSTEM AND METHODS" and US Patent NO. 5,307,412, teach the use of a thesaurus and/or synonyms together with arithmetic/logic operations to combine data and masks to accomplish encoding/decoding. These patents are thus limited by the use of the thesaurus and synonyms. US PATENT 5,008,935 entitled "EFFICIENT METHOD FOR ENCRYPTING SUPERBLOCK OF DATA" teaches the use of multiple table-lookup combined with binary exclusive-or as a way to permute the sequence of bytes in a buffer. It teaches away from the concept of using this mechanism as a data encrypting/decrypting mechanism for translating data bytes from one value to another.

US. PATENT 5,077,793 entitled "RESIDUE NUMBER ENCRYPTION AND DECRYPTION SYSTEM" teaches (column 3 lines 40 to column 4 lines 8): "If the moduli are chosen to be mutually prime, then all integers with the range of zero to the product of the moduli minus one can be uniquely represented. The importance of the residue number system to numerical process is that the operations of addition, subtraction, and multiplication can be performed without the use of carry operations between the moduli. In other words, each digit in the n-tuple can be operated on independently and in parallel." And shows that for the sum Z of the digits X and Y, the ith digit may be given by:

mod m; and that "a sixteen bit binary number can be represented in the residue number system using five moduli 5,7,11,13,17." The moduli (m;) are chosen to be relatively prime to each other. In Columns 5 and 6 the description goes on to define Z=(X+Y) mod M (where M is the product of all of the moduli, i.e., M=m₁ x m₂ ... m_n,) is a generalization of the Vigenere cipher. If Z=(X-Y) mod M is used to encrypt X using Y then X may be recovered from Z by X=(Y-Z) mod M, which is a gen- eralization of the Beaufort cipher. The method described by this patent requires that multiple and different moduli must be used at the same time to calculate different residues which are transmitted to a receiver to uniquely define the number which was encrypted. The encryption method described herein does not require mutually prime moduli and is different from this patent. Because mutually prime moduli are not re- quired, the encryption/decryption apparatus may be simpler in design.

Pages 13 through 15 in "Applied Cryptography, Second Edition" by Bruce Schneier, John Wiley & Sons, Inc. 1996, provide a critique on the security inherent in the Nigenere encryption method. "The simple-XOR algorithm is really an embarrassment; it's nothing more than a Nigenere poly alphabetic cipher." "There is no real secu- rity here. This kind of encryption is trivial to break, even without computers: It will take only a few seconds with a computer. Assume the plaintext is English. Furthermore, assume the key length is any small number of bytes. Here's how to break it:

1. Discover the length of the key by a procedure known as counting coincidences. XOR the ciphertext against itself shifted various number of bytes, and count those bytes that are equal. If the displacement is a multiple of the key length, then something over 6 percent of the bytes will be equal. If it is not, then less than 0.4 percent will be equal (assuming a random key encrypting normal ASCII text; other plaintext will have different numbers). This is called the index of coincidence. The smallest displacement that indicates a multiple of the key length is the length of the key. 2. Shift the ciphertext by that length and XOR it with itself. This removes the key and leaves you with the plaintext XORed with the plaintext shifted then length of the key. Since English has 1.3 bits of real information per byte, there is plenty of redundancy for determining a unique decryption."

The above method for breaking a Vigenere cipher relies on the fact that XOR (base 2) is its own inverse and that the encrypting key (masking bytes) are repeated many times. The XOR is its own inverse because A XOR B XOR B = A. It is an object of the present invention to improve upon the security of the Nigenere and Variant Beaufort cipher methods by applying them not to characters directly but rather to digits representing that character in another number base. Pages 70 and 71 in "Cryptography: An Introduction to Computer Security" by

Jennifer Seberry and Josef Pieprzyk, Prentice Hall, 1989 - "The Nigenere cipher. The key is specified by a sequence of letters: K=ki ... k where kj, (z-1, ... ,d) gives the amount of shift in the fth alphabet, that is: (a)=a + kj (mod ή)." "Variant Beaufort cipher. Here we use:^(a)=(a - kj) (mod ή). Since a - kj = a + (n - kj) (mod n) the Variant Beaufort cipher is equivalent to the Vigenere cipher with the key character n - kj. The Variant Beaufort cipher is, in fact, the inverse of the Vigenere cipher since if one is used to encipher the other is used to decipher."

Historically the Vigenere and Variant Beaufort ciphers have been applied to whole letters or characters. That is, the value (position in the alphabet) of a character has a number either added or subtracted to it (modulo the length of the alphabet) and the resultant number is used to specify a character position in the alphabet and the character at that position is sent as the ciphered character.

Herein a byte is defined as two or more bits. In typical usage a byte is considered to be, but is not limited to, eight bits. Herein, arrays (or masks) are described as being comprised of elements. Such elements are defined as any actual or logical grouping, for example: a bit, a nibble, a byte or word of any length.

It is an object of the present invention to provide an encryption/decryption apparatus and method that does not depend upon the use of thesaurus. It is yet another object of the present invention to provide an encryption/decryption scheme wherein the presentation of a character in one number base is transformed into a corresponding representation in another number base.

SUMMARY OF THE INVENTION

The foregoing objects are met in an encryption/decryption apparatus where a message or information expressed as elements or characters is to be encrypted from transmission or sending to another where the message will be decrypted. A mask of elements or characters is defined and utilized in the encryption/decryption. The message elements and mask elements are converted into corresponding elements in another new number base system, where this new number base system is a power of 2. The converted message and mask elements are combined, element by element, respectively, wherein each element by element combination can be in a different number base than the previous and the succeeding combination. As discussed below, in a preferred embodiment, the differing number bases may be formed using a bit map together with shifting and adding. The new set of elements is defined as a ciphertext. To decode the ciphertext, mask elements, identical to those used for encryption, are converted into corresponding elements in another number base (the same number base as that of the digits of ciphertext. Then these elements are combined, element by element, respectively using the inverse from that which was used for encryption, thus forming a new set of elements which when converted to a number in the original message number base is the plaintext message.

Herein XORn (XOR+ and XOR-) describes an exclusive-or operation (base n) defined as: let the numbers A and B base n=2^M be defined (for m digits).

Then, in a preferred embodiment, the elements A and B may be combined according to the following equations.

Eq. 1

and C= A XOR- B

Eq. 2 The conversion of a binary number to digits or segments (base nj) is done by the successive division of the number by nj where the remainder of each division becomes the ith digit (or segment) for i=0 to m-l. And where the value of n_j may be changed during the conversion. The digits of a number (base nj) are converted back to binary by: setting sum=0, then for i=m-l to 0 perform sum=(sum * nj) + digit j. When done the result is in sum. For numbers written out in binary notation, the binary bits may be grouped together to form a group of segments, which are then numerically combined as individual segments, with no carry or borrow between the segments. Each segment forms a number base n j where n j=2^M and where M is the number of bits in the segment. For example, if a number in binary has eight bits, the number may be broken into segments each having a different number of bits, but the numbers must add up to the eight so that the whole number is used. So, in this example, the eight bits may be broken into segments of two, one, three and two - totaling the necessary eight bits. Continuing the example, these segment values form the respective number bases as powers of two (binary) of four (2²), two (2¹), eight (2³) and four (2²). Thus more than one number base may be used at a time. When adding or subtracting segments, the original number of bits in the segment is maintained without change. This has the ef- fect of creating an implied AND operation with a bit mask equal to 2^M -1. The size of each segment may be determined by table look-up, numeric computation, digital sampling from a repeatable digital source or a combination of these methods. The binary numbers A and B are broken up or decatenated into segments aj and bj which are then combined according to Eq. 3 and Eq. 4.

(XOR-) Cj = (_ai - bi) Eq. 4

.Whereupon, the output C is the concatenation of the elements cj. In another embodiment, no shown, the order of the elements Ci are shuffled prior to concatenation. And where the order of shuffling is determined by digital sampling or other numeric means. Other implementations allow for the complementation or negation of any of the segments, a;, bi or Ci prior to their use in any of these equations. In yet another implementation, any of these segments a,, b; or c; may be modified by table lookup with or without any pre or post numeric modification. EXAMPLE: The following is a numeric example of the above technique with calculations for two eight bit numbers A=139, B=85 and the number bases no=4, nj=2, n =8 and n₃= (giving segment widths of so=2, sι=l, s₂=3 and s₃=2 bits, respectively for a total of 8 bits - the sum of the segment widths must equal the number of bits in the numbers) then: The remainders from the successive division of A by n(o t_{o 3)} gives: ao=3, a O, a₂=l, a₃=2. Similarly successive division of B by n(o_{to 3)} gives: bo=l, bι=l, b =2, b₃=l. Then combining the a's and b's element by element gives for XOR+ (see EQ. 3): (ao+bo) base 4 = (3+1) where no is base 4 = 0 = Co and

(a_t+b base 2 = (0+1) where n_! is base 2 = 1 = Ci and

(a₂+b₂) base 8 = (1+2) where n₂ is base 8 = 3 = c₂ and

(a₃+b₃) base 4 = (2+1) where n₃ is base 4 = 3 = C₃ and

The setting Sum=0 then sequencing for j=3 to 0 we process: Sum=Sum*n_j + C_j (* is decimal multiplication) which is (0*4)+3 = 3 then (3*8)+3 = 24+3=27 then (27*2)+l = 54+1=55 then (55*4)+0 = 220 = the answer for C.

The value for A may be recovered by converting 220 back into segments as before, then: (co-bo) base 4 = (0-1) = -1 where no is base 4 = 3, for ao (by adding no back or masking the result off to 2 bits i.e. base 4) and

(c_t-bi) base 2 = (1-1) = 0 where no is base 2 = 0 = a_l5 and

(c -b ) base 8 = (3-2) = 1 where no is base 8 = 1 = a₂, and

(c₃-b₃) base 4 = (3-1) = 2 where no is base 4 = 2 = a₃ which when converted back using the appropriate number bases will be our original starting value for A of 139. It should be noted in the above example that C is not the simple addition of A+B, rather it formed by adding segments modulo η where the value of nj can change during the conversion to segments. The simple sum of A+B is 224 which is different from 220, the result of the XOR+ as shown above. Just for com- parison, the simple exclusive-or of A and B is 222 for this example.

Now using XOR- and combining the a's and b's element by element gives (see EQ. 4):

(ao-bo) base 4 = (3-l) = 2 where n₀ is base 4 = 2 = c₀ and

(aι-bι) base 2 = (0-1) =-1 where n_ϊ is base 2 = 1 = cist d

(a -b ) base 8 = (1-2) =-1 where n₂ is base 8 = 7 = c₂and (a₃-b₃) base 4 = (2-1) = 1 where n₃ is base 4 = 1 = c₃ and

Setting Sum=0 then sequencing for j=3 to 0 we process: Sum=Sum*n_j + C_j which is (0*4)+l = 1 then (l*8)+7 = 8+7=15 then (15*2)4-1 = 30+1=31 then (31*4)+2 = 124 = the answer for C.

Note, C equals 124 is different from the simple subtraction of A-B which is 139-85 which is 54.

In a preferred embodiment shown in FIG. 3, a binary bit mask , CE (Carry Enable) is used to control the carry from one bit operation to another. The blocking of a carry provides a segmentation boundary, while the enabling of the carry allows the continuation of the calculation within a segment. With this implementation, a 0 bit starts and terminates a segment while 1 bits enable the segment computation to con- tinue. Not shown, is the complementation or further modification of the CE bits in this embodiment prior to their use specifying segmentation boundaries. When all of the CE bits are set equal to 0, then XOR+ and XOR- is functionally equivalent to an exclusive- or function and when all of the CE bits are set equal to 1, then the XOR+ is equivalent to addition and XOR- is equivalent to subtraction.

The effect of an arbitrary bit pattern in CE on both A and B is to break up each A and B into a set of arbitrary width segments aj and b; and these are then added or subtracted together, segment by segment using Eq. 3 or Eq. 4, forming arbitrary width elements Ci which are then concatenated or combined to produce the final product C. Conversion of data elements A and B to segments a.\ and bj may also be done by table lookup and would be a simple matter for one skilled in the art to implement.

An advantage of the present invention is that an encryption method employing an XOR (base 2) is strengthened by the use of a base greater than 2. This is because A XORn B XORn B does not equal Am(where XORn is one of XOR+ or XOR-). In a preferred embodiment, EQ. 3 is used for encryption and Eq. 4 is used for decryption. Since these are inverse ciphers, in another preferred embodiment Eq. 4 is used instead for encryption and Eq. 3 is used for decryption.

Other objects, features and advantages will be apparent from the following detailed description of preferred embodiments thereof taken in conjunction with the ac- companying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of an XORn operation for C=A XORn B using bit shifting operations.

FIG. 2 is a diagram of a 1 bit adder with a gated input carry section. FIG. 3 is diagram of a XORn operation for C=A XORn B (gated with CE) using the 1 bit adder and carry from FIG. 2.

FIG. 4 is a flowchart of the process diagrammed in FIG. 3.

FIG. 5 is a flowchart version of C = A XORn B (gated with CE) done in parallel. DETAILED DESCRIPTION OF AN ILLUSTRATIVE

EMBODIMENT

FIG. 1 is a diagram of an XORn operation (C=A XORn B) created using shift registers. The input data value, Data Value #1, 21, goes via 22 to the parallel input of shift register, 23. Here under control of CONTROL LOGIC, 39, via 40, to the shift register, 23, bits from the least significant end of the shift register are shifted out via 24. SegWidths, 35, via 36a and 36, is the number of bits to be shifted by the shift register and processed by the ADDER / SUBTRACTOR, 33. Control information also goes via 41 to a serial input, parallel output shift register, 25. This shift register, 25, receives the bits shifted out of 23, via 24. The control logic is created such that, the bits which are shifted in are right justified in the shift register, 25. The (right justified) parallel output of shift register 25 goes via 26 to the "a" input of ADDER / SUBTRACTOR. PMF, 37, is the Plus Minus Flag which designates whether XOR+ (PMF=0) or XOR- (PMF=1) operations are to be performed. This binary flag is complemented when ED=1 thus providing the opposite function for decoding. NumBits, ED, and PMF, 37, via 38a go to the CONTROL LOGIC, 39 to provide information to the control logic. NumBits is the total number of bits to be processed. ED is the encode/decode flag. Normally ED=0 is encode and ED=1 is decode. ED and PMF also go via 38 to the ADDER / SUBTRACTOR, 33, to provide control information. Internally in the ADDER / SUBTRACTOR operation, though not shown, the binary flag PMF1 is used to XOR (binary) each "b" input bit presented via 32, and is also used as a carry-in value for the internal ADDer. PMF1 is set equal to ED XOR PMF. Thus, when PMF1=1, the "b" data values are complemented and with carry-in set equal to 1, the result is that the "b" input data value is now 2's complemented and the resulting ADD will result in a numeric subtract. Any carry-out resulting from internal overflow is ignored. After adding, only the lowest SegWidth, 35, number of bits will be parallel sent out of the ADDER / SUBTRACTOR, 33, via 34 to shift register 47. This has the effect of performing an implied AND to the result of the ADD operation. Note, SegWidth, is a variable and may be changed during the processing of the A and B inputs. The different number bases are powers of two, since in the preferred embodiment, shifting is a power of two change.

The second data value, Data Value "B", 27, is used to modify Data Value "A", 21 and the result of the modification will be Data Value "C", 51. Now Data Value "B", 27, via 28 goes to the parallel input of a shift register 29. The CONTROL LOGIC, 39, via 44 and 43 shifts SegWidth, 35, binary bits from shift register 29 to shift register 31, via 30, in a serial fashion starting with the least significant bits. The shifted value in shift register 31 is right justified within the register. The output of register 31 (right justified) goes via 32 to the "b" input of the ADDER / SUBTRACTOR, 33, where it is combined with the bits from the "a" input, sent via 26 from shift register 25. Under control of the PMFl flag the resulting SegWidth binary bits are parallel sent (right justified), via 34, to shift register 47. The SegWidth number of binary bits in shift register 47 are right justified in the shift register 47, before being shifted to register 49 via 48. Then under control of CONTROL LOGIC, 39, via 45 and 46, the right justified least significant SegWidth bits are shifted out from 47, via 48 to the most significant end of shift register 49. Thus the first SegWidth bits start at the most significant end of register 49, but end up as the least significant SegWidth bits when done This process is repeated until all initial bits which were loaded into shift register 23 and 29 have been processed and a final result resides in shift register 49. When the process is finished, the bits contained in the shift register 49 are parallel sent, via 50, to Data Value "C", 51 , which will now contain the result of the XORn operation.

FIG. 2. is a diagram of a 1 bit adder with a gated input carry section. This adder and gated carry section is item 70 on FIG 3. Starting with the least significant bits and proceeding to the most significant bits, the input values Data Value "A", 21, and Data Value "B", 27 are sent to A, 100, and B, 101 respectively via 22 and 30. Similarly, a , bit is sent from Bit Mask "CE" (FIG. 3, item 55) via 59 to CE, 103. The control logic, 39, initializes Carry_Out, 52, via 61 to the binary value of PMFl where PMF1= PMF XOR ED. Carry_Out, 52 goes via 54 to P_Carry, 104 (Prior Carry). A bit from the Bit Mask "CE", 55 is shifted out of the shift register 57 via 59 to CE, 103. CE is used to form a selector where if CE =0 then Carry_In equals PMF 1 otherwise Carry_In equals the value contained in P_Carry (the prior carry bit). CE, 103, goes via 113 to an AND, 119, and to a NOT (inverter) 114. The output of the NOT, 114, goes via 115 to another AND, 116, where it is logically ANDed with PMFl, 62 (from control logic 39) and the result 117 goes to the OR, 121. Also P_Carry, 104 goes via 118 to the AND, 119, where the logical AND of P_Carry and CE goes via 120 to the OR, 121. The output of the OR, 121, is Carry n, 122 which goes to XOR, 123 and AND 136. Carryjn, 122, as previously stated is either the prior carry (P_Carry = Carry_Out) if CE is equal to 1 or the value of the PMFl flag if CE is equal to 0. Subtraction is achieved (when PMF1=1) by adding the 2's complement of the B input, 101, to the A input, 100. The two's complement is achieved by exclusive-oring the B input bit with PMFl and then also using PMFl as the carry in value for the addition operation. The B input bit, 101 goes via 128 to XOR 127 where it is combined with PMFl, 62, to form BI 129. The output of A, 100, is Al which goes via 130 to: AND 131, XOR 125 and OR 134. A carry-out will occur is either A and B are both 1 or if either A and B are 1 and carry-in is also a 1 bit. The result of the addition, C is equal to the XOR of Al, BI and Carry_In. One part of the carry out calculation is A 100 via 130 (Al) to AND 131 combined with BI via 129 also to AND 131. The result of AND 131 goes via 132 to OR 133. The other part of the calculation is A 100 via 130 (Al) to OR 134 where it is combined with BI via 129 and the logical result goes via 135 to AND 136 where it is combined with Carryjn, 122 and the resulting logical AND 136 goes via 137 also to OR 133. The output of OR 133 goes via 53 to Carry_Out, 52, where it will be used for the next iteration (becoming P_Carry). BI, 129 goes to the XOR 123, where it is combined with Carryjn, 122, and the result 124 goes to XOR 125. A 100 via 130 (Al) also goes to XOR 125. The output of XOR 125 goes via 126 to C 106 where it is sent via 34 to the input of the Data Value "C" shift register 49. This process is repeated un- til all of the bits are processed. The diagram shown in FIG. 2 could be implemented as a gated ripple carry adder/subtractor by any one skilled in the art to process the inputs in a parallel fashion.

FIG 3. is a diagram of a gated XORn operation using a binary bit array Bit Mask "CE" 55 to control the carry operation of the 1 Bit Adder, 70. In the implemen- tation shown, a 0 bit in "CE" causes the prior carry to be ignored with PMFl being used instead to create a segment boundary. PMFl is set equal to PMF XOR ED. The control logic, 39 initializes Carry_Out, 52, to PMFl via 61. This initialization could also be achieved by forcing the first CE bit to have a 0 value. Data Value "A", 21, is sent via 22 to shift register 23. Data Value "B", 27, is sent via 28 to shift register 29 and Bit Mask "CE" is sent via 56 to shift register 57. Then for each input bit the following is performed: A data bit is shifted out of the shift register 23 via 24 to the "A input" of the 1 Bit Adder, 70, and a data modifying bit is shifted out of the shift register 29 via 30 to the "B input" of the 1 Bit Adder, 70, and a gating mask bit is shifted out of the shift register 57 via 59 to the Carry Jϊnb input of the 1 bit adder, 70, and the value of "Carry J)ut is sent via 54 to the P_Carry input of the 1 bit adder 70. Then the result of the add (or subtract) C, FIG. 2, item 106, goes via 34 to the input of shift register 49 where the result of the computation is formed. The Carry )ut computation goes via 53 back to Carry_Out, 52, for use with the next computation, becoming P_Carry in via 54. After all of the bits have been processed, the result is sent from shift register 49 via 50 to Data Value "C", 51.

FIG 4. is a flowchart of the process diagrammed by FIG. 3. At step 1, ED is a binary flag indicating whether the operation is encoding (0) or decoding (1). PMF is the plus-minus-flag used to specify whether a XOR+ (adding) or XOR- (subtracting) operation is to be performed. When PMF=0 then XOR+ is selected and when PMF=1 then a XOR- operation is specified. PMFl is another binary flag which is actually used as part of the Carryjn calculation in step 5 and is set equal to ED XOR PMF. The value of Carry_Out is initialized to PMFl in case the first CE mask bit is not zero. At step 2, a bit is right shifted off the least significant end of the shift register containing the Data Value "A", the data modifier Data Value "B" and the Mask Bit "CE" into A, B and CE respectively. Then BI is set equal to B XOR PMFl. If PMFl is a 1 then BI becomes the l's complement of B. At step 3, if CE is equal to 0, signifying the start or termination of a segment of bits, then we proceed to step 4 where Carry_Out is reinitialized to PMFl . Otherwise we skip step 4 and go directly from step 3 to step 5, leaving the Carry_Out value unchanged. At step 5 several items are calculated. A working value for the Carryjn is set equal to the previously computed value of Carry_Out if CE is equal to 1 (thus allowing the computation within a segment to continue) or if CE is equal to 0 then Carryjn becomes PMFl (allowing the 1 's complemented B 1 value to become a 2's complemented value if PMFl equal 1). The output of the addition, C, is equal to (A AND B 1) OR (Carryjn AND (A or B 1)). The Carry )ut value which will be used for the next iteration (assuming CE=1) is set equal to A XOR BI XOR Carryjn. Then at step 6, the computed sum, C, is right shifted into the most significant end of the Data Value "C" shift register. Then at step 7 if there are more bits which need to be process we go back to step 2 to repeat the these step until all bits have been processed. When all bits have been processed, we go from -step 7 to step 8 to end the processing. At this point, the shift register for Data Value "C" contains the final result.

The ability to vary the effective distance for binary carry or borrow operations of a masking element, B, on a data element, A, combined with an ADD or SUB operation is of a significant benefit in that it creates yet another variable which must be taken into account when an eavesdropper intercepts a message.

FIG. 5 is a flowchart of a method similar to the one in FIG. 4, but done with parallel computation rather than in a bit serial fashion. This flowchart will produce the exact same C values as does the C formed in FIG. 4 if the CE bit Mask contains at least two 0's between 1 bits. This is because the left most 0 of the two 0 bits is where the new segment starts (and acts as a 1 bit) and the parallel method requires that there must be a real "0" between the segments. The reason there must be a 0 bit between the segment of 1 's is so that any carry-out from one segment can not be included in the computation of the next segment. With this parallel method, there is no other way to pre- sevent the carry-out from becoming a carry-in of the next segment unless a real 0 bit (1 bit XOR segment) is inserted between the segments of 1 's (where ADD and SUB occur). Inorder to achieve the extra zero needed, CE bit Mask (CEBM) may be modified as follows:

CEBM= a bit pattern then Ml= CEBM OR integer(CEBM/2) EQ. 5 then M2= NOT(CEBM) AND integer(Ml/2) and Ml EQ. 6 and then CEBM=CEBM AND NOT integer(M2/2) EQ. 7

With EQ. 5, Ml is a bit pattern CEBM with the left most 0 bit which is next to a 1 bit converted to a 1 bit. This is where the two 0's between segments of 1 's becomes one 0 between segments of l's. With EQ. 6, M2 contains a 1 bit at the least significant bit position of any segment of 1 's. And finally with EQ. 7, the l's in M2 are comple- mented to 0's, shifted right 1 bit (by dividing by 2) and then ANDed with CEBM to force that bit position to be a 0.

At step 1, we calculate Ml, NotM and A2 where NotM is the complemented bit pattern for Ml . A2 is equal to Ml AND the input value "A". Below is an example illustrating the relationship between: M, Ml and M2.

EXAMPLE: M = 11100100

M/2 = 01110010 then

M1=M OR (M/2)= = 11110110 now to start the M2 calculations:

NOT(M)= = 00011011 which is ANDed with

(Ml/2) = = 01111011 (Ml ANDed Ml/2) becomes

Tempi

Templ= = 00011011

Ml= = 11110110 tempi ANDed with Ml = M2

= 00010010 = M2, where the 1 's are at the start of a segment. Later on a 1 bit is Or'd to M2 to make sure the first bit has a one if PMF1=1 and a segment for ADDing also starts at bit one. Since Ml contains a 0 at bit 1, it will remove any bits at that bit position for both A and B (in this example).

Where Ml has 0 bits, A2 will also contain 0 bits (this is where XOR computation will occur) later on (see CY). At Step 2, PMFl is tested. If PMFl is 1 the we go to step 3 otherwise we go to step 4. At Step 3, BI is set equal to the complement of B (1 's complement) and M2 is a bit pattern of 1 bits existing only at the start of each segment which when used with ADDing, at step 7, will cause the 1 's complement to become a 2's complement number converting the ADD to a SUB. A 1 is OR'd with M2 just to make sure that the least significant bit of the first segment contains a 1 bit. From either step 3 or step 4 we go to step 5 where B2, CX and CY are calculated. B2 is BI ANDed with Ml. CX equals A2 plus B2, and is later "ANDED" with Ml at step 8. Where Ml containsl's, addition or subtractions will occur. Because there is at least 1 bit between segments (otherwise the segment would be continuous) any carry-out from the A2+B2 operation will be removed in step 8 (by ANDing with Ml again). CY is equal to A XOR B AND NotM and represents the bit pattern resulting from XOR's occurring where "Ml" contains 0 bits. At step 6, if PMFl is equal to 1 we go to step 7 otherwise we go to step 8. At step 7, M2 is added to the value of CX. M2 presents a 1 carry-in bit to complete the 2's complement calculation to change the addition into a subtraction operation, where the l's complement was formed at step 3. At step 8, any extra carry bit in CX are removed by ANDing it again with M . The final result C is the logical OR ofCX and CY.

It will now be apparent to those skilled in the art that other embodiments, improvements, details and uses can be made consistent with the letter and spirit of the foregoing disclosure and within the scope of this patent, which is limited only by the following claims, constraed in accordance with the patent law, including the doctrine of equivalents.

What is claimed is:

Claims

CLAIMS i 1. Encryption/Decryption apparatus comprising:

2 a. means for retrieving information to be encoded/decoded, said informa-

3 tion defining an array Dl of first elements expressed in a number base M,

4 b. first means for converting said first elements into an array D3 of third

5 elements, wherein each of the first elements is converted into a group of one or more

6 third elements, wherein each of the third elements is expressed in a number base which

7 is a power of two, and wherein the sum of the powers for each of the third elements

8 equals M, and wherein the number base may be different for each of said third ele-

9 ments, 0 c. means for retrieving modifying information, said information defining 1 an array D2 of second elements expressed in a number base M, 2 d. second means for converting said second elements into an array D4 of 3 fourth elements, wherein each of the second elements is converted into a group of one 4 or more fourth elements, wherein each of the fourth elements is expressed in a number s base which is a power of two, and wherein the sum of the powers for each of the fourth 6 elements equals M, and wherein the number base may be different for each of said 7 fourth elements, but wherein the sequence of number bases converting the second ele- 8 ments into the fourth elements is the same sequence as used for converting the first 9 elements in step a., 0 e. means for combining arrays D3 and D4 element by element thereby i forming fifth elements of an array D5, and 2 f. second means for converting the elements of D5 into an array of such 3 elements, D6, expressed in a number base M wherein the sixth array, D6, is the cipher- 4 text of Dl when encrypting and wherein array D6 is the plaintext when decrypting.

1 2. Encryption/Decryption apparatus as defined in claim! wherein the expression

2 of the third and fourth elements is any number base.

1 3. The Encryption/Decryption apparatus as defined in claim 1 wherein the means

2 for combining comprises the means for adding, the modulo N determined by the re- 3 spective number base, with the third elements and then adding N and from that sum

4 adding the corresponding fourth elements, the result taken modulo N, forming the ele-

5 ments of the fifth array D 5.

i 4. The Encryption/Decryption apparatus as defined in claim 1 wherein the means

2 for combining comprises the means for adding, the modulo N determined by the re-

3 spective number base, with the third elements and from that sum subtracting the corre-

4 sponding fourth elements the result taken modulo N forming the elements of the fifth

5 array D5.

1 5. The Encryption/Decryption apparatus as defined in claim 1 wherein said array

2 D6 is expressed in a number base different from M.

1 6. The Encryption/Decryption apparatus as defined in claim 1 wherein the means

2 for combining includes a look-up table.

1 7. The Encryption/Decryption apparatus as defined in claim 1 wherein the first

2 means for converting includes a look-up table.

1 8. The Encryption/Decryption apparatus as defined in claim 1 wherein array D2

2 includes numbers selected from the group consisting of random numbers, pseudo-

3 random numbers and arbitrary numbers, or by digital sampling.

i 9. The Encryption/Decryption apparatus as defined in claim 1 wherein said means

2 for combining includes combining said elements d3 of array D3 and elements d4 of ar-

3 ray D4 in accordance with the equation d3 (XOR+) d4.

1 10. The Encryption/Decryption apparatus as defined in claim 1 wherein said means

3 ray D4 in accordance with the equation d3 (XOR-) d4.

i

11. A method for encryption/decryption comprising the steps of: a. retrieving information to be encoded/decoded, said information defining an ar- ray Dl of first elements expressed in a number base M, b. converting said first elements into an array D3 of third elements, wherein each of the first elements is converted into a group of one or more third elements, wherein each of the third elements is expressed in a number base which is a power of two, and wherein the sum of the powers for each of the third elements equals M, and wherein the number base may be different for each of said third elements. c. retrieving fourth elements of an array D4, wherein each of the fourth elements is expressed in a number base which is a power of two, and wherein the sum of the pow- ers for each of the fourth elements equals M, and wherein the number base may be dif- ferent for each of said fourth elements, but wherein the sequence of number bases is the same sequence as used for converting the first elements in step a., d. combining arrays D3 and D4 thereby forming fifth elements of an array D5, and e. converting the elements of D5 into an array of elements, D6, expressed in a number base M, wherein the array D6 is the ciphertext of Dl when encrypting and wherein the array D6 is the plain text if decrypting.

12. The method as defined in claim 11 wherein the expression of the third and fourth elements is in any number base.

13. The method as defined in claim 11 wherein the step of combing comprises the step of adding the elements of D4 and D3 modulo N.

14. The method as defined in claim 11 wherein the step of combing comprises the step of adding N to D3 and subtracting D4 modulo N.

15. The method as defined in claim 11 wherein the step of combining includes the step of looking-up said elements of D5 from a look-up table.

16. The method as defined in claim 11 wherein the first means for converting in- eludes the step of looking-up said elements of D3 from a look-up table.

17. The method as defined in claim 12 wherein the first means for converting in- eludes the step of looking-up said elements of D4 from a look-up table.

18. The method as defined in claim 12 wherein array D2 includes numbers selected from the group consisting of random numbers, pseudo-random numbers and arbitrary numbers.

19. The method as defined in claim 11 wherein said first or second step of convert- ing the first elements includes shifting each elements from which the group of third elements are calculated.