WO2002025714A8 - A process for dry-etching a semiconductor wafer surface - Google Patents

A process for dry-etching a semiconductor wafer surface

Info

Publication number
WO2002025714A8
WO2002025714A8 PCT/EP2001/010134 EP0110134W WO0225714A8 WO 2002025714 A8 WO2002025714 A8 WO 2002025714A8 EP 0110134 W EP0110134 W EP 0110134W WO 0225714 A8 WO0225714 A8 WO 0225714A8
Authority
WO
WIPO (PCT)
Prior art keywords
surface portions
exterior surface
recesses
etching
dry
Prior art date
Application number
PCT/EP2001/010134
Other languages
French (fr)
Other versions
WO2002025714A1 (en
Inventor
Peter Kirchhof
Bernhard Poschenrieder
Virinder Grewal
Thomas Morgenstern
Jens Stolze
Gabriele Fichtl
Original Assignee
Infineon Technologies Sc300
Applied Materials Inc
Peter Kirchhof
Bernhard Poschenrieder
Virinder Grewal
Thomas Morgenstern
Jens Stolze
Gabriele Fichtl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Sc300, Applied Materials Inc, Peter Kirchhof, Bernhard Poschenrieder, Virinder Grewal, Thomas Morgenstern, Jens Stolze, Gabriele Fichtl filed Critical Infineon Technologies Sc300
Publication of WO2002025714A1 publication Critical patent/WO2002025714A1/en
Publication of WO2002025714A8 publication Critical patent/WO2002025714A8/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate

Abstract

A process for dry-etching a semiconductor wafer having exterior surface portions and having recesses between the exterior surface portions is disclosed, wherein the surface is exposed to a plasma etching component and a first material is anisotropically etched by the plasma etching component in bottom regions of the recesses. During anisotropical etching of the first material, the plasma parameters are adjusted in such a way that a layer of a second material is deposited on the exterior surface portions, protecting the exterior surface portions from the plasma etching component and the first material in the recesses being etched selectively to the second material on the exterior surface portions. Due to an aspect ratio dependent net growth/etch rate, bottom regions of recesses can be etched selectively to exposed surface portions on top of the semiconductor surface which are protected by a layer of the second material deposited.
PCT/EP2001/010134 2000-09-20 2001-09-03 A process for dry-etching a semiconductor wafer surface WO2002025714A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP00120174 2000-09-20
EP00120174.8 2000-09-20

Publications (2)

Publication Number Publication Date
WO2002025714A1 WO2002025714A1 (en) 2002-03-28
WO2002025714A8 true WO2002025714A8 (en) 2002-06-06

Family

ID=8169850

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2001/010134 WO2002025714A1 (en) 2000-09-20 2001-09-03 A process for dry-etching a semiconductor wafer surface

Country Status (2)

Country Link
TW (1) TW499714B (en)
WO (1) WO2002025714A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3024777A4 (en) * 2013-07-26 2017-01-11 3M Innovative Properties Company Method of making a nanostructure and nanostructured articles

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2502536B2 (en) * 1986-08-08 1996-05-29 松下電器産業株式会社 Pattern formation method
JP2734915B2 (en) * 1992-11-18 1998-04-02 株式会社デンソー Dry etching method for semiconductor
DE19706682C2 (en) * 1997-02-20 1999-01-14 Bosch Gmbh Robert Anisotropic fluorine-based plasma etching process for silicon
WO1999067817A1 (en) * 1998-06-22 1999-12-29 Applied Materials, Inc. Silicon trench etching using silicon-containing precursors to reduce or avoid mask erosion
KR100514150B1 (en) * 1998-11-04 2005-09-13 서페이스 테크놀로지 시스템스 피엘씨 A method and apparatus for etching a substrate

Also Published As

Publication number Publication date
WO2002025714A1 (en) 2002-03-28
TW499714B (en) 2002-08-21

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