WO2002023601A2 - Method for contact etching using a hardmask and advanced resist technology - Google Patents

Method for contact etching using a hardmask and advanced resist technology Download PDF

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Publication number
WO2002023601A2
WO2002023601A2 PCT/US2001/026647 US0126647W WO0223601A2 WO 2002023601 A2 WO2002023601 A2 WO 2002023601A2 US 0126647 W US0126647 W US 0126647W WO 0223601 A2 WO0223601 A2 WO 0223601A2
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WO
WIPO (PCT)
Prior art keywords
layer
hard mask
dielectric layer
etching
recited
Prior art date
Application number
PCT/US2001/026647
Other languages
French (fr)
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WO2002023601A3 (en
Inventor
Michael Stetter
Uwe Paul Schroeder
Original Assignee
Infineon Technologies North America Corp.
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Publication date
Application filed by Infineon Technologies North America Corp. filed Critical Infineon Technologies North America Corp.
Publication of WO2002023601A2 publication Critical patent/WO2002023601A2/en
Publication of WO2002023601A3 publication Critical patent/WO2002023601A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Definitions

  • This disclosure relates to semiconductor fabrication and more particularly, to
  • ARC anti-reflection coating
  • resist systems combine both features.
  • the imaging layer has to contain silicon to permit a pattern transfer
  • the silicon can be present in the form of a silicon-
  • a dielectric layer 10 is provided on a semiconductor
  • Dielectric layer 10 is to be patterned for contacts, for example.
  • a resist
  • image layer 12 is silylated to include a silylated portion 14.
  • Portion 14 is employed
  • ARC layer 16 As a mask to etch through a bottom layer or ARC layer 16. This is called an ARC
  • layer 16 is about 8000 angstroms thick. The thickness of layer 16 is needed as layer 16 is
  • imaging resist layer is patterned and the anti-reflection coating and the hard mask
  • the dielectric layer is
  • a method for forming contacts for a semiconductor device in accordance with
  • the present invention includes the steps of providing a first dielectric layer on a first level of the semiconductor device, forming a nitride hard mask layer on the first
  • CARL chemical amplification of resist lines
  • imaging resist layer on the anti-reflection layer patterning the imaging resist layer
  • nitride layer by employing the imaging resist layer and the anti-reflection coating as a
  • the dielectric layer may include one of an oxide and an
  • the imaging resist layer may include a chemical amplification of
  • the hard mask may remain after the step of etching the
  • the method may include the steps of depositing a conductive material in holes formed in the dielectric layer and on a sur ace of the hard mask and
  • the method as may include the steps of forming an
  • the imaging resist layer may be included to form the silicon containing image resist
  • the step of etching the anti-reflection coating and the hard mask may include
  • the imaging resist layer preferably includes a thickness of
  • silylated imaging resist layer preferably includes about 30% silicon.
  • FIG. 1 is a cross-sectional view of a conventional stack for patterning a dielectric layer showing a thick resist layer and a thick anti-reflection layer;
  • FIG. 2 is a cross-sectional view of a stack for patterning a dielectric layer
  • FIG. 3 is a cross-sectional view of the stack of FIG. 2 showing the resist layer
  • FIG. 4 is a cross-sectional view of the stack of FIG. 3 showing the resist layer
  • FIG. 5 is a cross-sectional view of the stack of FIG. 3 or 4 showing the anti-
  • FIG. 6 is a cross-sectional view of the stack of FIG. 5 showing the hard mask
  • FIG. 7 is a cross-sectional view of the stack of FIG. 6 showing a dielectric
  • FIG. 8 is a cross-sectional view of the stack of FIG. 7 showing a conductive
  • FIG. 9 is a cross-sectional view of the stack of FIG. 8 showing the conductive
  • FIG. 10 is a cross-sectional view of the stack of FIG. 9 showing another
  • FIG. 11 is a cross-sectional view of the stack of FIG. 10 showing the dielectric
  • FIG. 12 is a cross-sectional view of the stack of FIG. 11 showing a conductive
  • the present invention provides a combination of a resist layer and a
  • the dielectric layer is preferably
  • CARL chemical amplification of resist lines
  • the selectivity between the silylated CARL resist and the nitride is very high.
  • CD critical dimension
  • an etch stop layer and endpoint signal are advantageously
  • the nitride hardmask is employed as an etch mask to pattern
  • the ARC layer is no longer employed as an etch mask.
  • the present invention is advantageously employed only for reflection control. This yields better imaging.
  • the present invention is particularly useful for 0.15 micron and 0.13 micron
  • CMOS complementary metal-oxide-semiconductor
  • ARC layers are one important feature of the present invention. Even conventional
  • chrome on glass masks may be employed in accordance with the present invention.
  • the dielectric layer patterned in accordance with the hardmask may include an
  • the hardmask preferably nitride, will serve as an etch stop and endpoint
  • SILK or another organic material is employed as the dielectric layer, the nitride
  • FIG. 2 a stack of layers is shown employed for patterning a dielectric layer
  • Dielectric layer 102 is formed on a structure 104.
  • Structure 104 may include a
  • the structure 104 may include a plurality of different structures including, but
  • metal lines not limited to metal lines, contacts, diffusion regions, gate structures, capacitors,
  • dielectric layer 102 is employed for electrical isolation of
  • Dielectric layer 102 may include an oxide, such as silicon dioxide, or a glass
  • dielectric layer 102 may be any suitable material such as a boro-phospho silicate glass (BPSG).
  • BPSG boro-phospho silicate glass
  • dielectric layer 102 may be any suitable material.
  • SILK organic material
  • Dielectric layer 102 may also include a plurality of dielectric
  • a top surface of dielectric layer 102 is preferably planarized by for example,
  • a hard mask layer 106 is formed on
  • Hard mask layer 106 preferably includes nitride, although other
  • Hard mask layer 106 may be
  • hard mask layer 106 is nitride and dielectric
  • the thickness of the hard mask layer 106 is preferably
  • hard mask layer 106 is
  • nitride and dielectric layer includes an organic material, the thickness of the hard
  • mask layer 106 is preferably sufficient to handle process losses minus about 50% to
  • An anti-reflection coating (ARC) 108 is formed on hard mask layer 106.
  • ARC 108 is less than
  • ARC 108 may
  • AR3 for example, available commercially from Shipley, Inc. or equivalents.
  • a resist layer 110 is than spun onto a top surface of ARC 108. Resist layer 110
  • resist layer 110 is less than or equal to 2000 angstroms.
  • resist layer 110 is between about 1000-2000 angstroms. Resist layer 110
  • CARL chemical amplification of resist lines
  • resist layer 110 or ARC 108 since hard
  • mask 106 is advantageously provided in accordance with the present invention.
  • a photomask 112 is employed to expose resist layer 110 in accordance with a
  • photomask 112 may be of the chrome on glass type and
  • Resist layer 110 is exposed and developed as shown in FIG. 3. In
  • resist layer 110 is developed in accordance with the exposure pattern of
  • An opening 114 exposes ARC 108 below resist layer 108.
  • resist layer 110 has been developed.
  • Silylation 113 of resist layer 110 may be performed
  • a wet treatment with a silylation solution for example, a solution containing
  • amino-silanes which can react selectively with anhydride groups of resist polymer.
  • opening 114 will advantageously shrink by about 20
  • the silylation step of FIG. 4 may
  • CARL resist is employed as resist 110 and includes a sufficient amount
  • silicon for example 20%-30% silicon by weight.
  • ' ARC 108 is opened by employing a reactive ion
  • etch (RIE) process for example, an oxygen based etch chemistry which may include
  • ARC 108 is opened up, and then, hard mask 106 is
  • dielectric layer 102 e.g., silicon
  • the silicon containing resist may include as much as
  • nitride of hard mask 108 can be etched selectively to the thin
  • a thick bottom layer (e.g., Novolak), as required in
  • dielectric layer 102 is now etched.
  • a RIE etch e.g.,
  • oxygen etch is preferably employed. If dielectric layer 102 includes oxide, the etch
  • a contact hole 116 is formed in or through
  • Contact hole 116 may be adapted for a dual damascene
  • resist layer 110 and ARC 108 are consumed during the oxide etch.
  • a metal or conductive layer 120 are formed over
  • Conductive layer 120 may include
  • barrier (not shown) may be formed in hole 116 prior to the deposition of conductive
  • Conductive layer 120 is planarized to remove conductive materials from
  • hard mask layer 106 and form contact 121.
  • the dielectric layer includes oxide, the CMP is preferably performed selective to nitride of
  • nitride is much harder than, for example, BPSG of dielectric layer 102.
  • a touch up of dielectric layer 102 is no longer needed due to the
  • dielectric layer 102 includes an organic material
  • nitride hard mask 106 may be completely consumed during the etching of hole 116.
  • a conductive layer 120 is deposited and planarized (e.g., with CMP) to dielectric layer 102 and a touch up step may be needed to remove scratches in
  • a dielectric layer 122 is deposited over hard mask
  • a resist layer (not shown) is employed to pattern dielectric layer 122 for
  • the resist layer may be employed with a thin ARC layer, and a
  • dielectric layer 122 includes an oxide, an oxide
  • etch is performed selective to nitride of hard mask 106.
  • dielectric layer 122 includes an organic dielectric, dielectric
  • layer 122 is etched selective to oxide. No hard mask 106 may be present, so
  • selectivity is improved between the resist layer and dielectric layer 122.
  • a conductive material 124 is deposited and planarized (e.g., by
  • Processing may include a hard mask(s) (e.g.,
  • materials 120 and 124 may be deposited in a single step in a dual damascene

Abstract

A method for forming contact holes, in accordance with the present invention, includes forming a hard mask layer on a dielectric layer, forming an anti-reflection coating of less than or equal to 1000 angstroms in thickness on the hard mask layer, and forming a silicon containing imaging resist layer on the anti-reflection layer. The imaging resist layer is patterned and the anti-reflection coating and the hard mask are etched by employing the imaging resist layer as a mask. The dielectric layer is then etched by employing the hard mask as a mask.

Description

INTEGRATION METHOD FOR A HARDMASK CONTACT ETCH USING ADVANCED RESIST TECHNOLOGY
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to
a method for employing a resist hardmask using advanced resist technology.
2. Description of the Related Art
As a result of technological improvements in semiconductor fabrication,
aggressively shrinking device ground rules are needed to increase the productivity
and efficiency of optical lithography processes. In semiconductor fabrication
processes an anti-reflection coating (ARC) is formed prior to the formation of a resist
layer. Thinning the resist to open up the lithographic process window has been the
trend in conventional processes. A thick ARC is employed below the resist layer.
However, a larger photoresist thickness gives better etch performance. Bilayer
resist systems combine both features. For example, a thin imaging layer for
improved imaging and a thick underlayer which acts as an etch mask. For a bilayer
resist system, the imaging layer has to contain silicon to permit a pattern transfer
etch into the underlayer of resist. The silicon can be present in the form of a silicon-
containing substituent of the base polymer or it can be added after development of
the image by a silylation step (if CARL is used). Unfortunately, the underlayer is too
thick. Referring to FIG. 1 , a dielectric layer 10 is provided on a semiconductor
device. Dielectric layer 10 is to be patterned for contacts, for example. A resist
image layer 12 is silylated to include a silylated portion 14. Portion 14 is employed
as a mask to etch through a bottom layer or ARC layer 16. This is called an ARC
open process. To etch through layer 16 is both technically challenging and poorly
controlled. This is in part due to the thickness of layer 16, which is, for example,
about 8000 angstroms thick. The thickness of layer 16 is needed as layer 16 is
employed as an etch mask to transfer the pattern of resist image layer 12 to
dielectric layer 10.
Therefore, a need exists for a method of protecting the resist and critical
dimensions during an ARC open process. A further need exists for a method, which
permits the use of a relatively thin ARC layer below the resist layer.
SUMMARY OF THE INVENTION
A method for forming contact holes, in accordance with the present invention,
includes forming a hard mask layer on a dielectric layer, forming an anti-reflection
coating of less than or equal to 1000 angstroms in thickness on the hard mask layer,
and forming a silicon containing imaging resist layer on the anti-reflection layer. The
imaging resist layer is patterned and the anti-reflection coating and the hard mask
are etched by employing the imaging resist layer as a mask. The dielectric layer is
then etched by employing the hard mask as a mask.
A method for forming contacts for a semiconductor device, in accordance with
the present invention, includes the steps of providing a first dielectric layer on a first level of the semiconductor device, forming a nitride hard mask layer on the first
dielectric layer, forming an anti-reflection coating of less than or equal to 1000
angstroms in thickness on the hard mask layer, forming a silicon containing imaging
resist layer on the anti-reflection layer, patterning the imaging resist layer in
accordance with a hole pattern, etching the anti-reflection coating by employing the
imaging resist layer as a mask, patterning the hard mask in accordance with the
imaging resist layer and the anti-reflection layer, etching the first dielectric layer to
form holes therein by employing the hard mask as an etch mask and filling the holes
in the first dielectric layer to form contacts through the first dielectric layer.
Another method for forming contacts for semiconductor devices employing
groundrules of 0.15 microns or smaller, in accordance with the present invention
includes the steps of providing an oxide layer, forming a nitride layer on the oxide
layer, forming an anti-reflection coating of less than or equal to 1000 angstroms in
thickness on the nitride layer, forming a chemical amplification of resist lines (CARL)
imaging resist layer on the anti-reflection layer, patterning the imaging resist layer,
etching the anti-reflection coating by employing the imaging resist layer, etching the
nitride layer by employing the imaging resist layer and the anti-reflection coating as a
mask, etching the oxide layer to form holes therein by employing the nitride layer as
a mask and filling the holes with conductive material.
In other methods, the dielectric layer may include one of an oxide and an
organic dielectric. The imaging resist layer may include a chemical amplification of
resist lines (CARL) resist. The hard mask may remain after the step of etching the
dielectric layer, and the method may include the steps of depositing a conductive material in holes formed in the dielectric layer and on a sur ace of the hard mask and
planarizing the conductive material to remove the conductive material from the hard
mask such that the hard mask prevents damage to the underlying dielectric layer.
In still other methods, the method as may include the steps of forming an
additional dielectric layer on the hard mask layer and etching the additional dielectric
layer in accordance with a pattern to form openings in communication with the
conductive material in the holes such that the hard mask is employed to indicate
when the etching of the additional dielectric layer is complete. The step of silylating
the imaging resist layer may be included to form the silicon containing image resist
layer. The step of etching the anti-reflection coating and the hard mask may include
the step of consuming the imaging resist layer and the anti-reflection layer during the
etching of the hard mask. The imaging resist layer preferably includes a thickness of
less than or equal to 2000 angstroms. The method CARL imaging resist layer or the
silylated imaging resist layer preferably includes about 30% silicon.
These and other objects, features and advantages of the present invention
will become apparent from the following detailed description of illustrative
embodiments thereof, which is to be read in connection with the accompanying
drawings.
BRIEF DESCRIPTION OF DRAWINGS
This disclosure will present in detail the following description of preferred
embodiments with reference to the following figures wherein:
FIG. 1 is a cross-sectional view of a conventional stack for patterning a dielectric layer showing a thick resist layer and a thick anti-reflection layer;
FIG. 2 is a cross-sectional view of a stack for patterning a dielectric layer
showing a photomask for exposing a resist layer and a hard mask in accordance
with the present invention;
FIG. 3 is a cross-sectional view of the stack of FIG. 2 showing the resist layer
developed in accordance with the present invention;
FIG. 4 is a cross-sectional view of the stack of FIG. 3 showing the resist layer
optionally silylated in accordance with one embodiment of the present invention;
FIG. 5 is a cross-sectional view of the stack of FIG. 3 or 4 showing the anti-
reflection layer opened in accordance with the present invention;
FIG. 6 is a cross-sectional view of the stack of FIG. 5 showing the hard mask
"layef opened in accorda ce with the present invention;
FIG. 7 is a cross-sectional view of the stack of FIG. 6 showing a dielectric
layer patterned in accordance with the hard mask layer in accordance with the
present invention;
FIG. 8 is a cross-sectional view of the stack of FIG. 7 showing a conductive
material layer patterned formed to fill holes in the dielectric layer in accordance with
the present invention;
FIG. 9 is a cross-sectional view of the stack of FIG. 8 showing the conductive
material layer planarized, employing the hard mask as a stop in accordance with the
present invention;
FIG. 10 is a cross-sectional view of the stack of FIG. 9 showing another
dielectric layer formed on the hard mask in accordance with the present invention; i
FIG. 11 is a cross-sectional view of the stack of FIG. 10 showing the dielectric
layer patterned over the hard mask in accordance with the present invention; and
FIG. 12 is a cross-sectional view of the stack of FIG. 11 showing a conductive
material deposited to form a conductive line in accordance with the present
invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The present invention provides a combination of a resist layer and a
hardmask for patterning a dielectric layer. The dielectric layer is preferably
employed for forming contacts or metal lines in a semiconductor device structure. In
a preferred embodiment, CARL (chemical amplification of resist lines) resist is
employed which contains Si to provide an etch selectivity against a nitride layer.
The selectivity between the silylated CARL resist and the nitride is very high.
Therefore, a relatively thin resist layer is employed. This permits improved contact
lithography process windows, where even standard chrome on glass masks may be
employed. This will reduce costs significantly. The thinner resist layer provides better
critical dimension (CD) transfer between the resist layer and the dielectric layer.
Further, by employing a nitride hardmask between an anti-reflection coating (ARC)
and the dielectric layer, an etch stop layer and endpoint signal are advantageously
built into the structure. The nitride hardmask is employed as an etch mask to pattern
the dielectric layer. This solves the problem of reactive ion etch lag and etch tool
control, since the ARC layer is no longer employed as an etch mask. The ARC layer
is advantageously employed only for reflection control. This yields better imaging. The present invention is particularly useful for 0.15 micron and 0.13 micron
technologies (e.g., CMOS technologies) or smaller technologies. However, the
present invention may be useful for larger technologies as well. The hardmask and
method for employing the hardmask, provided by the present invention, will improve
the lithographic process window drastically by permitting thinner resists and thinner
ARC layers. In addition, patterning the resist and transferring the image, in
accordance with the present invention, are more accurate. The thinner resist and
ARC layers are one important feature of the present invention. Even conventional
chrome on glass masks may be employed in accordance with the present invention.
The dielectric layer patterned in accordance with the hardmask may include an
oxide, an organic dielectric or any other suitable dielectric material, which is
selectively etchable relative to the hard mask. In case of the dielectric layer being
oxide, the hardmask, preferably nitride, will serve as an etch stop and endpoint
signal for RIE, thereby reducing the issues with RIE lag and etch tool control. If
SILK or another organic material is employed as the dielectric layer, the nitride
hardmask will be consumed during the process.
Referring now in specific detail to the drawings in which like reference
numerals identify similar or identical elements throughout the several views, and
initially to FIG. 2, a stack of layers is shown employed for patterning a dielectric layer
102. Dielectric layer 102 is formed on a structure 104. Structure 104 may include a
semiconductor substrate and/or dielectric and metal layers. The present invention
applicable to semiconductor devices, such as semiconductor memories, for example
DRAMs, processors, application specific chips, etc. The structure 104 may include a plurality of different structures including, but
not limited to metal lines, contacts, diffusion regions, gate structures, capacitors,
dielectric structures and layer, or any other structure or device known in the art. In a
preferred embodiment, dielectric layer 102 is employed for electrical isolation of
contacts formed within dielectric layer 102.
Dielectric layer 102 may include an oxide, such as silicon dioxide, or a glass
such as a boro-phospho silicate glass (BPSG). Alternatively, dielectric layer 102 may
include an organic material, such as for example, SILK, available commercially from
Dow Chemicals, Inc. Dielectric layer 102 may also include a plurality of dielectric
layers. A top surface of dielectric layer 102 is preferably planarized by for example,
a chemical-mechanical polish (CMP) process. A hard mask layer 106 is formed on
dielectric layer 102. Hard mask layer 106 preferably includes nitride, although other
materials may be employed which provide etch resistance when selectively etching
dielectric layer 102 relative to hard mask 106. Hard mask layer 106 may be
deposited by known methods. When hard mask layer 106 is nitride and dielectric
layer includes an oxide, the thickness of the hard mask layer 106 is preferably
sufficient to handle process losses plus about 100%. When hard mask layer 106 is
nitride and dielectric layer includes an organic material, the thickness of the hard
mask layer 106 is preferably sufficient to handle process losses minus about 50% to
ensure that hard mask layer 106 is thoroughly consumed during the etch.
An anti-reflection coating (ARC) 108 is formed on hard mask layer 106.
Advantageously, in accordance with the present invention, ARC 108 is less than
1000 angstroms, preferably about 800 to 950 angstroms. This is almost an order of magnitude less than the prior art coatings as described above. ARC 108 may
include AR3, for example, available commercially from Shipley, Inc. or equivalents.
A resist layer 110 is than spun onto a top surface of ARC 108. Resist layer 110
includes a thickness, which is equal to or less than the conventional resist layers. In
one embodiment, resist layer 110 is less than or equal to 2000 angstroms.
Preferably, resist layer 110 is between about 1000-2000 angstroms. Resist layer
110 preferably includes a chemical amplification of resist lines (CARL) resist. No
additional resist thickness is needed for resist layer 110 or ARC 108 since hard
mask 106 is advantageously provided in accordance with the present invention.
A photomask 112 is employed to expose resist layer 110 in accordance with a
pattern. Advantageously, photomask 112 may be of the chrome on glass type and
stiH~provideO.15 micron, 0.13 micron or smaller groundrule sizes (e.g., minimum
feature sizes). Resist layer 110 is exposed and developed as shown in FIG. 3. In
FIG. 3, resist layer 110 is developed in accordance with the exposure pattern of
photomask 112. An opening 114 exposes ARC 108 below resist layer 108.
Referring to FIG. 4, after resist layer 110 has been developed, resist layer
110 may be silylated (if CARL resist is employed) to increase the silicon on the
exposed surfaces of resist layer. Silylation 113 of resist layer 110 may be performed
by a wet treatment with a silylation solution, for example, a solution containing
amino-silanes which can react selectively with anhydride groups of resist polymer.
During the silylation process, opening 114 will advantageously shrink by about 20
nm per edge (silylated resist expands). This is another advantage of this process
because the exposure critical dimension (CD) will be more relaxed to begin with, thus allowing a larger lithographic process window. The silylation step of FIG. 4 may
be skipped if CARL resist is employed as resist 110 and includes a sufficient amount
of silicon, for example 20%-30% silicon by weight.
Referring to FIGS. 5 and 6,' ARC 108 is opened by employing a reactive ion
etch (RIE) process, for example, an oxygen based etch chemistry which may include
Argon. In another embodiment, ARC 108 is opened up, and then, hard mask 106 is
opened in an etch process, which is selective to dielectric layer 102 (e.g., silicon
oxide or other material). Since the silicon containing resist may include as much as
30% silicon by weight, nitride of hard mask 108 can be etched selectively to the thin
imaging layer of resist layer 110. A thick bottom layer (e.g., Novolak), as required in
the prior art, which acts as a resist etch mask is therefore no longer necessary. This
permits the elimination of a process step", andΥeduces the number of different resist
materials in the manufacturing line. Multiple resist materials should be eliminated
since setup times for the lithographic tools will be longer and monitoring would be
increased.
Referring to FIG. 7, dielectric layer 102 is now etched. A RIE etch (e.g.,
oxygen etch) is preferably employed. If dielectric layer 102 includes oxide, the etch
is selective to nitride of hard mask 106. A contact hole 116 is formed in or through
dielectric layer 102. Contact hole 116 may be adapted for a dual damascene
process in which contacts and metal lines are formed simultaneously.
Advantageously, resist layer 110 and ARC 108 are consumed during the oxide etch.
The majority of hard mask 106 will also be consumed during the etch of dielectric
layer 102. This leaves a very thin nitride layer, which may then be employed as an etch/polish stop layer in later steps. By employing hard mask 106, processing is
simplified by elimination process steps, and eliminating a bottom layer (thick ARC)
which is difficult to accurately etch. By the present invention, critical dimensions are
more reliably achieved, process windows are increased and processing steps are
eliminated.
Referring to FIGS. 8 and 9, a metal or conductive layer 120 are formed over
hard mask 106 and in hole 116 to fill hole 116. Conductive layer 120 may include
tungsten, aluminum, copper or any other suitable conductive material. A diffusion
barrier (not shown) may be formed in hole 116 prior to the deposition of conductive
layer 116. Conductive layer 120 is planarized to remove conductive materials from
hard mask layer 106 and form contact 121.
Advantageously, hard mask layer! 06 iϊfemplόyed as a stop for the planarizing
process, which may include CMP or an etching process. If CMP is employed and
dielectric layer includes oxide, the CMP is preferably performed selective to nitride of
hard mask 106. The CMP process yields significantly fewer scratches due to the
use of nitride is much harder than, for example, BPSG of dielectric layer 102.
Advantageously, a touch up of dielectric layer 102 is no longer needed due to the
presence of hard mask 106. Conventional processes performed CMP on the
dielectric layer causing scratches, which required a touch up step to fill the
scratches.
In alternate embodiments, if dielectric layer 102 includes an organic material, a
nitride hard mask 106 may be completely consumed during the etching of hole 116.
In this case, a conductive layer 120 is deposited and planarized (e.g., with CMP) to dielectric layer 102 and a touch up step may be needed to remove scratches in
dielectric layer 102.
Referring to FIGS. 10 and 11 , a dielectric layer 122 is deposited over hard mask
layer 106. A resist layer (not shown) is employed to pattern dielectric layer 122 for
conductive lines. The resist layer may be employed with a thin ARC layer, and a
hard mask as described above. If dielectric layer 122 includes an oxide, an oxide
etch is performed selective to nitride of hard mask 106. The nitride of hard mask
106 is employed for an endpoint signal during the formation of openings 127 to
pattern layer 122. The contact 121 is already exposed so no nitride open of hard
mask 106 is needed. If dielectric layer 122 includes an organic dielectric, dielectric
layer 122 is etched selective to oxide. No hard mask 106 may be present, so
selectivity is improved between the resist layer and dielectric layer 122.
Referring to FIG. 12, a conductive material 124 is deposited and planarized (e.g., by
CMP) to form conductive lines 126. Processing may include a hard mask(s) (e.g.,
hard mask 106) as described above in later steps as well. Alternately, conductive
materials 120 and 124 may be deposited in a single step in a dual damascene
process.
By the present invention, better lithographic process windows are achieved
due to very thin imaging layers and due to controlled CD shrinkage during silylation
of the imaging layers. This results in greater flexibility during fabrication. Process
windows are improved thereby holding critical dimensions, reducing the likelihood of
misalignment and permitting larger mask CDs. This permits the use of, e.g., chrome
on glass masks. Better reflection control is provided by the present invention by usage of a second generation ARC instead of a Novolak as anti-reflective material.
Better adhesion between imaging layer and ARC is also achieved as well as a
significantly thinner ARC. Advantageously, no intermixing between the ARC and the
imaging layer is encountered. It is to be understood that the concepts and
processes of the present invention are applicable to single layer resist (SLR) as well
as bilayer resist structures.
Having described preferred embodiments for integration method for a
hardmask contact etch using advanced resist technology (which are intended to be
illustrative and not limiting), it is noted that modifications and variations can be made
by persons skilled in the art in light of the above teachings. It is therefore to be
understood that changes may be made in the particular embodiments of the
invention disclosed which "are within the scope and spirit of the invention as outlined
by the appended claims. Having thus described the invention with the details and
particularity required by the patent laws, what is claimed and desired protected by
Letters Patent is set forth in the appended claims.

Claims

WHAT IS CLAIMED IS:
1. A method for forming contact holes comprising the steps of:
forming a hard mask layer on a dielectric layer;
forming an anti-reflection coating of less than or equal to 1000 angstroms in
thickness on the hard mask layer;
forming a silicon containing imaging resist layer on the anti-reflection layer;
patterning the imaging resist layer;
etching the anti-reflection coating and the hard mask by employing the silylated
imaging resist layer as a mask; and
etching the dielectric layer by employing the hard mask as a mask.
2. The method as recited in claim 1 , wherein the dielectric layer includes one of
an oxide and an organic dielectric.
3. The method as recited in claim 1 , wherein the imaging resist layer includes a
chemical amplification of resist lines (CARL) resist.
4. The method as recited in claim 1 , wherein the hard mask remains after the
step of etching the dielectric layer, the method further comprising the steps of:
depositing a conductive material in holes formed in the dielectric layer and on a
surface of the hard mask; and
planarizing the conductive material to remove the conductive material from the hard
mask such that the hard mask prevents damage to the underlying dielectric layer.
5. The method as recited in claim 4, further comprising the steps of:
forming an additional dielectric layer on the hard mask layer; and
etching the additional dielectric layer in accordance with a pattern to form openings in communication with the conductive material in the holes such that the hard mask
is employed to indicate when the etching of the additional dielectric layer is
complete.
6. The method as recited in claim 1 , further comprising the step of silylating the
imaging resist layer.
7. The method as recited in claim 1 , wherein the step of etching the anti-
reflection coating and the hard mask includes the step of consuming the imaging
resist layer and the anti-reflection layer during the etching of the hard mask.
8. The method as recited in claim 1 , wherein the imaging resist layer includes a
thickness of less than or equal to 2000 angstroms.
9. A method for forming contacts for a semiconductor device comprising the
steps of:
providing a first dielectric layer on a first level of the semiconductor device;
forming a nitride hard mask layer on the first dielectric layer;
forming an anti-reflection coating of less than or equal to 1000 angstroms in
thickness on the hard mask layer;
forming a silicon containing imaging resist layer on the anti-reflection layer;
patterning the imaging resist layer in accordance with a hole pattern;
etching the anti-reflection coating by employing the imaging resist layer as a mask;
patterning the hard mask in accordance with the imaging resist layer
and the anti-reflection layer;
etching the first dielectric layer to form holes therein by employing the
hard mask as an etch mask; and filling the holes in the first dielectric layer to form contacts through the
first dielectric layer.
10. The method as recited in claim 9, wherein the dielectric layer includes one of
an oxide and an organic dielectric.
11. The method as recited in claim 9, wherein the imaging resist layer includes a
chemical amplification of resist lines (CARL) resist.
12. The method as recited in claim 9, wherein the hard mask remains after the
step of etching the first dielectric layer, the step of filling the holes further comprising
the steps of:
depositing a conductive material in the holes formed in the first dielectric layer and
on a surface of the hard mask; and
planarizing the conductive material to remove the conductive material from the hard
mask such that the hard mask prevents damage to the underlying first dielectric
layer.
13. The method as recited in claim 12, further comprising the steps of:
forming a second dielectric layer on the hard mask layer; and
etching the second dielectric layer in accordance with a pattern to form openings in
communication with the conductive material in the holes such that the hard mask is
employed to indicate when the etching of the additional dielectric layer is complete.
14. The method as recited in claim 9, further comprising the step of silylating the
imaging resist layer.
15. The method as recited in claim 9, wherein the step of patterning the hard mask in accordance with the imaging resist layer and the antireflection layer includes
the step of consuming the imaging resist layer and the anti-reflection layer during
etching of the hard mask.
16. The method as recited in claim 9, wherein the imaging resist layer includes a
thickness of less than or equal to 2000 angstroms.
17. A method for forming contacts for semiconductor devices employing
groundrules of 0.15 microns or smaller comprising the steps of:
providing an oxide layer;
forming a nitride layer on the oxide layer;
forming an anti-reflection coating of less than or equal to 1000 angstroms in
thickness on the nitride layer;
forming a chemical amplification of resist lines (CARL) imaging resist layer on the
anti-reflection layer;
patterning the imaging resist layer;
etching the anti-reflection coating by employing the imaging resist layer;
etching the nitride layer by employing the imaging resist layer and the anti-reflection
coating as a mask;
etching the oxide layer to form holes therein by employing the nitride layer as a
mask; and
filling the holes with conductive material.
18. The method as recited in claim 17, wherein the step of patterning the imaging
resist includes employing a chrome on glass photomask.
19. The method as recited in claim 17, wherein the nitride layer remains after the step of etching the oxide layer, the step of filling the holes including the steps of:
depositing the conductive material in the holes and on a surface of the nitride layer;
and
planarizing the conductive material to remove the conductive material from the
nitride layer such that the hard mask prevents damage to the underlying oxide layer.
20. The method as recited in claim 19, further comprising the steps of:
forming an additional dielectric layer on the nitride layer; and
etching the additional dielectric layer in accordance with a pattern to form openings
in communication with the conductive material in the holes such that the nitride layer
is employed to indicate when to the etching of the additional dielectric layer is
complete.
21. The method as recited in claim 17, wherein the CARL imaging resist layer
includes about 30% silicon.
22. The method as recited in claim 17, further comprising the step of consuming
the CARL imaging resist layer and the anti-reflection layer during the etching of the
nitride layer.
23. The method as recited in claim 17, wherein the imaging resist layer includes a
thickness of less than or equal to 2000 angstroms.
PCT/US2001/026647 2000-09-14 2001-08-27 Method for contact etching using a hardmask and advanced resist technology WO2002023601A2 (en)

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