WO2002021282A1

WO2002021282A1 - Method and apparatus for estimating physical parameters in a signal

Info

Publication number: WO2002021282A1
Application number: PCT/SE2001/001882
Authority: WO
Inventors: Anders Host-Madsen; Mikael Skoglund; Peter HÄNDEL; Tomas Andersson
Original assignee: Hällström, Hans
Priority date: 2000-09-04
Filing date: 2001-09-04
Publication date: 2002-03-14
Also published as: SE520067C2; WO2002021282A8; SE0003108D0; AU2001282834A1; SE0003108L

Abstract

A signal processing device for determining at least one parameter of a signal, comprises: a shift register (3) arranged to receive a quantized digital signal and arranged to store temporarily a number of bits corresponding to the number of bits in a number N of samples of the quantized digital signal, memory means (7) comprising at least one look-up table (9) comprising values that may be used to determine said at least one parameter, and address means for determining at least one address of the memory means (7) to be read, in dependence of the content of the shift register (3). The table entries are determined by generating sample signals having known parameter values and determining the shift register values resulting from the sample signals, then entering suitable parameter values in the table (9) in positions corresponding to each shift register address.

Description

Method and Apparatus for Estimating Physical Parameters in a Signal

Technical Field

The invention relates to a method and an electronic circuit for estimating physical parameters of analogue signals by means of processing digital data.

Background

Parameter estimation from a sequence of noise corrupted digital data representing analogue-to-digital (A/D) converted physical signals is an important problem in many applications, for example, to obtain the period, amplitude or initial phase of a signal or the relative phase of two signals. A/D conversion of the analogue input signal will give a digital sequence of length N:

{x[0J,...,x[N-lJ} (1)

A digital sequence is characterized by a quantized value, that is, the analogue signal is sampled at regular time intervals and each sample is quantized by a given number of bits.

For frequency estimation, consider the signal model describing the analogue data at discrete time instants

where A>0 is the amplitude, φ the initial phase, and ₀ is the normalized frequency, 0<fo<l/2, i.Q. fo=F( F_s, Fø being the signal frequency in Hertz of the analogue signal and F_s being the sampling frequency in Hertz. The noise is assumed zero mean with power σ². If the additive noise is white Gaussian, the maximum likelihood estimator (MLE) of the unknown frequency is given by a non-linear least squares fit of a sinusoidal model to the samples. For a large sample-size N, the MLE is well approximated as the location at which the periodogram P(f) (the magnitude squared Fourier trans- form of observations) attains its maximum. No closed formula exists for the location at which P(f) attains its maximum so an exact solution requires an infinite number of arithmetic operations.

An earlier method for frequency estimation uses the Fast Fourier transform (FFT) algorithm, which requires a number of additions and multiplications proportional to 7VTog₂ N where N is the dimension of the transform.

Fast methods with a complexity proportional to JVhave been derived. One such method is outlined below. The autocorrelation sequence

of x[n] in (2) is given by

r[k]=βcos(2πf₀k), k=\, 2, 3,... (3)

where β=A²/2. The E{-} denotes statistical expectation. Using the trigonometric re- lation

>^*[lM3]=β{cos(2π/o) + cos(2π/₀-3)}=2β{cos(2π/₀-2)cos(2π/₀-l)}

it follows that

COS r[lj + r[3]

(' 2ff f₀)= (4) 2r[2J

Replacing the autocorrelations with sample correlations calculated from digital data (1) leads to a frequency estimator that requires «3 N arithmetic operations, that is ?[l] + ?[3] ω = arccos] 2f[2] , (5)

where

fM ^ ∑ _kx[l]x[l - k], = l,2,3 (6)

N - k

In (5), ώ is an estimate of the angular frequency ω=2πf. With digital data represented by b bits (floating-point representation, or fixed-point representation) the method can be implemented in a digital signal processor.

For measuring the relative phase between two signals using a similar method as the one outlined above, the measurements from the two sensors are processed by quadrature mixing and sampling, and are given by

xι[n] = sι[n] + vι[n], x₂[n] = s₂[n] + v₂[n] (7)

where s^n] and s₂[n] are the signals of interest. The circular zero-mean white noise sequences Vi[n] and v₂[n] are mutually uncorrelated. The noise powers θ and σ₂ may, or may not, be equal. The signals from the two channels have the same fre- quency, but different phases, that is,

s_p[n] = A_p exp{j(2πf₀n+φ_p)}, p=l,2 (8)

where A₁ and A₂ are the real-valued amplitudes, A_p>0, p=l,2, (φι,φ₂) are the initial phases, άf₀ is the normalized frequency. The quantity / is defined by j = V- . If the additive noise is white Gaussian, the MLE of the relative phase ψ =cpi-q>2 requires the MLE of frequency. As for the frequency estimation, an exact solution requires an infinite number of arithmetic operations.

A low complexity estimator (with a complexity «N) is as follows.

Ψ ⁼ 1 (9)

^• where * denotes complex conjugate, and where Z[z] denotes the phase angle of the complex-valued scalar z. The cross-correlation in (10) requires 4N (real-valued) multiplications and 2N (real-valued) additions. The phase angle calculation can be implemented by a table look-up with (the In-phase and Quadrature part of) ^n] and x₂[n] quantized by b bits.

From an estimation theoretic point of view, the MLE is the preferred method for estimation of physical parameters of analogue signals from digital data. Besides the fact that the MLE may be hard, or even impossible, to derive, it generally requires an infinite number of calculations to produce the resulting estimate. All solutions of practical interest are subject to a condition on the number of arithmetic calculations. In particular, in applications such as communication, measurement technology and signal processing, high sample rates are considered (typically F_s in the Giga Hertz range) in combination with requirements on real-time processing.

State-of-the-art practical estimators with a numerical complexity proportional to the size of the sample set have been described by aid of the two exemplary descriptions. Problems with state-of-the art solutions are twofold: • Their complexity is still too high for demanding applications. Alternatively, they are too expensive (in terms of silicon area, price, the requirement on analogue or digital preprocessing of data, etc.).

• Their performance (in a statistical sense) is poor. That is, the aim to reduce the numerical complexity has led to an algorithm that is unable to solve the problem subject to given specifications on estimation accuracy.

Summary of the Invention

It is therefore an object of the present invention to provide a method and an appa- ratus for estimating physical parameters in a digital data sequence, in particular one obtained by A/D conversion of an analogue signal, that are simple and inexpensive compared to prior art solutions, yet have a high performance.

This is achieved according to the present invention by a signal processing device for deterrmning at least one parameter of a signal, comprising:

• a shift register arranged to receive a quantized digital signal having a number of bits corresponding to the number of bits in the quantized digital signal, said shift register being arranged to store temporarily a number of bits corresponding to the number of bits in a number N of samples of the quantized digital signal, • memory means comprising at least one look-up table comprising values that may be used to deteπnine said at least one parameter, and

• address means for determining at least one address of the memory means to be read, in dependence of the content of the shift register.

The object is also achieved according to the invention by a method of deteπniriing at least one parameter of an input signal, comprising the steps of

• writing a quantized digital signal to a shift register arranged to store temporarily a number of bits corresponding to the number of bits in a number N of samples of the quantized digital signal; • reading at least one bit from the shift register; • reading a value from at least one address in a memory unit in dependence of the at least one bit read from the shift register.

The apparatus and method according to the invention can be fully implemented in hardware and thus can be used at very high sampling frequencies with typical applications such as measurement systems and radio systems (mobile telephony, etc). They can also be fully implemented in software to an extremely low cost in terms of operations. In its most extreme form the estimator does not require any calculations, only a memory access. This is suitable for applications such as speech processing (e.g. finding the fundamental frequency of the speaker in speech coding applications such as IP telephony and mobile telephony).

The signal processing device preferably further comprises a quantizer arranged to received an input signal to be quantized, and having at least one input and at least one digital output, the output forming the quantized digital signal which is the input to the shift register. If the input to the quantizer is analogue, and the quantizer must also perform analogue to digital conversion. Alternatively, an analogue to digital converter may be provided before the quantizer.

In a preferred embodiment quantizer is a one-bit quantizer. This is particularly suitable in applications requiring very high sample frequencies, in which high- resolution analogue to digital conversion and quantization may be impossible, or economically infeasible. Also, if one-bit quantization is used, no gain control is needed before the A/D converter. The one-bit quantization is also very simple to implement, which makes it popular, for example, for sigma-delta modulators.

Preferably, the address means comprises a first processor arranged between the shift register and the memory unit, for processing the output signal from the shift register before it is used to address at least one table entry of the memory unit. This enables, e.g. simplification of the address found in the shift register, or calculating more than one address based on one shift register entry. The signal processing device may further comprise a second processor arranged to calculate an estimate of at least one physical parameter from said at least one addressed table entry of the memory unit.

The writing of data to, and reading of addresses from, the shift register, respectively, may be controlled by a first clock generating means arranged to provide a first clock signal controlling the input of data to the shift register and a second clock generating means arranged to provide a second clock signal controlling the output of data from the shift register.

A preferred way of training the memory unit before using it to determine parameters from signals is as follows: a) Generating a parameter value for at least one parameter relevant to the input sig- nal; b) Generating a signal having the generated parameter values; c) Determining at least one address obtainable from the shift register resulting from the input of the generated signal; Repeating steps a) b) and c) a number of times sufficient to get a representative number of values. d) Determining, for each shift register address, a suitable memory entry value on the basis of the sets of parameter values associated with this shift register address as determined by steps a) b) and c); e) Entering, for each memory entry, the value determined in step d) in the memory at the location corresponding to the associated shift register address.

In particular, the described solution is based on a novel methodology for design of estimators. A key feature with this methodology is that the quantization in the A/D conversion of analogue signals is taken into account in the design of the estimator.

This method has major advantages compared to known state-of-the-art solutions, which require explicit knowledge of the memory entries, when look-up tables are used to approximate a functional description of the form g(x)=arccos(x), g(z) = Z[z] , etc, whereas the present invention does not.

Brief Description of the Drawings In the following the invention will be described in more detail, by way of embodiments intended to serve as examples only, and with reference to the appended drawings, in which:

Figure 1 is a general depiction of an electronic circuit according to the invention; Figure 2 shows an example of frequency estimation by table look-up procedure; Figure 3 shows how two 4-bit inputs to the first processor may be formed according to the invention; and

Figure 4 is a flow chart showing how a training sequence can be used to determine the table entries according to the invention.

Detailed Description of Embodiments

A general embodiment of the apparatus according to the invention is shown in Figure 1. The apparatus comprises an analogue to digital (A/D) converter 1 receiving one or more analogue input signals and transmitting one or more digital output signals. The input signal can originate from a single sensor or from multiple sensors. If the input signal originates from a number O of sensors, A/D converter 1 quantizes the signal from each sensor by b_k bits, k=0,...,0-1.

The output signal or signals from the A/D converter 1 are fed to a K-bit shift register 3 where binary information is temporarily stored representing a sequence of samples of digital output of said A/D converter 1. With a number O of digital outputs from said A/D converter 1, where each output is represented by b_k bits for k=0,...,O-l, the total number of bits K in the shift register 3 is b_k storing binary information representing N samples of digital output from said A/D converter 1. In the case of a number of O outputs from AD converter it is not necessary to shift in N samples from each output of said AD converter into shift register 3. We can use a different number of samples for each channel, say rik

O-l for k=0...O-l, that is using a shift register with the total number of bits ∑n_kb_k , rep- fc=0 resenting n_k samples of digital output data from each channel of said AD converter 1.

From the shift register 3 the signal or signals are fed to a first processor 5, arranged to calculate one or several output signals forming addresses. The addresses are integers, represented by a given number of bits that are to be used as pointers to one or several memory units 7. The number of output signals from the first processor 5 may be different from the number of input signals. The first processor 5 includes binary operations ("and", "or", "xor", "not"), counters, and the arithmetic operations "+", "-", "*", ^x7" The role of the first processor is to calculate one or several addresses for the forthcoming memory access. This may be done, for example, in one of the following ways: • A simple example would be to calculate the address according to equation

(13). In a mathematical description such as (13) we represent binary data by +1 and -1. In an electronic circuit, of course, a representation with ones and zeros are used, for example, with a 10-bits shift register with contents 1100011100 = 796 (in a decimal representation) point to the 796-th memory entry. With a 10-bits address bus 1024 different memory locations can be addressed. In this example, there is no first processor. • Another simple example is described more in detail in the next section. Several shorter addresses are formed from the sequence in the same manner as above. • It is known that correlations contain information about the frequency, as well as other physical parameters. See, for example, the prior art estimator in equation (5). In (5) the information in the data x[n] has been condensed to the three correlations r[l], r[2] and r[3]. The estimate is then formed by (5). With the present invention, we can form arbitrary correlations from, for ex- ample, binary data, and use them (directly or after some calculations) to address the memories.

Each memory input address unit 7 contains a pre-calculated table 9. Each output from the first processor 5 is input to one of these tables 9.

If needed, a second processor 11 calculates an estimate of one or more physical parameters of said analogue input to the A/D converter 1 from memory data addressed according to the output signals from the first processor 1. The output signal or sig- nals from the second processor 11 therefore describe one or several physical parameters of the input signal to the A/D converter 1. If the value or values read from the memory units correspond directly to the parameters to be estimated, of course the second processor is not needed. The second processor 11 may include the arithmetic operations "+", "-", *", "/", and delay elements and elements such as min() and max(). The operations to be performed by the second processor depend on the type of value or values read from the memory unit and the type of parameter wanted. A simple example would be to calculate an average value of two or more values read from different memory units, or several values read from a single memory unit at different time instants, to obtain a more reliable value. Another example would be to process a value corresponding to the frequency of the signal to obtain a value for the period of the signal, or the other way around.

A first clock generating means 13 generates a first clock signal having a frequency of F_s, used for the timing of the A/D converter 1, the shift register 3 and the first processor 5. A second clock generating means 15 generates a second clock signal having a lower frequency than F_s. For example, the frequency of F_s/N, may be used for the timing of the memory units 7 and the second processor 11. In this way, N sets of input data form the Q addresses to the memoiy units 7 before all values in the memory units 7 are read from the memory units 7. If the input signal is digital, of course, the A/D converter 1 will not be needed. If the digital input signal needs further quantizing, a quantizer must be used in the place of the A/D converter, if not, the input signal may be fed directly to the shift register 3.

In a preferred embodiment, the A/D converter 1 has the same number of analogue input signals and digital output signals, each output represented by b (with b<4) bits.

The table entries in the memory units 7 have been chosen as the conditional expectation of parameters given digital data, that is, minimizing the mean square error (MMSE). The table entries may be calculated by training, for example, as discussed below in connection with Figure 4.

An indirect approach to calculate the conditional expectation of parameters given digital data, and also alternative design criteria than the MMSE criterion can be relevant, for example the Maximum Likelihood (MLE) method or the method of Maximum a Posteriori (MAP).

Using the maximum likelihood criterion to specify how the entries in the memory units are determined in relation to at least one parameter of said input signal can be summarized as follows: letting i_p denote the address to the p:th memory unit, the content of said memory unit at memory location i_p, for each possible value of memory address i_p, is determined by that parameter (parameters) of the input signal that maximizes (maximize) the conditional probability of observing i_p as the address to the p:th memory unit, conditioned on the value (values) of the parameter (parame- ters).

The maximum a posteriori criterion for specifying how the entries in the memory units are determined in relation to at least one parameter of said input signal briefly comprises, assuming that i_p denotes the address to the p:th memory unit: the content of said memory unit at memory location i_p, for each possible value of memory ad- dress i_p, is determined by that parameter (parameters) of the input signal that maximizes (maximize) the conditional probability density function of said parameter (parameters), conditioned that the address to the p:th memory unit has the value i_p.

Consider the signal model given in equation (2). Our aim is to devise an estimator, say , that strives to estimate the true value f₀ of the unknown frequency, based on a block of observed data according to (1). We utilize the assumption that before the data is processed by the estimator, the observations x[n] are quantized to form a binary sequence according to

y[n] = sign( x[n] ) (11)

where sign(x)=l for x>0 and sign(x)=-l for x<0. Our goal is then to find an estimator f:{± l}^N → 5R , operating on the observed and quantized data

{ y[0], ..., y[N-i]} (12)

that is optimal in the sense of minimum mean-square error (MMSE). One key observation is that, because of the quantization the number of possible sequences that can be observed by the estimator is finite. More precisely, we note that a particular observed sequence according to (12) of length N corresponds uniquely to an integer ie {0,l,...,M-l}, with M=2^N, where the mapping from an observed sequence to the index (or address) i can be chosen as

_{i = ∑}-i lW .₂n

^Jn=0 (13)

Since the observed data is of finite resolution there can only be a finite number of possible estimator outputs. Thus, without loss of generality all possible frequency estimators based on a sequence of quantized data, as in (12), can be implemented in two steps: by first determining the index i that corresponds to the observed sequence according to (13), and then using this index as a pointer to a table

f(o)f(ι),...,f( -ι } (14)

containing all possible frequency estimates that can be produced by the estimator. Designing the best possible frequency estimator is then equivalent to constructing the table (14). Under the MMSE criterion, we have that the table entries should be chosen as

/( =£{/ } (15)

where the conditional expectation can be computed under the assumption that a prior distribution for the unknown frequency is known. When the table has been calculated and stored, the operation of the new frequency estimator by table look-up processing can be illustrated as in Figure 2, which is a special case of the method outlined in connection with Figure 1.

Figure 2 shows a simpler version of the apparatus shown in Figure 1, in which it is assumed that there is only one quantized digital signal and only one memory unit is used. In this version, a quantizer 1' receives an input signal. As in Figure 1, the quantizer may also perform A/D conversion, or it may not be needed at all, if the input signal is a quantized digital signal. The quantized signal is input to a shift register 3, and at regular intervals the content of the shift register is used to address a memory unit 7 in the same way as in Figure 1. Because of the simplicity of this embodiment, no first processor, or a very simple one, is needed. The binary address read from the shift register 3 is used directly to address the memory unit 7. The value read from the memory unit 7 according to the address may be used as it is, or it may be processed in a second processor, similar to the one in Figure 1 (not shown in Figure 2).

As in Figure 1, the quantizer 1' and the shift register 3 are controlled by a first clock signal and a second clock signal controls the reading of the address used to address the memory unit from the shift register 3. The frequencies of the clock signals are as discussed in connection with Figure 1. In this case the frequency F_s/N may be suitable for the second clock signal.

If the N-bit sequence is long, it may be desirable to shorten the sequence before using it as an address, to avoid the need for a very large memory unit. One way of doing this is shown in Figure 3, which shows a 10-bit shift register. Only a number of bits, in this case four, out of the ten bits stored in the shift register are selected. The bits may be evenly or unevenly spaced. The selected bits are then used to ad- dress the memory unit or units. In Figure 3, two four-bit sequences are selected, the first sequence comprising the first, second, third and last bits and the second sequence comprising the third, fifth, sixth and eighth bits. These two four-bit sequences may be used as they are, as two binary addresses to address the memory units directly, or they may be input to the first processor and processed to form one or more addresses.

The stored table is designed according to the MMSE criterion, that is, the table entiles are determined according to equation (15).

One straightforward approach to determining the table entries for the tables 9 in Figure 1 is shown in Figure 4. One way of determining the table entries is to use a tiaining sequence T={i_k}_k=ι , where each i_k corresponds to a particular length-TV block of quantized data.

A general tiaining method is shown in Figure 4: Step S 1 : Determine the parameter or parameters that are relevant to the signal concerned. For a signal x(n) as given by equation (2), for example, the parameter that should be obtainable from the memory may be the frequency. Relevant parameters to use when training will include, for de- terministic waveforms such as sine waves, triangle waves and square waves, the amplitude (A), the frequency (f) and the initial phase (φ). Other parameters, such as noise power may be considered as well. For other types of signals, other sets of parameters will be relevant. For example, a pure direct current (DC) signal will be characterized by a level. For of several deterministic waveforms such as a sum of sine waves, several frequencies, phases etc may be identified. In stochastic waveforms such as white noise or coloured noise, parameters such as mean value, covariance and higher order moments may be the parameters searched for. Normally, the signal is described by a mixture of deterministic and stochastic waveforms, such as represented in equations (2) and (7).

Step S2: Generate a parameter value for each of the parameters. This may be done, for example, within certain limits, randomly, or according to a known distribution function, such as a Gaussian curve. Step S3: Generate a signal having the parameter values generated in step S2. Step S4: Determine the address in the shift register resulting from the input of the signal generated in step S3. This is suitably carried out by generating the signal and inputting it to the shift register, then reading the content of the shift register, in the same way as will be done for a signal to be tested later on. The same kind of quantizer and first processor should be used, performing exactly the same functions as will be used when testing signals. Steps S2-S4 are repeated a number of times sufficient to get a representative number of values. The number of times needed depends, for example, on the number of parameters and size of the memory or memories. This procedure results in a large number of shift register addresses, each associated with a set of parameter values. Each shift register address points to an entry in the memory.

Step S5: For each shift register address, determine a suitable table entry value on the basis of the sets of parameter values associated with this shift register address.

Step S6: For each table entry, enter the value determined in step S5 in the memory in the location corresponding to the associated shift register address.

The result of this procedure will be a memory comprising a number of entries, each of which will be addressed by one shift register address.

Regarding step S5, the suitable memory entry may be determined in a number of ways. If there was only one set of parameter values associated with the shift register address, the value of the desired parameter or parameters may be entered directly. If there were more than one set of parameter values associated with the shift register address, the memory entry should be calculated on the basis of all these sets of values. This can be done as discussed above using the MMSE method, using equation (15), the MAP method or the MLE method.

The trade-off between accuracy and computational complexity can be tuned by proper selection of the P multi-bits inputs to first processor (see Figure 1). In particular, non-regularities as illustrated in Figure 3 can be used to ensure high per- formance. Such non-regularity schemes are favourable from an estimation theoretic point of view, but makes FFT processing, and processing employing other state-of- the art methods, impossible.

Claims

1. A signal processing device for determining at least one parameter of a signal, comprising: • a shift register (3) arranged to receive a quantized digital signal having a number of bits corresponding to the number of bits in the quantized digital signal, said shift register being arranged to store temporarily a number of bits corresponding to the number of bits in a number N of samples of the quantized digital signal,

• memory means (7) comprising at least one look-up table (9) comprising values that may be used to determine said at least one parameter, and

• address means for determining at least one address of the memory means (7) to be read, in dependence of the content of the shift register (3).

2. A signal processing device according to claim 1, further comprising a quantizer (1, V) arranged to received an input signal to be quantized, and having at least one input and at least one digital output, the output forming the quantized digital signal which is the input to the shift register.

3. A signal processing device according to claim 2, wherein the input to the quan- tizer (1; 1') s analogue, and the quantizer also performs analogue to digital conversion.

4. A signal processing device according to claim 2 or 3, wherein the quantizer is a one-bit quantizer.

5. A signal processing device according to any one of the preceding claims, wherein the address means comprises a first processor (5) arranged between the shift register (3) and the memory unit (7), for processing the output signal from the shift register before it is used to address at least one table entry of the memory unit.

6. A signal processing device according to any one of the preceding claims, further comprising a second processor arranged to calculate an estimate of at least one physical parameter from said at least one addressed table entry of the memory unit.

7. A signal processing device according to any one of the preceding claims, further comprising a first clock generating means (13) arranged to provide a first clock signal controlling the input of data to the shift register and a second clock generating means (15) arranged to provide a second clock signal controlling the output of data from the shift register.

8. A method of determining at least one parameter of an input signal, comprising the steps of writing a quantized digital signal to a shift register arranged to store temporarily a number of bits corresponding to the number of bits in a number N of samples of the quantized digital signal; reading at least one bit from the shift register; reading a value from at least one address in a memory unit in dependence of the at least one bit read from the shift register.

9. A method according to claim 8, further comprising the step of receiving the input signal and quantizing it to produce the quantized digital signal.

10. A method according to claim 8 or 9, further comprising the step of A/D converting the input signal before quantizing it.

11. A method according to any one of the claims 8-10, further comprising the step of processing the at least one bit read from the shift register to determine the address in the memory unit.

12. A method according to any one of the claims 8-11, further comprising the step of processing the at least one value read from the at least one memory to obtain the parameter of the input signal.

13. A method according to any one of the claims 8-12, further comprising the following steps, carried out before writing the quantized digital signal to the shift register: a) Generating a parameter value for at least one parameter relevant to the input signal; b) Generating a signal having the generated parameter values; c) Deteirriining at least one address obtainable from the shift register resulting from the input of the generated signal; Repeating steps a) b) and c) a number of times sufficient to get a representative number of values. d) Determining, for each shift register address, a suitable memory entry value on the basis of the sets of parameter values associated with this shift register address as determined by steps a) b) and c); e) Entering, for each memory entry, enter the value determined in step d) in the memory in the location corresponding to the associated shift register ad- dress.

AMENDED CLAIMS

[received by the International Bureau on 16 January 2002 (16.01.02); original claims 1-13 replaced by new claims 1-13 (3 pages)]

1. A signal processing device for determining at least one parameter of a signal, said parameter having a non-linear dependency on the signal, comprising • a shift register (3) arranged to receive a quantized digital signal having a number of bits corresponding to the number of bits in the quantized digital signal, said shift register being arranged to store temporarily a number of bits corresponding to the number of bits in a number N of samples of the quantized digital signal,

• memory means (7) comprising at least one look-up table (9) comprising values that may be used to determine said at least one parameter, whereby table entries are chosen as the conditional expectation of said parameters given digital data, and

• address means for determining at least one address of the memory means (7) to be read, mi dependence of the content of the shift register (3).

2. A signal processing device according to claim 1, further comprising a quantizer

15 (1, 1 ') arranged to received an input signal to be quantized, and having at least one input and at least one digital output, the output forming the quantized digital signal which is the input to the shift register.

3. A signal processing according to claim 2, wherein the input to the quantizer (1; 1') is analogue, and the quantizer also performs analogue to digital conversion.

8. A method of determining at least one parameter of an input signal, said parameter having a non-linear dependency on the signal, comprising the steps of writing a quantized digital signal to a shift register arranged to store temporarily a number of bits corresponding to the number of bits in a number N of samples of the 15 quantized digital signal, reading at least one bit from the shift register; reading a value of at least one address, said address being determined from a conditional expectation of said parameters given digital data, in a memory unit in dependence of the at least one bit read from the shift register.

11. A method according to any one of the claims 8- 10, further comprising the step of processing the at least one bit read from the shift register to determine the address in the memory unit.

13. A method according to any one of the claims 8-12, further comprising the following steps, carried out before writing the quantized digital signal to the shift register,

a) Generating a parameter value for at least one parameter relevant to the input signal; b) Generating a signal having the generated parameter values;

c) Determining at least one address obtainable from the shift register resulting from the input of the generated signal;

Repeating steps a) b) and c) a number of times sufficient to get a representative number of values.

d) Determining, for each shift register address, a suitable memory entry value on the basis of the sets of parameter values associated with this shift register address as determining by steps a) b) and c);

e) Entering, for each memory entry, enter the value determined in step d) in the memory in the location corresponding to the associated shift register address.