SE520067C2 - Device and method for estimating parameters in a signal - Google Patents

Abstract

A signal processing device for determining at least one parameter of a signal, comprises: a shift register (3) arranged to receive a quantized digital signal and arranged to store temporarily a number of bits corresponding to the number of bits in a number N of samples of the quantized digital signal, memory means (7) comprising at least one look-up table (9) comprising values that may be used to determine said at least one parameter, and address means for determining at least one address of the memory means (7) to be read, in dependence of the content of the shift register (3). The table entries are determined by generating sample signals having known parameter values and determining the shift register values resulting from the sample signals, then entering suitable parameter values in the table (9) in positions corresponding to each shift register address.

Description

25 30 35 520 067 where ß = A2 / 2. E indicates a statistical expectation. By applying the trigonometric relationship r [i] + r [3] = ß {cos (z fl f,) + cos (z fl fo -3)} = zß {@ 0s (z fl f, -2) COS (z fl f, -1)} from which it follows that cos (znfo) = (4) I 'An exchange of the self-corrections for sample corrections calculated on the basis of digital data (1) leads to a frequency estimate that requires z 3N arithmetic operations, ie 6: 7 = arccos (5) 2r [ 2] where ^ l Ni f [1 <] = -bízm x [1] x [1-1 <11 <= 1,2,3 (6) At (5) à is an estimate of the angular frequency o) = 21rf Med digital data reproduced by b bits (fl surface point reproduction or fixed point reproduction), the procedure can be performed in a digital signal processor.

For measuring the relative phase between two signals using a method similar to that mentioned above, the measurements from sensors are processed by quadrature mixing and sampling, and obtained by Xiinl = Siinl + Vilnl, Xzinl = Szinl + Vzlnl (7) where s, [n] and s2 [n] are the signals of interest. The white average noise sequences v, [n] and v2 [n] with circular zero are mutually uncorrelated. The noise effects of and G22 can be the same, but also different. The signals from the two channels have the same frequency, but different phases, ie: spnr] = A, exp g (z fl fün + (pp)}, p = 1,2 (s) where A, and A2 are the real-estimated arnplits, Ap> O, p = 1, 2 (cpl, (pz) are the initial phases, and fo is the normalized frequency. .-. .tuvvs f. .- iu 1 n. »H» Q ii ~. -. .v. -. 1. v -. st _ v 1 ii.. .n 3 If the additional noise is white Gaussian noise MLE for the relative phase xp = cp, = (p, dcn maximum probable estimate of the frequency. As for the frequency estimate, an exact solution requires an infinite number of arithmetic operations.

An estimate of low complexity (with a complexity z N) is as follows. êf = Aili <9) (10) where * denotes a complex conjugate and where ¿[z] denotes the phase angle of the scaler z with complex quantities. The cross-correlation at (10) requires 4N (real values) multiplications and 2N (real values) additions. The phase angle calculation can be performed by a table lookup with (the phase and the quadrature part of) x, [n] and x2 [n] which is quantized by b bits.

From a theoretical estimation point of view, MLE is the preferred method for estimating physical parameters of analog signals based on digital data. In addition to the fact that it may be difficult or even impossible to derive the MLE, this estimate requires an infinite number of calculations to arrive at the resulting estimate. All solutions of practical interest set requirements regarding the number of arithmetic calculations. Especially in applications such as communication, measurement technology and signal processing, this refers to high sample rates (typically FS in the Gigahertz area) in combination with requirements for real-time processing.

Practical estimation methods in the prior art with a numerical complexity proportional to the size of the sample set have been described using the two examples. The problems in known solutions are of two kinds: v Their complexity is still too great for the applications that need them. Alternatively, they are too expensive (in terms of silicon surface, price, requirements for analog or digital pre-processing of data, etc.). 0 Their performance (in static sense) is poor. This means that the purpose of reducing the numerical complexity has led to an algorithm which is not able to solve the problem which requires certain specifications with respect to the accuracy of the estimation.

SUMMARY OF THE INVENTION The present invention thus has for its object to propose a method and an apparatus for estimating physical parameters in a digital data sequence, in particular one obtained by analog-to-digital conversion of an analog signal, which are simple and inexpensive compared with previously known solutions and yet exhibits high performance.

This is achieved by the present invention by a signal processing device for determining at least one parameter of a signal comprising: a shift register arranged to receive a quantized digital signal with a number of bits corresponding to the number of bits of the quantized digital signal, the shift register being arranged to temporarily store a number of bits corresponding to the number of bits in a number N samples of the quantized digital signal, 0 memory means (comprising at least one look-up table comprising values which can be used to determine the at least one parameter, and 0 address means for determining at least one address of the memory means to be read, depending on the contents of the shift register.

The object is also achieved according to the invention by a method for determining at least one parameter of an input signal, comprising the steps consisting of: 0 writing a quantized signal in a shift register which is arranged to temporarily store a number of bits corresponding to the number of bits in a number of N samples. of the quantized digital signal; 0 read at least one bit from the shift register; 0 read a value from at least one address in the memory unit depending on at least one bit read from the shift register.

The device and method according to the invention can be carried out entirely in hardware and thus be used at very high sampling frequencies with typical applications such as measuring systems and radio systems (mobile telephony, etc.). They can also be fully implemented by software at an extremely low cost with respect to the operations. In its most extreme form, the estimate does not require any calculations but only a memory access. This is suitable for applications such as voice processing (eg to find the speaker's fundamental frequency in voice coding applications such as IP telephony (with Internet protocol) and mobile telephony).

The signal processing device preferably further comprises a quantizer which is arranged to receive an input signal to be quantized, and is provided with at least one input and at least one digital output, the output forming the quantized digital signal which is input to the shift register. If the input to the quantizer is analog, the quantizer must also perform an analog-to-digital conversion. As an alternative, an analog-to-digital converter can be provided for the quantizer.

In a preferred embodiment, the quantizer is a one-bit quantizer. This is particularly suitable for applications requiring high sample rates, at which high-resolution analog-to-digital conversion and quantization may be impossible, or economically gain control before the analog-to-digital converter. The one-bit quantization is very simple and unworkable. If a one-bit quantization is used, no one is required to perform it, which means that it is often used for eg sigma-delta modulators.

Preferably, the address means comprises a first processor arranged between the shift register and the memory unit, for processing the output signal from the shift register before it is used to address at least one table input of the memory unit. This enables, for example, a simplification of the address found in the shift register, or the calculation of more than one address based on a single shift register entry.

The signal processing device may further comprise a second processor which is arranged to calculate an estimate of at least one physical parameter based on the at least one addressed table input of the memory unit.

The writing of data and reading of addresses from the shift register, respectively, can be controlled by a first clock generating means arranged to output a first clock signal which controls the input of data to the shift register and a second clock generating means arranged to output a second clock signal which controls the output of data from the shift register.

A preferred way of training the memory unit before it is used to determine the parameters from signals is as follows: a) Generating a parameter value for at least one parameter relevant to the input signal; b) Generating a signal representing the generated parameter values; c) Determining at least one address obtainable from the shift register resulting from the input of the generated signal; Repeat steps a), b) and c) a sufficient number of times to obtain a representative number of values. d) Determining, for each shift register address, an appropriate memory input value based on sets of parameter values associated with said shift register address as determined by steps a), b) and c); e) Input, for each memory unit, of the value determined in step d) in the memory at the location corresponding to the associated shift register address.

The situation described is based in particular on a new methodology for designing estimates. An important feature of this methodology is that the quantization in analog-digital conversion of analog signals is taken into account in the design of the estimate.

This method has greater advantages over the known solutions which require explicit knowledge of the memory inputs, when look-up tables are used to approximate a function description with the form g (x) = arccos (x), g (z) = ¿[z], etc., while the present invention does not do this.

Brief Description of the Figures The invention is further described in more detail, by means of embodiments which serve only by way of example and with reference to the accompanying drawings, in which: Figure 1 is a general illustration of an electronic circuit according to the invention; Figure 2 shows an example of frequency estimation through the circulation table procedure; Figure 3 shows how two 4-bit inputs to the first processor can be designed according to the invention; and 10 15 20 25 30 35 520 oe7§q $, wy§ +; Figure 4 is a fate diagram showing how a training sequence can be used to determine the table entries according to the invention.

Detailed Description of Preferred Embodiments A general embodiment of the device according to the invention is shown in Figure 1.

The device comprises an analog-to-digital (A / D) converter 1 which receives one or fl your analog inputs and which transmits one or fl your digital outputs. The input signal can originate from a single sensor or from your sensors. If the input signal originates from a number of 0 sensors, the analog-to-digital converter 1 quantizes the signal from each sensor by bk bits, k = 0, ..., O-1.

The output signal or outputs from the analog-to-digital converter 1 are fed to a K-bit shift register 3 where a binary temporary storage of binary information takes place which represents a sequence of samples from the digital output of said analog-to-digital converter 1. With a number of 0 digital outputs from said analog-digital converter. analog-to-digital converter 1, where each output is represented by bk bits for k = 0, ..., = 0-1, the total number of bits K in the shift register 3 is K = N 0-1 'zbk which stores binary information which represents N sample of the digital k = 0 output from said analog-to-digital converter 1. In the case of a number of 0 outputs from the analog-to-digital converter, it is not necessary to shift N samples from each output of said analog-to-digital converter in the shift register 3. We can use a different number of samples for each channel, eg nk for k = 0, ..., O = -1, which means the use of a shift register 0-1 with the total number of bits Enkbk, which represents nk samples of names da digital output k = 0 from each channel of said analog-to-digital converter.

From the shift register 3 the signal or signals are fed to a first processor 5 which is arranged to calculate one or more output signals which form addresses. The addresses are integers represented by a given number of bits used as pointers for one or more of your memory units 7. The number of outputs from the first processor 5 may be less than the number of inputs.

The first processor 5 includes binary operations ("and", "or", "exclusive or", "neither or"), counters, and the arithmetic operations "+", "-", "*", "/". The first processor has the task of calculating one or fl your addresses for the upcoming memory access. This can be done, for example, in one of the following ways: 0 A simple example is obtained by calculating the address according to equation (13). In a mathematical description such as (13), we represent binary data with +1 and -1. In an electronic circuit, of course, a representation with ones and zeros is used, for example with a 10-bit shift register whose content 1100011100 = 796 (in decimal representation) points to the 796th memory input. With a 10-bit address bus, 1024 different memory locations can be addressed. In this example, there is no first processor. Another simple example is described in more detail in the next section. Many short addresses are formed by the sequence in the same manner as above. It is known that the correlations contain information about the frequency, as well as other physical parameters. See, for example, the known estimate in equation (5). In equation (5), the information in data x [n] has been fused to the three correlations r [1], r [2] and r [3]. The estimate is then made by (5). With the present invention we can form arbitrary correlations of eg binary data and use them (directly or after certain calculations) to address the memories.

Each memory input address unit 7 contains a pre-calculated table 9.

Each output from the first processor 5 is fed into one of these tables 9.

If required, a second processor 11 calculates an estimate of one or more of the physical parameters of said analog input to the analog-to-digital converter 1 from memory data addressed in accordance with the outputs of the first processor 1. The output or outputs of the second processor 11 therefore describe a or fl your physical parameters of the input signal to the analog-to-digital converter l. If the value or values read from the memory units directly correspond to the parameters to be estimated, the other processor is of course not needed. The second processor ll may include arithmetic operations "+", "-", "*", "l /", and delay elements and elements such as min () and max (). The operations to be performed by the second processor depend on the type of value or values read from the memory unit and the type of parameter desired.A simple example may involve calculating an average value of two or fl your values read from different memory units, or fl your values read from a single memory unit at different times, to obtain Another example might be to process a value corresponding to the frequency of the signal to obtain a value for the period of the signal, or vice versa.

A first clock generating means 13 first generates a clock signal having a frequency FS which is used for clocking the analog-to-digital converter 1, the shift register 3 and the first processor 5. A second clock generating means 15 generates a second clock signal having a lower frequency than FS. For example, the frequency FS / N can be used for clocking the memory units 7 and the second processor 11. In this way, N sets of input data form the Q addresses of the memory units 7 before all values in the memory units 7 are read from the memory units 7.

Of course, if the input signal is digital, the analog-to-digital converter 1 is not needed. If the digital input signal requires further quantization, a quantizer must be used instead of the analog-to-digital converter and otherwise the input signal can be fed directly to the shift register 3.

In a preferred embodiment, the analog-to-digital converter 1 has the same number of analog inputs and digital outputs, each output being represented by b bits (where b S 4).

The table inputs in the memory units 7 have been selected as the conditional wait values on parameters based on given digital data, ie that the mean square error is minimized (MMSE).

The table entries can be calculated by training, for example, according to what is mentioned below in connection with Figure 4. 10 15 20 25 30 35 520 067. 8 An indirect method for calculating the conditional expectation of parameters based on given digital data, but also alternative design criteria other than the MMSE criterion may be relevant, eg the method for maximum probability (MLE) or the method for maximum a posteriori (MAP).

The use of the maximum probability criterion to specify how the inputs of the memory units are determined in connection with at least one parameter for said input signal can be summarized as follows: let ip denote the address of the memory unit no. P, the contents of said memory unit at the memory location ip i is determined by the parameter (s) of the input signal that p, maximizes the conditional probability that ip will be observed as the address of memory unit no. p, which depends on the value (s) of the parameter (s).

The maximum a posteriori criterion for specifying how the inputs to the memory units are determined in connection with at least one parameter for said input signal includes in short, if it is assumed that ip denotes the address of memory unit no. of memory addresses ip, is determined by the parameter (s) of the input signal that maximizes the conditional probability density function for said parameter (s), with the condition that the address of memory unit no. p has the value ip.

We now consider the signal model given in equation (2). Our purpose is to devise an estimate, let's say f, which strives to estimate the true value fo for the unknown frequency, based on a block of observed data according to (l). We use the assumption that before data is processed by the estimate, the observations x [n] are quantized to form a binary sequence according to ylnl = Signülnl) (11) where sign (x) = 1 for x20 and sing (x) = - l for x < 0. Our aim is then to find an estimate f: {i1} N -> ÉR, which works with observed and quantized data {y [01 ylN - Ill (12) that is optimal with respect to the minimum mean square error (MMSE). An important observation is that due to the quantization, the number of possible sequences that can be observed through the estimation is finite. More specifically, we can notice that a specially observed sequence according to (12) with the length N corresponds to only an integer ie {0,1, ..., M -1}, where M = 2N, where the mapping from an observed sequence to index (or address) i can be selected SOm 10 15 20 25 30 35 t .. .-. a. i ».. _. _ = - i. i u. n. t; in; »N i. | n i i in .i n v. o. v »1 i + - ~ 1. - _ - «> lt ._- = EN" lllnlg ", = 0 2 (13) Since observed data have a finite resolution, only a finite number of possible estimation results can be found. Thus, without loss of the general character, all possible frequency estimates based on a sequence of quantized data as in (12) are entered in two steps: first by determining the index in which corresponds to the observed sequence according to (13), and then using this index as a pointer for the table: (14) (f (o), f (1), (M -1)} which contains all possible frequency ratings that can be obtained by estimating.

The design of the best frequency estimate then corresponds to the structure of the table (14). In the MMSE criterion, the table inputs should be selected as (15) where a conditional expectation can be calculated assuming that a previous distribution of the unknown frequency is known. Once the table has been calculated and stored, the operation of the new frequency estimate by a table lookup treatment can be illustrated as in Figure 2, which corresponds to a special case of the procedure described in connection with Figure 1.

Figure 2 shows a simpler version of the device in Figure 1, where it is assumed that a single quantized digital signal is present and that a single memory unit is used. In this version, a quantizer 1 'receives an input signal. As in Figure 1, the quantizer can also perform an analog-to-digital conversion, or it may not be needed at all, if the input signal is a quantized digital signal. The quantized signal is input to a shift register 3, and at regular intervals the contents of the shift register are used to address a memory unit 7 in the same way as in Figure 1. Due to the simplicity of this embodiment, neither a first processor nor a very simple one is required. The binary address read from the shift register 3 is used directly to address the memory unit 7. The value read from the memory unit 7 according to the address can be used as it is or processed in a second processor similar to that in fi gur 1 (not shown in fi gur 2).

As in Figure 1, the quantizer 1 'and the shift register 3 are controlled by a first clock signal and a second clock signal controls the reading of the address used to address the memory unit from the shift register 3. The frequency of the clock signals is mentioned in connection with Figure 1. In this case 10 15 20 25 30 35 520 067, 10, the frequency FO / N may be suitable for the second clock signal.

If the sequence with N bits is long, it may be desirable to shorten the sequence before using it as an address, in order to avoid the need for a very large memory unit. One way to do this is shown in Figure 3, which illustrates a 10-bit shift register. Only a number of bits, in this case four, of the ten bits stored in the shift register are selected. The bits can be at regular or irregular distances from each other. The selected bits are then used to address the memory unit or units. In Figure 3, two four-bit sequences are selected, the first sequence comprising the first, second, third and last bits and the second sequence comprising the third, fourth, sixth and eighth bits. These two four-bit sequences can be used as they are, as two binary addresses to address the memory units directly, or they can be fed into the first processor and processed to form one or more of your addresses.

The stored table is designated according to the criterion MMSE, ie that the table entries are determined according to equation (15).

Figure 4 shows an uncomplicated method for determining the table entries for the tables 9 in Figure 1. One way of determining the table entries is to use a training sequence T = (ik j ;, where each ik corresponds to a particular block of length N of quantized data.

A general training method is shown in Figure 4: Step S1: Determine the parameter or parameters that are relevant for the signal in question. For a signal x (n) given by the equation (2), the parameter that should be obtainable from the memory can, for example, be the frequency. Relevant parameters used during training may include, for certain waveforms such as sine waves, triangle waves and square waves, the amplitude (A), the frequency (f) and the initial phase (tp). Other parameters such as noise effect can also be considered. For other types of signals, other parameter sets may be relevant. For example, a pure DC signal can be characterized by a level. Several different Detenninist waveforms, such as the sum of sine waves, your frequencies, phases, etc. can be identified. In stochastic road forms such as white noise or colored noise, parameters such as mean, covariance or higher order elements may be the desired parameters. Normally the signal is described by a mixture of detenninist and stochastic waveforms as shown in equations (2) and (7).

Generate a parameter value for each of the parameters. This can be done well known Step S2: randomly eg within certain limits or according to a distribution function such as a Gaussian curve.

Step S3: Step S4: Generate a signal that has the parameter values generated during step S2.

Determine the address in the shift register that results from the input of the signal generated during step S3. This can be conveniently done by generating the signal and inputting it into the shift register, then reading the contents of the shift register, in the same manner as this is done for a signal to be tested later. The same kind of quantizer and first processor should be used, which performs the same functions as those used when testing signals.

Steps S2-S4 are repeated the number of times sufficient to obtain a representative number of values. The number of times needed depends, for example, on the number of parameters and the size of the memory or memories.

This procedure results in a large number of shift register addresses, each of which is associated with a set of parameter values. Each shift register address points to an input inside.

Step S5: For each shift register address: determine an appropriate table entry value based on the set of parameter values associated with this shift register address.

Step S6: For each table entry: enter the value determined during step S5 in the memory at the location corresponding to the associated shift register address.

The result of this method will be a memory comprising a number of inputs, each of which is addressed by a single shift register address.

With respect to step S5, the appropriate memory input can be determined in various ways.

If there was only one set of parameter values associated with the shift register address, the value of the desired parameter or parameters can be entered directly. If there is more than one set of parameter values associated with the shift register address, the memory input should be calculated based on all these sets of values. This can be done as mentioned above using the MMSE method, using the equation (15), the MAP method or the MLE method.

The compromise between accuracy and computational complexity can be adjusted by an appropriate choice of the P multibitin feeds to the first processor (see Figure 1).

In particular, the irregularities illustrated in Figure 3 can be used to provide high performance.

Such irregularity schemes are favorable from an estimation theoretical point of view, but make FFT treatment and treatment using other known methods impossible.

Claims (13)

10 15 20 25 30 35 520 057 14 1A. Patent claims A signal processing device for determining at least one parameter of a signal, the parameter having a non-linear dependence on the signal, comprising: 0 a shift register (3) arranged to receive a quantized digital signal having a number of bits corresponding to the number of bits of the quantized digital signal, the shift register being arranged to temporarily store a number of bits corresponding to the number of bits in a number N samples of the quantized digital signal, v memory means (7) comprising at least one look-up table (9) comprising values which can be used to determining said at least one parameter, the values being selected as conditional wait values of the parameter with respect to the digital input signal, and 0 address means for determining at least one address of the memory means (7) to be read, depending on the contents of the shift register (3). The signal processing apparatus according to claim 1, further comprising a quantizer (1; 1 ') arranged to receive an input signal to be quantized, and provided with at least one input and at least one digital output, the output forming the quantized the digital signal input to the shift register. The signal processing device according to claim 2, wherein the input to the quantizer (1; 1 ') is analog and the quantizer also performs an analog-to-digital conversion. The signal processing device according to claim 2 or 3, wherein the quantizer is a one-bit quantizer. A signal processing device according to any one of the preceding claims, wherein the address means comprises a first processor (5) arranged between the shift register (3) and the memory unit (7), for processing the output signal from the shift register before it is used to address at least one table entry of the memory unit. A signal processing device according to any one of the preceding claims, which further comprises a second processor arranged to calculate an estimate of at least one physical parameter from said at least one addressed table unit of the memory unit. A signal processing device according to any one of the preceding claims, further comprising a clock generating means (13) arranged to output a first clock signal controlling the input of data to the shift register and a second clock generating means (15) arranged to output a second clock signal which controls the output of data from the shift register. A method for determining at least one parameter of an input signal, the parameter having a non-linear dependence on the signal, comprising the steps of: writing a quantized signal in a shift register arranged to temporarily store a number of bits corresponding to the number of bits in a number N of samples of the quantized digital signal; read at least one bit from the shift register; read a value from at least one address, which relates to conditional wait values of the parameter with respect to the digital input signal, in a memory unit depending on at least one 10 15 25 520 057 _ħ ¥ * GET 2, ... b) bit read from the shift register. The method of claim 8, further comprising a step of receiving the input signal and quantizing it to output the quantized digital signal. ' The method of claim 8 or 9, further comprising a step of analog-to-digital conversion of the input signal prior to quantizing it. 11. ll. A method according to any one of claims 8 to 10, further comprising a step of processing said at least one bit read from the shift register to determine the address in the memory unit. A method according to any one of claims 8 to 11, further comprising a step of processing said at least one value read from said at least one memory to obtain the parameter of the input signal. A method according to any one of claims 8 to 12, further comprising the following steps, performed before writing the quantized digital signal in the shift register 1 a) Generating a parameter value for at least one parameter relevant to the input signal; b) Generating a signal representing the generated parameter values; c) Determining at least one address obtainable from the shift register resulting from the input of the generated signal; Repeat steps a), b) and c) a sufficient number of times to obtain a representative number of values. d) Determining, for each shift register address, an appropriate memory input value based on sets of parameter values associated with said shift register address as determined by steps a), b) and c); e) Input, for each memory unit, of the value determined in step d) in the memory at the location corresponding to the associated shift register address.