WO2002019434A1 - Trench igbt - Google Patents

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Publication number
WO2002019434A1
WO2002019434A1 PCT/EP2000/008459 EP0008459W WO0219434A1 WO 2002019434 A1 WO2002019434 A1 WO 2002019434A1 EP 0008459 W EP0008459 W EP 0008459W WO 0219434 A1 WO0219434 A1 WO 0219434A1
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WIPO (PCT)
Prior art keywords
trench
zone
trench igbt
igbt according
insulating layer
Prior art date
Application number
PCT/EP2000/008459
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German (de)
French (fr)
Inventor
Frank Pfirsch
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Infineon Technologies Ag
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Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Priority to PCT/EP2000/008459 priority Critical patent/WO2002019434A1/en
Priority to DE10085054T priority patent/DE10085054B4/en
Priority to AU2000274149A priority patent/AU2000274149A1/en
Publication of WO2002019434A1 publication Critical patent/WO2002019434A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Definitions

  • IEGT Injection Enhanced Gated Transistor
  • the reaction capacitance which is also referred to as miller capacitance and is based on the capacitance formed by the gate oxide, has a significant influence on the on and off behavior of the IGBT and on its stability in the event of a short circuit.
  • a high feedback capacity leads to longer switching operations and thus increased switching losses.
  • an capacitance which is negative in effect can even arise, which leads to unstable behavior, namely in particular a tendency to oscillate and an uncontrollable gate voltage and current rise (cf. I. O ura et al .: IGBT Negative Gate Capacity and Related Instability Effects, IEEE Electron device Letters, Vol. 18, No. 12, 1997, pp.
  • the gate oxide area adjacent to an n-doped base is large, which also leads to a very large reaction capacity. 1
  • the basic structure of such a trench IGBT is shown in FIG. 6:
  • a semiconductor body has a p-type collector zone 5 1, on which a first n-type base zone 2 and a second p-type base zone 3 are provided in succession.
  • An n-type emitter zone 4 is embedded in the p-type base zone 3.
  • two IGBT cells are shown, so that, correspondingly, two EMIT 0 terzonen 4 are available.
  • the emitter zones 4 and the p-type base zone 3 are penetrated by trenches 5, 6 which extend into the n-type base zone 2. These trenches 5, 6 are lined with E - > an insulating layer 7, which acts as a gate oxide and is made of, for example, silicon dioxide.
  • the interior of the trenches 5, 6 is filled with a conductive material 8, such as in particular doped polycrystalline silicon, which forms a gate electrode.
  • This Gateelektro0 de 8 is covered on a main surface 9 of the semiconductor body with an insulating layer 10 made of, for example, silicon dioxide and / or silicon nitride, so that the conductive material 8 is electrically separated from a metallization serving as an emitter contact 11. 5
  • a collector contact 13 is also located on the other main surface 12 of the semiconductor body opposite the main surface 9.
  • IEGTs for which examples are shown in FIGS. 7, 8 and 9, are particularly suitable for higher reverse voltages.
  • the distance is between two Cells expanded by an additional trench 14 without an emitter zone, while in the examples of FIGS. 8 and 9 there is a relatively wide p-type zone 15 between the corresponding two cells.
  • the conductive materials 8 in trenches 5, 6 of the two adjacent cells are connected to one another by a metallization 16.
  • the basic principle common to the IEGTs of FIGS. 7 to 9 is that only a relatively narrow current path is available to the holes flowing via the p-type base zone 3 as the body region to the emitter contact 11 forming a front-side metallization, so that sets a high hole current density and thus a high charge carrier gradient below these body areas.
  • This high charge carrier gradient results in a strong charge carrier flooding in the n-type base zone 2, which is less doped with respect to the base zone 3.
  • the voltage drop in the n-type base zone determines the forward voltage of the IEGT as a whole, especially in the case of a large layer thickness of the n-type base zone 2, that is to say with higher blocking IEGTs, it is possible in this way despite the resistance which the holes in the narrow area have Current path in the p-type base zone 3 is opposed, reduce the forward voltage of the IEGT. .
  • This narrow current path is, as shown in the examples of FIGS. Is seen to 9 "1, produced in that the individual trench IEGT cells are not directly adjacent, but have a certain distance between them which by the additional trench 14 or the wide p-type zone 15 is formed.
  • IEGTs of the type described above are known for example from US 5 329 142, US 5 448 083, US 5 585 651 and GB-A-2314206.
  • a disadvantage of these known IEGTs or IGBTs is the large feedback capacity, which is a consequence of the large gate oxide area which is not required for a MOS channel, which in turn is due to the large distance between the cells.
  • a trench IGBT is proposed in the already mentioned DE-A1 196 51 108, in which the electrode arranged in the inactive trench (see trench 14 in FIG. 7) does not connect to the gate potential, but to the potential of the emitter contact or the front is connected.
  • a disadvantage of such a structure is that a large part of the conductive material in the trenches, for example half of the polycrystalline silicon, is not available for the conductivity of the gate electrode, which increases the effective gate resistance.
  • the insulating layer acts as a gate insulating film (or gate oxide) only in the area necessary for the functionality of the MOS channel. This means that the gate oxide area is limited to the area required for the functionality of the MOS channel.
  • a thicker insulating layer in which an active MOS channel is' present on only one side of the trench, a thicker insulating layer, the entire inactive side of the trench, and optionally also a portion occupied by the upper side thereof, while only in the area of the active MOS channel, that is to say in the area of the second base zone, a thin gate insulating film is provided instead of the thicker insulating layer *.
  • the reaction capacity can be reduced to half, for example.
  • the trench IGBT according to the invention can be produced in a particularly advantageous manner by means of the method described in the aforementioned DE-Al-199 35 442, in which at least one trench is made in a semiconductor body, which is then separated from the inner surface of the trench by an insulating layer managerial tendency material is at least partially filled, wherein the insulating layer is introduced into the trench so that it is provided in the region of the lower end of the trench with a greater layer thickness than at the upper end.
  • This method has in particular the following process steps:
  • 1 to 5 are sectional views for explaining various embodiments of the IGBT and
  • the following exemplary embodiments relate to an IGBT with an n-type emitter zone to explain the prior art. Although this is the preferred conduction type for the emitter zone, the invention can in principle also be applied to a trench IGBT in which the emitter zone is p-type.
  • FIG. 1 shows a first exemplary embodiment of the trench IGBT according to the invention, which differs from the conventional trench IGBT according to FIG. 6 in that the insulating layer 7 is formed as thick oxide 17 in the lower regions of the trench 5, 6 is while in Area of the active MOS channel, ie in the area of the p-type base zone 3, forms a thin gate oxide film.
  • the reaction capacitance is not insignificantly reduced by the thick oxide 17, while the gate oxide film with a small layer thickness is only present in the area necessary for the functionality of the MOS channel.
  • the structure shown in FIG. 1 with the thick oxide 17 in the lower region of the trenches 5, 6 can easily be produced by the method explained above using the method steps (a) to (g).
  • a photoresist can be used for the auxiliary layer mentioned therein, while silicon nitride and / or silicon dioxide are advantageous for the insulating films.
  • the exemplary embodiments of FIGS. 2 to 5 are more advantageous than the exemplary embodiment of FIG. 1.
  • the active MOS channel is provided only on one side of the trench, while in the exemplary embodiment the 5, the distance between two cells of the IGBT is widened by the p-type zone 15.
  • FIG. 2 shows an exemplary embodiment (IEGT) in which, similar to the existing IGBT from FIG. 7, an additional trench 17 without an active MOS channel is provided between two IGBT cells, thereby increasing the distance between these cells to expand.
  • this additional trench 14 has a thick oxide 17, which is also formed in the trenches 5, 6 of the two IGBT cells, with the exception of the region of the active MOS channel.
  • the insulating layer 7 is provided as a gate oxide film with a much smaller layer thickness than the thick oxide 17.
  • the insulation as thick oxide 17 In all areas of trenches 5, 6 and 14, with the exception of the areas of the active MOS channels, the feedback capacity can be greatly reduced.
  • FIG. 3 shows a further exemplary embodiment of the trench IGBT (IEGT) according to the invention, in which, instead of the trench 14 without an active MOS channel in accordance with the conventional IGBT of FIG. 8, a relatively wide p-conducting zone 15 is arranged between the two IGBT cells is. Otherwise, the trenches 5, 6 in this exemplary embodiment are designed in a similar manner to the exemplary embodiment in FIG. 2.
  • IEGT trench IGBT
  • FIG. 4 shows a further exemplary embodiment of the invention, in which the conductive materials 8 (polycrystalline silicon) of the trenches 6 of the two cells are connected to one another via a conductive connection 16 in accordance with the conventional IGBT from FIG. 9.
  • a connection is also provided in the exemplary embodiment in FIG. 5, in which, in contrast to the exemplary embodiment in FIG. 4, the trenches 5, 6 are provided on both sides with the insulating layer 7 as a gate oxide film at their lower end.
  • the layer thickness of the thick oxide 17 is preferably at least twice the layer thickness of the gate oxide film 7.

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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

The invention relates to a trench IGBT. In order to reduce the reaction capacity, the trench is lined, solely in the area of the active MOS canal with a gate oxide film (7) and an insulating layer (17) which has an increased density in comparison with the gate oxide film (7).

Description

Beschreibungdescription
Trench-IGBTTrench IGBT
Die Erfindung betrifft einen Trench-IGBT (IGBT = Bipolartransistor mit isoliertem Gate) nach dem Oberbegriff des Patentanspruches 1. Unter einem IGBT soll dabei und im folgenden auch ein sogenannter IEGT (IEGT = Injection Enhanced Gated Transistor) verstanden werden. Auf den Aufbau eines IEGTs, der eine besonders für höhere Sperrspannungen vorteilhafte Variante eines IGBTs darstellt, wird weiter unten näher eingegangen werden.The invention relates to a trench IGBT (IGBT = bipolar transistor with insulated gate) according to the preamble of claim 1. An IGBT is to be understood here and in the following also a so-called IEGT (IEGT = Injection Enhanced Gated Transistor). The construction of an IEGT, which is a variant of an IGBT that is particularly advantageous for higher reverse voltages, will be discussed in more detail below.
Bei IGBTs hat die Rückwirkungskapazität, die auch als Millerkapazität bezeichnet wird und auf der durch das Gateoxid gebildeten Kapazität beruht, einen wesentlichen Einfluß auf das Ein- und Ausschaltverhalten des IGBTs sowie auf dessen Stabilität im Kurzschlußfall. Eine hohe Rückwirkungskapazität führt nämlich zu längeren Schaltvorgängen und damit erhöhten Schaltverlusten. Im Kurzschlußfall des IGBTs kann sogar eine im Effekt negative Kapazität entstehen, die zu einem instabilen Verhalten, nämlich insbesondere einer Schwingungsneigung und einem unkontrollierbaren Gatespannungs- und Stromanstieg führt (vgl. hierzu I. O ura et al.: IGBT Negative Gate Capaci- tance and Related Instability Effects, IEEE Electron de- vice Letters, Vol. 18, No. 12, 1997, S. 622-624, und I. Omura et al.: Oscillation Effects in IGBT 's Related to Negative Capacitance Phenomena, IEEE Transaction on Electron Devices, Vol. 46, No. 1, 1999, S. 237-244).In the case of IGBTs, the reaction capacitance, which is also referred to as miller capacitance and is based on the capacitance formed by the gate oxide, has a significant influence on the on and off behavior of the IGBT and on its stability in the event of a short circuit. A high feedback capacity leads to longer switching operations and thus increased switching losses. In the event of a short circuit of the IGBT, an capacitance which is negative in effect can even arise, which leads to unstable behavior, namely in particular a tendency to oscillate and an uncontrollable gate voltage and current rise (cf. I. O ura et al .: IGBT Negative Gate Capacity and Related Instability Effects, IEEE Electron device Letters, Vol. 18, No. 12, 1997, pp. 622-624, and I. Omura et al .: Oscillation Effects in IGBT's Related to Negative Capacitance Phenomena, IEEE Transaction on Electron Devices, Vol. 46, No. 1, 1999, pp. 237-244).
Bei vielen Ausführungsformen von Trench-IGBTs und vor allem bei Trench-IGBTs, die für höhere Spannungen ab etwa 1200 V eingesetzt werden sollen, ist die an eine n- dotierte Basis angrenzende Gateoxidfläche groß, was zu einer ebenfalls sehr großen Rückwirkungskapazität führt. 1 Die Grundstruktur eines derartigen Trench-IGBTs ist in Fig. 6 gezeigt:In many embodiments of trench IGBTs and especially trench IGBTs that are to be used for higher voltages from about 1200 V, the gate oxide area adjacent to an n-doped base is large, which also leads to a very large reaction capacity. 1 The basic structure of such a trench IGBT is shown in FIG. 6:
Ein Halbleiterkörper weist eine p-leitende Kollektorzone 5 1 auf, auf der nacheinander eine erste n-leitende Basiszone 2 und eine zweite p-leitende Basiszone 3 vorgesehen sind. In die p-leitende Basiszone 3 ist eine n-leitende Emitterzone 4 eingebettet. Im vorliegenden Beispiel sind zwei IGBT-Zellen gezeigt, so daß entsprechend zwei Emit- 0 terzonen 4 vorhanden sind.A semiconductor body has a p-type collector zone 5 1, on which a first n-type base zone 2 and a second p-type base zone 3 are provided in succession. An n-type emitter zone 4 is embedded in the p-type base zone 3. In the present example, two IGBT cells are shown, so that, correspondingly, two EMIT 0 terzonen 4 are available.
Die Emitterzonen 4 und die p-leitende Basiszone 3 werden durch Trenches 5, 6 durchsetzt, die bis in die n-leitende Ba-siszone 2 reichen. Diese Trenches 5, 6 sind mit E-> einer als Gateoxid wirkenden Isolierschicht 7 aus beispielsweise Sili-ziumdioxid ausgekleidet. Das Innere der Trenches 5, 6 ist mit einem leitenden Material 8, wie insbesondere dotiertem polykristallinem Silizium, gefüllt, das eine Gateelektrode bildet. Diese Gateelektro0 de 8 ist auf einer Hauptoberfläche 9 des Halbleiterkörpers mit einer Isolierschicht 10 aus beispielsweise Siliziumdioxid und/oder Siliziumnitrid abgedeckt, so daß das leitende Material 8 von einer als Emitterkontakt 11 dienenden Metallisierung elektrisch getrennt ist. 5The emitter zones 4 and the p-type base zone 3 are penetrated by trenches 5, 6 which extend into the n-type base zone 2. These trenches 5, 6 are lined with E - > an insulating layer 7, which acts as a gate oxide and is made of, for example, silicon dioxide. The interior of the trenches 5, 6 is filled with a conductive material 8, such as in particular doped polycrystalline silicon, which forms a gate electrode. This Gateelektro0 de 8 is covered on a main surface 9 of the semiconductor body with an insulating layer 10 made of, for example, silicon dioxide and / or silicon nitride, so that the conductive material 8 is electrically separated from a metallization serving as an emitter contact 11. 5
Auf der der Hauptoberfläche 9 gegenüberliegenden anderen Hauptoberfläche 12 des Halbleiterkörpers befindet sich noch ein Kollektorkontakt 13.A collector contact 13 is also located on the other main surface 12 of the semiconductor body opposite the main surface 9.
0 Ähnliche IGBTs und deren Funktionsweise sind beispielsweise in EP-A2-847 090 und DE-Al-196 51 108 beschrieben.Similar IGBTs and their mode of operation are described, for example, in EP-A2-847 090 and DE-Al-196 51 108.
Für höhere Sperrspannungen sind wie bereits erwähnt wurde, besonders IEGTs geeignet, für die Beispiele in den 5 Fig. 7, 8 und 9 gezeigt sind.As already mentioned, IEGTs, for which examples are shown in FIGS. 7, 8 and 9, are particularly suitable for higher reverse voltages.
Im Beispiel von Fig. 7 ist der Abstand zwischen zwei Zellen durch einen zusätzlichen Trench 14 ohne Emitterzone erweitert, während in den Beispielen von Fig. 8 und 9 zwischen den entsprechenden beiden Zellen eine relativ breite p-leitende Zone 15 gelegen ist. Im Beispiel von Fig. 9 sind zusätzlich zum Beispiel von Fig. 8 noch die leitenden Materialien 8 in Trenches 5, 6 der beiden benachbarten Zellen durch eine Metallisierung 16 miteinander verbunden.In the example of Fig. 7, the distance is between two Cells expanded by an additional trench 14 without an emitter zone, while in the examples of FIGS. 8 and 9 there is a relatively wide p-type zone 15 between the corresponding two cells. In the example of FIG. 9, in addition to the example of FIG. 8, the conductive materials 8 in trenches 5, 6 of the two adjacent cells are connected to one another by a metallization 16.
Den IEGTs der Fig. 7 bis 9 ist als Grundprinzip gemeinsam, daß den über die p-leitende Basiszone 3 als Bodyge- biet zu dem eine Vorderseitenmetallisierung bildenden ' Emitterkontakt 11 abfließenden Löchern nur ein relativ schmaler Strompfad zur Verfügung steht, so daß sich un- terhalb dieser Bodygebiete eine hohe Löcherstromdichte und damit ein hoher Ladungsträgergradient einstellt. Dieser hohe Ladungsträgergradient hat eine starke Ladungsträgerüberschwemmung in der bezüglich der Basiszone 3 schwächer dotierten, n-leitenden Basiszone 2 zur Fol- ge. Da vor allem bei einer großen Schichtdicke der n- leitenden Basiszone 2, also bei höher sperrenden IEGTs, der Spannungsabfall in der n-leitenden Basiszone die Durchlaßspannung des IEGTs insgesamt bestimmt, läßt sich auf diese Weise trotz des Widerstands, der den Löchern in dem schmalen Strompfad in der p-leitenden Basiszone 3 entgegengesetzt wird, die Durchlaßspannung des IEGTs verringern. .Dieser schmale Strompfad wird, wie aus den Beispielen der Fig. "1 bis 9 zu ersehen ist, dadurch erzeugt, daß die einzelnen Trench-IEGT-Zellen nicht direkt benachbart sind, sondern zwischen sich einen bestimmten Abstand aufweisen, der durch den zusätzlichen Trench 14 oder die breite p-leitende Zone 15 gebildet ist.The basic principle common to the IEGTs of FIGS. 7 to 9 is that only a relatively narrow current path is available to the holes flowing via the p-type base zone 3 as the body region to the emitter contact 11 forming a front-side metallization, so that sets a high hole current density and thus a high charge carrier gradient below these body areas. This high charge carrier gradient results in a strong charge carrier flooding in the n-type base zone 2, which is less doped with respect to the base zone 3. Since the voltage drop in the n-type base zone determines the forward voltage of the IEGT as a whole, especially in the case of a large layer thickness of the n-type base zone 2, that is to say with higher blocking IEGTs, it is possible in this way despite the resistance which the holes in the narrow area have Current path in the p-type base zone 3 is opposed, reduce the forward voltage of the IEGT. .This narrow current path is, as shown in the examples of FIGS. Is seen to 9 "1, produced in that the individual trench IEGT cells are not directly adjacent, but have a certain distance between them which by the additional trench 14 or the wide p-type zone 15 is formed.
IEGTs der oben beschriebenen Art sind beispielsweise aus US 5 329 142, US 5 448 083, US 5 585 651 und GB-A- 2314206 bekannt. Ein Nachteil dieser bekannten IEGTs bzw. IGBTs besteht in der großen Rückwirkungskapazität, die eine Folge der großen, nicht für einen MOS-Kanal benötigten Gateoxidfläche ist, wel-che wiederum auf den großen Abstand zwischen den Zellen zurückzuführen ist.IEGTs of the type described above are known for example from US 5 329 142, US 5 448 083, US 5 585 651 and GB-A-2314206. A disadvantage of these known IEGTs or IGBTs is the large feedback capacity, which is a consequence of the large gate oxide area which is not required for a MOS channel, which in turn is due to the large distance between the cells.
Um diese große Rückwirkungskapazität zu vermindern, wird in der bereits erwähnten DE-Al 196 51 108 ein Trench- IGBT vorgeschlagen, bei dem die in den inaktiven Trenchs angeordnete Elektrode (vgl. Trench 14 in Fig. 7) nicht an das Gatepotential, sondern an das Potential des Emitterkontaktes bzw. der Vorderseite angeschlossen ist. Ein Nachteil einer derartigen Struktur liegt aber darin, daß ein großer Teil des leitenden Materials in den Trenches, also beispielsweise die Hälfte des polykristallinen Siliziums, nicht für die Leitfähigkeit der Gateelektrode zur Verfügung steht, was den effektiven Gatewiderstand erhöht.In order to reduce this large feedback capacity, a trench IGBT is proposed in the already mentioned DE-A1 196 51 108, in which the electrode arranged in the inactive trench (see trench 14 in FIG. 7) does not connect to the gate potential, but to the potential of the emitter contact or the front is connected. However, a disadvantage of such a structure is that a large part of the conductive material in the trenches, for example half of the polycrystalline silicon, is not available for the conductivity of the gate electrode, which increases the effective gate resistance.
Aus EP-A2-837 508 ist ein IGBT bekannt, bei dem die Rückwirkungskapazität verringert ist, indem die Gateoxiddicke außerhalb des Kanalbereiches vergrößert ist.From EP-A2-837 508 an IGBT is known in which the feedback capacity is reduced by increasing the gate oxide thickness outside the channel area.
Schließlich ist aus der nicht vorveröffentlichten DE-Al- 199 35 442 ein Verfahren zum Herstellen eines Trench- MOS-Leistungstransistors bekannt, bei dem mittels einer Hilfsschicht in einem Trench einer epitaktischen Schicht eine Oxidstufe zwischen einer dickeren Oxidschicht und einer dünneren Oxidschicht erzeugt wird, um speziell bei tiefen Trenches das Auftreten von Spitzen des elektrischen Feldes zu vermeiden.Finally, from the unpublished DE-Al-199 35 442 a method for producing a trench MOS power transistor is known, in which an oxide layer is generated between a thicker oxide layer and a thinner oxide layer by means of an auxiliary layer in a trench of an epitaxial layer Avoid the occurrence of peaks in the electrical field, especially in deep trenches.
Es ist nun Aufgabe der vorliegenden Erfindung, einen Trench-IGBT anzugeben, bei dem auf einfache Weise die Rückwirkungskapazität verringert ist, ohne den effektiven Gatewiderstand zu erhöhen. Diese Aufgabe wird erfindungsgemäß durch einen Trench- IGBT mit den Merkmalen des Patentanspruches 1 gelöst.It is an object of the present invention to provide a trench IGBT in which the feedback capacity is reduced in a simple manner without increasing the effective gate resistance. This object is achieved according to the invention by a trench IGBT with the features of patent claim 1.
Vorteilhafte Weiterbildungen der Erfindung ergeben sich aus den Unteransprüchen.Advantageous developments of the invention result from the subclaims.
Bei der vorliegenden Erfindung wirkt also die Isolierschicht als Gateisolierfilm (bzw. Gateoxid) nur in dem für die Funktionsfähigkeit des MOS-Kanals notwendigen Bereich. Das heißt, die Gateoxidfläche ist auf den für die Funktionsfähigkeit des MOS-Kanals nötigen Bereich begrenzt .In the present invention, the insulating layer acts as a gate insulating film (or gate oxide) only in the area necessary for the functionality of the MOS channel. This means that the gate oxide area is limited to the area required for the functionality of the MOS channel.
Durch diese Maßnahme läßt sich eine nicht unerhebliche Verringerung der Rückwirkungskapazität erzielen.This measure makes it possible to achieve a not inconsiderable reduction in the retroactive capacity.
Besonders vorteilhaft ist es aber, wenn in Trench-IGBTs, bei denen' nur auf einer Seite des Trenchs ein aktiver MOS-Kanal vorhanden ist, eine dickere Isolierschicht die gesamte inaktive Seite des Trenchs und gegebenenfalls auch einen Teil von dessen Oberseite belegt, während nur im Bereich des aktiven MOS-Kanals, also im Bereich der zweiten Basiszone, anstelle der dickeren Isolierschicht * ein dünner Gateisolierfilm vorgesehen ist. Je nach dem Verhältnis der Schiσ-htdicken der dickeren Isolierschicht auf inaktiven Oberflächen des Trenchs zu der Schichtdik- ke des Gateisolierfilms im Bereich des aktiven MOS-Kanals kann so die Rückwirkungskapazität auf beispielswei- se die Hälfte reduziert werden.It is particularly advantageous, however, if in trench IGBTs, in which an active MOS channel is' present on only one side of the trench, a thicker insulating layer, the entire inactive side of the trench, and optionally also a portion occupied by the upper side thereof, while only in the area of the active MOS channel, that is to say in the area of the second base zone, a thin gate insulating film is provided instead of the thicker insulating layer *. Depending on the ratio of the layer thicknesses of the thicker insulating layer on inactive surfaces of the trench to the layer thickness of the gate insulating film in the region of the active MOS channel, the reaction capacity can be reduced to half, for example.
Der erfindungsgemäße Trench-IGBT kann in besonders vorteilhafter Weise mittels des in der bereits erwähnten DE-Al-199 35 442 beschriebenen Verfahrens hergestellt werden, bei dem in einen Halbleiterkörper wenigstens ein Graben eingebracht wird, der dann mit einem von der Grabeninnenfläche durch eine Isolierschicht getrennten lei- tenden Material wenigstens teilweise ausgefüllt wird, wobei die Isolierschicht so in den Graben eingebracht wird, daß diese im Bereich des unteren Endes des Grabens mit einer größeren Schichtdicke als an dessen oberen Ende versehen ist. Dieses Verfahren weist insbesondere die folgenden Verfahrensschritte auf:The trench IGBT according to the invention can be produced in a particularly advantageous manner by means of the method described in the aforementioned DE-Al-199 35 442, in which at least one trench is made in a semiconductor body, which is then separated from the inner surface of the trench by an insulating layer managerial tendency material is at least partially filled, wherein the insulating layer is introduced into the trench so that it is provided in the region of the lower end of the trench with a greater layer thickness than at the upper end. This method has in particular the following process steps:
Eiribringen wenigstens eines Grabens in den Halbleiterkörper,Bringing at least one trench into the semiconductor body,
Belegen der Wände und des Boden des Grabens mit einem ersten Isolierfilm,Covering the walls and the bottom of the trench with a first insulating film,
Auffüllen des unteren Endes des Grabens mit einer ersten Hilfsschicht,Filling the lower end of the trench with a first auxiliary layer,
Entfernen der nicht mit der ersten Hilfsschicht belegten Teile des ersten Isolierfilmes,Removing the parts of the first insulating film not covered with the first auxiliary layer,
- Entfernen der Hilfsschicht,- removal of the auxiliary layer,
Aufwachsen eines zweiten Isolierfilmes, der dünner als die Enddicke des ersten Isolierfilmes ist, auf den freiliegenden Wänden des Grabens,Growing a second insulating film, which is thinner than the final thickness of the first insulating film, on the exposed walls of the trench,
Füllen des Grabens mit dem leitenden Material undFilling the trench with the conductive material and
Einbringen von Source- und Bodyzonen in den Halbleiterkörper und Anbringen von Metallisierungen zur Kontak- tierung.Introduction of source and body zones into the semiconductor body and application of metallizations for contacting.
Die oben erläuterten bevorzugten Ausführungsbeispiele, bei denen nur im Bereich des aktiven MOS-Kanals ein dünner Gateisolierfilm im Trench angebracht wird, während dieser sonst mit der dickeren Isolierschicht ausgelegt ist, lassen sich mittels des obigen Verfahrens beispielsweise dadurch realisieren, daß die Kante einer weiteren Hilfsschicht, die aufgetragen wird, um die Entfernung des ersten Isolierfilmes in maskierten Bereichen zu verhindern, etwa in der Mitte über einem Trench zu liegen kommt. Auf der von der weiteren Hilfsschicht überdeckten Seite des Trenchs ergibt sich dann die dik- kere Isolierschicht über der gesamten Trenchtiefe, während auf der anderen Seite des Trenchs diese dicke Isolierschicht auf den unteren Teil des Trenchs beschränkt bleibt und im oberen Teil der im Vergleich zur dicken Isolierschicht dünnere Gateisolierfilm erzeugt wird.The preferred exemplary embodiments explained above, in which a thin gate insulating film is applied in the trench only in the region of the active MOS channel, while this is otherwise designed with the thicker insulating layer, can be realized by means of the above method, for example, in that the edge of a another auxiliary layer, which is applied to prevent the removal of the first insulating film in masked areas, for example in the middle of a trench. On the side of the trench covered by the additional auxiliary layer, the thicker insulating layer then results over the entire depth of the trench, while on the other side of the trench this thick insulating layer remains limited to the lower part of the trench and in the upper part that compared to the thick one Insulating layer thinner gate insulating film is produced.
Nachfolgend wird die Erfindung anhand der Zeichnungen näher erläutert. Es zeigen:The invention is explained in more detail below with reference to the drawings. Show it:
Fig. 1 bis 5 Schnittbilder zur Erläuterung verschiedener Ausführungsbeispiele des erfindungsgemäßen IGBTs und1 to 5 are sectional views for explaining various embodiments of the IGBT and
Fig. 6 bis 9 Schnittbilder durch bestehende IGBTs.6 to 9 sectional views through existing IGBTs.
Die Fig. 6 bis 9 sind bereits eingangs erläutert worden.6 to 9 have already been explained at the beginning.
In den Figuren werden einander entsprechende Bauteile jeweils mit den gleichen Bezugszeichen versehen.In the figures, components which correspond to one another are each provided with the same reference symbols.
Die folgenden Ausführungsbeispiele beziehen sich wie die Beispiele der Fig. 6 bis 9 zur Erläuterung des Standes der Technik -auf einen IGBT mit einer n-leitenden Emitterzone. Obwohl dies der bevorzugte Leitungstyp für die Emitterzone ist, kann die Erfindung grundsätzlich auch auf einen Trench-IGBT angewandt werden, bei dem die Emitterzone p-leitend ist.Like the examples in FIGS. 6 to 9, the following exemplary embodiments relate to an IGBT with an n-type emitter zone to explain the prior art. Although this is the preferred conduction type for the emitter zone, the invention can in principle also be applied to a trench IGBT in which the emitter zone is p-type.
Fig. 1 zeigt ein erstes Ausführungsbeispiel des erfindungsgemäßen Trench-IGBTs, der sich von dem herkömmlichen Trench-IGBT nach Fig. 6 dadurch unterscheidet, daß die Isolier-schicht 7 in den unteren Bereichen der Tren- che 5, 6 als Dickoxid.17 ausgebildet ist, während sie im Bereich des akti-ven MOS-Kanals, also im Bereich der p- leitenden Basiszone 3 einen dünnen Gateoxidfilm bildet. Durch das Dickoxid 17 wird die Rückwirkungskapazität nicht unerheblich verkleinert, wäh-rend der Gateoxidfilm mit geringer Schichtdicke nur in dem für die Funktionsfähigkeit des MOS-Kanals notwendigen Bereich vorliegt .1 shows a first exemplary embodiment of the trench IGBT according to the invention, which differs from the conventional trench IGBT according to FIG. 6 in that the insulating layer 7 is formed as thick oxide 17 in the lower regions of the trench 5, 6 is while in Area of the active MOS channel, ie in the area of the p-type base zone 3, forms a thin gate oxide film. The reaction capacitance is not insignificantly reduced by the thick oxide 17, while the gate oxide film with a small layer thickness is only present in the area necessary for the functionality of the MOS channel.
Die in Fig. 1 gezeigte Struktur mit dem Dickoxid 17 im unteren Bereich der Trenche 5, 6 kann ohne weiteres durch das oben erläuterte Verfahren mittels der Verfahrensschritte (a) bis (g) erzeugt werden. Für die darin erwähnte Hilfsschicht kann beispielsweise ein Photolack eingesetzt werden, während für die Isolierfilme Siliziumnitrid und/oder Siliziumdioxid vorteilhaft sind.The structure shown in FIG. 1 with the thick oxide 17 in the lower region of the trenches 5, 6 can easily be produced by the method explained above using the method steps (a) to (g). For example, a photoresist can be used for the auxiliary layer mentioned therein, while silicon nitride and / or silicon dioxide are advantageous for the insulating films.
Hinsichtlich der Verkleinerung der Rückwirkungskapazität sind die Ausführungsbeispiele der Fig. 2 bis 5 vorteilhafter als das Ausführungsbeispiel der Fig. 1. In den Ausführungsbeispielen der Fig. 2 bis 4 ist der aktive MOS-Kanal nur auf einer Seite der Trenche vorgesehen, während im Ausführungsbeispiel der Fig. 5 der Abstand zwischen zwei Zellen des IGBTs durch die p-leitende Zone 15 verbreitert ist.With regard to the reduction in the feedback capacity, the exemplary embodiments of FIGS. 2 to 5 are more advantageous than the exemplary embodiment of FIG. 1. In the exemplary embodiments of FIGS. 2 to 4, the active MOS channel is provided only on one side of the trench, while in the exemplary embodiment the 5, the distance between two cells of the IGBT is widened by the p-type zone 15.
Im einzelnen zeigt Fig. 2 ein Ausführungsbeispiel (IEGT) , bei dem, ähnlich wie bei dem bestehenden IGBT von Fig. 7, ein zusätzlicher Trench 17 ohne aktiven MOS- Kanal zwischen zwei IGBT-Zellen vorgesehen ist, um so den Abstand zwischen diesen Zellen zu erweitern. Entsprechend hat dieser zusätzliche Trench 14 ein Dickoxid 17, das auch bei den Trenches 5, 6 der beiden IGBT-Zellen mit Ausnahme des Bereiches des aktiven MOS-Kana-ls ausgebildet ist. Im Bereich dieses aktiven MOS-Ka-nals ist die Isolierschicht 7 als Gateoxidfilm mit wesentlich geringerer Schichtdicke als das Dickoxid 17 vorgesehen.In particular, FIG. 2 shows an exemplary embodiment (IEGT) in which, similar to the existing IGBT from FIG. 7, an additional trench 17 without an active MOS channel is provided between two IGBT cells, thereby increasing the distance between these cells to expand. Accordingly, this additional trench 14 has a thick oxide 17, which is also formed in the trenches 5, 6 of the two IGBT cells, with the exception of the region of the active MOS channel. In the area of this active MOS channel, the insulating layer 7 is provided as a gate oxide film with a much smaller layer thickness than the thick oxide 17.
Durch die Ausführung der Isolierung als Dickoxid 17 auf allen Bereichen der Trenche 5, 6 und 14 mit Ausnahme der Bereiche der aktiven MOS-Kanäle kann die Rückwirkungska- pazität stark vermindert werden.By designing the insulation as thick oxide 17 In all areas of trenches 5, 6 and 14, with the exception of the areas of the active MOS channels, the feedback capacity can be greatly reduced.
Fig. 3 zeigt ein weiteres Ausführungsbeispiel des erfindungsgemäßen Trench-IGBTs (IEGT) , bei dem anstelle des Trenches 14 ohne aktiven MOS-Kanal entsprechend dem herkömmlichen IGBT von Fig. 8 eine relativ breite p-leitende Zone 15 zwischen den beiden IGBT-Zellen angeordnet ist. Im übrigen sind die Trenche 5, 6 bei diesem Ausführungsbeispiel in ähnlicher Weise gestaltet wie bei dem Ausführungsbeispiel von Fig. 2.FIG. 3 shows a further exemplary embodiment of the trench IGBT (IEGT) according to the invention, in which, instead of the trench 14 without an active MOS channel in accordance with the conventional IGBT of FIG. 8, a relatively wide p-conducting zone 15 is arranged between the two IGBT cells is. Otherwise, the trenches 5, 6 in this exemplary embodiment are designed in a similar manner to the exemplary embodiment in FIG. 2.
Fig. 4 zeigt ein weiteres Ausführungsbeispiel der Erfin- düng, bei dem die leitenden Materialien 8 (polykristallines Silizium) der Trenche 6 der beiden Zellen über eine leitende Verbindung 16 entsprechend dem herkömmlichen IGBT von Fig. 9 miteinander verbunden sind. Eine solche Verbindung ist auch beim Ausführungsbeispiel der Fig. 5 vorgesehen, bei dem im Unterschied zum Ausführungsbeispiel von Fig. 4 die Trenche 5, 6 an ihrem unteren Ende beidseitig mit der Isolierschicht 7 als Gateoxidfilm versehen sind.FIG. 4 shows a further exemplary embodiment of the invention, in which the conductive materials 8 (polycrystalline silicon) of the trenches 6 of the two cells are connected to one another via a conductive connection 16 in accordance with the conventional IGBT from FIG. 9. Such a connection is also provided in the exemplary embodiment in FIG. 5, in which, in contrast to the exemplary embodiment in FIG. 4, the trenches 5, 6 are provided on both sides with the insulating layer 7 as a gate oxide film at their lower end.
Die Schichtdicke des Dickoxides 17 beträgt vorzugsweise wenigstens das Doppelte der Schichtdicke des Gateoxidfilmes 7. The layer thickness of the thick oxide 17 is preferably at least twice the layer thickness of the gate oxide film 7.

Claims

Patentansprüche claims
1. Trench-IGBT mit verringerter Rückwirkungskapazität, umfassend:1. A trench IGBT with reduced feedback capacity, comprising:
' - eine an eine erste Hauptoberfläche (9) eines Halbleiterkörpers (1, 2, 3, 4) angrenzende Emitterzone (4) eines ersten Leitungstyps,'- an emitter zone (4) of a first conductivity type adjacent to a first main surface (9) of a semiconductor body (1, 2, 3, 4),
- eine die Emitterzone (4) im wesentlichen umgebende erste Basiszone (3) eines zweiten, zum ersten Leitungstyp entgegengesetzten Leitungstyps, eine an die erste Basiszone (3) angrenzende zweite Basiszone (2) des ersten Leitungstyps, eine an die zweite Basiszone (2) angrenzende und eine zweite Hauptoberfläche (12) des Halbleiterkörpers (1, 2, 3, 4) bildende Kollektorzone (1) des zweiten Leitungstyps, eine Gateelektrode (8) in einem mit einer Isolierschicht (7, 17) ausgekleideten Trench (5, 6), der sich von der er-sten Hauptoberfläche (9) bis in die zweite Basiszone (2) erstreckt, wobei sich längs des Trenches (5, 6) in der ersten Basiszone (3) zwischen der Emitterzone (4) und der zweiten Basiszone (2) ein aktiver MOS- Kanal des ersten Leitungstyps auszubilden vermag, einen die Emitterzone (4) und die erste Basiszone (3) auf der ersten Hauptoberfläche (9) kontaktierenden Emitterkontakt (11) und einen an die Kollektorzone (1) auf der zweiten Hauptoberfläche (12) angrenzenden Kollektorkontakt (13), d a d u r c h g e k e n n z e i c h n e t , - daß die Isolierschicht (7, 17) als Gateisolierfilm (7) nur in dem für die Funktionsfähigkeit des MOS-Kanals notwendigen Bereich wirkt.- a first base zone (3) essentially surrounding the emitter zone (4) of a second line type opposite to the first line type, a second base zone (2) of the first line type adjoining the first base zone (3), one to the second base zone (2) Adjacent and a second main surface (12) of the semiconductor body (1, 2, 3, 4) forming collector zone (1) of the second conductivity type, a gate electrode (8) in a trench (5, 6) lined with an insulating layer (7, 17) , which extends from the first main surface (9) to the second base zone (2), wherein along the trench (5, 6) in the first base zone (3) between the emitter zone (4) and the second base zone ( 2) is able to form an active MOS channel of the first conductivity type, an emitter contact (11) contacting the emitter zone (4) and the first base zone (3) on the first main surface (9) and one to the collector zone (1) on the second main surface (12) adjacent collection orkontakt (13), d a d u r c h g e k e n n z e i c h n e t - that the insulating layer (7, 17) acts as a gate insulating film (7) only in the area necessary for the functionality of the MOS channel.
2. Trench-IGBT nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t , daß der Gateisolierfilm (7) im Bereich der ersten Basiszone (3) vorgesehen ist und die Isolierschicht (17) im Be- ' reich der zweiten Basiszone (2) eine gegenüber dem Gateisolierfilm größere Schichtdicke aufweist.2. Trench IGBT according to claim 1, characterized in that the gate insulating film (7) in the region of the first base zone Is provided (3) and reaching said second base region (2) having the insulating layer (17) in the loading 'is a gate insulating film over the greater layer thickness.
3. Trench-IGBT nach Anspruch 1 oder 2, d a d u r c h g e k e n n z e i c h n e t , daß zwischen einzelnen Zellen des Trench-IGBTs ein zusätzlicher Zwischenraum (vgl. 14, 15) vorgesehen ist.3. Trench IGBT according to claim 1 or 2, d a d u r c h g e k e n n z e i c h n e t that an additional space (cf. 14, 15) is provided between individual cells of the trench IGBT.
4. Trench-IGBT nach Anspruch 3, d a d u r c h g e k e n n z e i c h n e t , daß im zusätzlichen Zwischenraum ein weiterer Trench (14) ohne aktiven MOS-Kanal und mit ganzflächiger dicker Isolierschicht (17) vorgesehen ist.4. Trench IGBT according to claim 3, d a d u r c h g e k e n n e e c h n e t that a further trench (14) without an active MOS channel and with a full-surface thick insulating layer (17) is provided in the additional space.
5. Trench-IGBT nach Anspruch 4, d a d u r c h g e k e n n z e i c h n e t , daß im zusätzlichen Zwischenraum eine Zone (15) des zweiten Leitungstyps vorgesehen ist.5. Trench IGBT according to claim 4, d a d u r c h g e k e n n z e i c h n e t that a zone (15) of the second conduction type is provided in the additional space.
6. Trench-IGBT nach einem der Ansprüche 1 bis 5, d a d u r c h g e k e n n z e i c h n e t , daß die Gateelektroden (8) mehrerer Trenche (5, 6) elektrisch leitend miteinander verbunden sind (vgl. 16) .6. Trench IGBT according to one of claims 1 to 5, that the gate electrodes (8) of a plurality of trenches (5, 6) are connected to one another in an electrically conductive manner (cf. FIG. 16).
7. Trench-IGBT nach einem der Ansprüche 1 bis 6, d a d u r c h g e k e n n z e i c h n e t , daß die Gateelektroden (8) aus polykristallinem Silizium bestehen .7. Trench IGBT according to one of claims 1 to 6, d a d u r c h g e k e n n z e i c h n e t that the gate electrodes (8) consist of polycrystalline silicon.
8. Trench-IGBT nach einem der Ansprüche 1 bis 7, d a d u r c h g e k e n n z e i c h n e t , daß die Schichtdicke der Isolierschicht (17) wenigstens das Doppelte der Schichtdicke des Gateoxidfilmes (7) beträgt.8. Trench IGBT according to one of claims 1 to 7, characterized in that the layer thickness of the insulating layer (17) is at least twice the layer thickness of the gate oxide film (7).
9. Trench-IGBT nach einem der Ansprüche 1 bis 8, d a d u r c h g e k e n n z e i c h n e t , daß die Trenche (5, 6) nur auf der Seite des aktiven MOS-Kanals mit einem Gateoxidfilm (7) versehen sind. 9. trench IGBT according to one of claims 1 to 8, d a d u r c h g e k e n n z e i c h n e t that the trenches (5, 6) are provided only on the side of the active MOS channel with a gate oxide film (7).
PCT/EP2000/008459 2000-08-30 2000-08-30 Trench igbt WO2002019434A1 (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
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DE10127885B4 (en) * 2001-06-08 2009-09-24 Infineon Technologies Ag Trench power semiconductor device
US8044458B2 (en) 2006-05-23 2011-10-25 Infineon Technologies Austria Ag Semiconductor device including a vertical gate zone, and method for producing the same
CN104518017A (en) * 2013-09-30 2015-04-15 英飞凌科技股份有限公司 IGBT with reduced feedback capacitance
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