WO2002016955A2 - Capteur de hall a semi-conducteurs composes - Google Patents

Capteur de hall a semi-conducteurs composes Download PDF

Info

Publication number
WO2002016955A2
WO2002016955A2 PCT/US2001/024559 US0124559W WO0216955A2 WO 2002016955 A2 WO2002016955 A2 WO 2002016955A2 US 0124559 W US0124559 W US 0124559W WO 0216955 A2 WO0216955 A2 WO 0216955A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
monocrystalline
oxide
compound semiconductor
substrate
Prior art date
Application number
PCT/US2001/024559
Other languages
English (en)
Other versions
WO2002016955A3 (fr
Inventor
Lyndee Hilt
Jamal Ramdani
Original Assignee
Motorola, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola, Inc. filed Critical Motorola, Inc.
Priority to AU2001279196A priority Critical patent/AU2001279196A1/en
Publication of WO2002016955A2 publication Critical patent/WO2002016955A2/fr
Publication of WO2002016955A3 publication Critical patent/WO2002016955A3/fr

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/02—Measuring direction or magnitude of magnetic fields or magnetic flux
    • G01R33/06—Measuring direction or magnitude of magnetic fields or magnetic flux using galvano-magnetic devices
    • G01R33/07—Hall effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00

Definitions

  • This invention relates generally to semiconductor structures and devices and to a method for their fabrication, and more specifically to the fabrication and use of Hall sensors using compound semiconductor thin films, such as indium arsenide (InAs) and/or gallium arsenic antimonide (GaAsSb) thin films, grown on a monocrystalline semiconductor substrate.
  • compound semiconductor thin films such as indium arsenide (InAs) and/or gallium arsenic antimonide (GaAsSb) thin films, grown on a monocrystalline semiconductor substrate.
  • GaAs Gallium arsenide
  • silicon wafers are available up to about 300 mm and are widely available at 200 mm.
  • the 150 mm GaAs wafers are many times more expensive than are their silicon counterparts. Wafers of other compound semiconductor materials are even less available and are more expensive than GaAs.
  • a variety of semiconductor devices could advantageously be fabricated in that film at a low cost compared to the cost of fabricating such devices on a bulk wafer of compound semiconductor material or in an epitaxial film of such material on a bulk wafer of compound semiconductor material.
  • a thin film of high quality monocrystalline compound semiconductor material could be realized on a bulk wafer such as a silicon wafer, a monolithic integration of integrated devices, such as, for example, optoelectronic devices, such as laser diodes, light emitting diodes, photodiodes, or heterojunction tunnel devices, could be achieved that took advantage of the best properties of both the silicon and the compound semiconductor material.
  • a Hall device such as a Hall sensor, is normally a four-terminal device used for detecting a magnetic field, h a typical Hall sensor, a semiconductor layer has two electrodes for passing electrical current in a first direction through the semiconductor layer, and two additional electrodes for detecting the voltage transverse to the electrical current at times when a magnetic field to be detected is passing through the semiconductor layer.
  • Hall sensors typically use n-type silicon when cost is of primary importance and GaAs for higher temperature capability due to its larger band gap.
  • InAs, indium antimonide (InSb), and other semiconductor materials are gaining popularity due to their high carrier mobilities that result in greater sensitivity and frequency response capabilities above the 10-20 kHz typical of silicon Hall sensors.
  • InAs Hall sensors have small temperature dependence of output voltage, good stability to pulse voltage noise, low offset drift and low noise properties for low magnetic field sensing.
  • the demand for Hall sensors is rapidly growing due to the evolving electronics industry. As the demand increases, there is a need for materials that are highly sensitive, with a large electron mobility over a wide temperature range.
  • InAs is a good material for use in Hall sensors due to its high electron mobility as compared with other III-V compound semiconductor materials.
  • One difficulty in the past with InAs is the lack of insulating substrates that are lattice matched with InAs to enable growth of high quality InAs thin films.
  • current InAs thin films grown by molecular beam epitaxy (MBE) on GaAs exhibit approximately 7% lattice mismatch, which creates many misfit dislocations at the InAs/GaAs interface, thus degrading the electronic properties of the InAs thin film, such as electron mobility.
  • MBE molecular beam epitaxy
  • a monocrystalline compound semiconductor film such as InAs
  • GaAs or silicon another monocrystalline material
  • FIGS. 1 - 3 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention
  • FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer
  • FIG. 5 illustrates a high resolution Transmission Electron Micrograph of a structure including a monocrystalline accommodating buffer layer
  • FIG. 6 illustrates an x-ray diffraction spectrum of a structure including a monocrystalline accommodating buffer layer
  • FIG. 7 illustrates a high resolution Transmission Electron Micrograph of a structure including an amorphous oxide layer
  • FIG. 8 illustrates an x-ray diffraction spectrum of a structure including an amorphous oxide layer
  • FIG. 9 illustrates schematically, in cross section, a monolithic integrated circuit in accordance with one embodiment of the invention.
  • FIGS. 10-11 illustrate schematically, in cross section, device structures in accordance with further exemplary embodiments of the invention.
  • the present invention provides a template that reduces the lattice mismatch between InAs and an underlying insulating substrate to less than about 2% and provides a method of growing the InAs over a semiconductor substrate or layer, thus allowing for monolithic integration of Hall sensors with complementary metal-oxide-silicon (CMOS) integrated circuits.
  • CMOS complementary metal-oxide-silicon
  • FIG. 1 illustrates schematically, in cross section, a portion of a semiconductor structure 20 in accordance with an embodiment of the invention.
  • Semiconductor structure 20 includes a monocrystalline substrate 22, accommodating buffer layer 24 comprising a monocrystalline material, and a layer 26 of a monocrystalline compound semiconductor material.
  • monocrystalline shall have the meaning commonly used within the semiconductor industry.
  • the term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.
  • structure 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24.
  • Structure 20 may also include a template layer 30 between the accommodating buffer layer and compound semiconductor layer 26.
  • the template layer helps to initiate the growth of the compound semiconductor layer on the accommodating buffer layer.
  • the amorphous intermediate layer helps to relieve the strain in the accommodating buffer layer and by doing so, aids in the growth of a high crystalline quality accommodating buffer layer.
  • Substrate 22 in accordance with an embodiment of the invention, is a monocrystalline semiconductor wafer, preferably of large diameter.
  • the wafer can be of a material from Group IV of the periodic table, and preferably a material from Group rVA.
  • Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like.
  • substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry.
  • Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate.
  • amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer by the oxidation of substrate 22 during the growth of layer 24.
  • the amorphous intermediate layer serves to relieve strain that might otherwise occur in the monocrystalline accommodating buffer layer as a result of differences in the lattice constants of the substrate and the buffer layer.
  • lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by the amorphous intermediate layer, the strain may cause defects in the crystalline structure of the accommodating buffer layer. Defects in the crystalline structure of the accommodating buffer layer, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline compound semiconductor layer 26.
  • Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate and with the overlying compound semiconductor material.
  • the material could be an oxide or nitride having a lattice structure substantially matched to the substrate and/or to the subsequently applied semiconductor material.
  • Materials that are suitable for the accommodating buffer layer include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafhates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer.
  • metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafhates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vana
  • Amorphous interface layer 28 is preferably an oxide formed by the oxidation of the surface of substrate 22, and more preferably is composed of a silicon oxide. The thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating buffer layer 24. Typically, layer 28 has a thickness in the range of approximately 0.5-5 nm.
  • the compound semiconductor material of layer 26 can be selected, as needed for a particular semiconductor structure, from any of the Group IIIA and VA elements (III- V semiconductor compounds), mixed III-V compounds, Group II(A or B) and VIA elements (II- VI semiconductor compounds), and mixed II- VI compounds.
  • Group IIIA and VA elements III- V semiconductor compounds
  • mixed III-V compounds Group II(A or B) and VIA elements
  • II- VI semiconductor compounds VIA elements
  • mixed II- VI compounds examples include gallium arsenide (GaAs), gallium indium arsenide (GalnAs), gallium aluminum arsenide (GaAlAs), indium phosphide (InP), cadmium sulfide (CdS), cadmium mercury telluride (CdHgTe), zinc selenide (ZnSe), zinc sulfur selenide (ZnSSe), and the like.
  • FIG. 2 illustrates, in cross section, a portion of a semiconductor structure 40 in accordance with a further embodiment of the invention.
  • Structure 40 is similar to the previously described semiconductor structure 20, except that an additional buffer layer 32 is positioned between accommodating buffer layer 24 and layer of monocrystalline compound semiconductor material 26. Specifically, the additional buffer layer is positioned between template layer 30 and the overlying layer of compound semiconductor material.
  • the additional buffer layer formed of a semiconductor or compound semiconductor material, serves to provide a lattice compensation when the lattice constant of the accommodating buffer layer cannot be adequately matched to the overlying monocrystalline compound semiconductor material layer.
  • FIG. 3 schematically illustrates, in cross section, a portion of a semiconductor structure 34 in accordance with another exemplary embodiment of the invention.
  • Structure 34 is similar to structure 20, except that structure 34 includes an amorphous layer 36, rather than accommodating buffer layer 24 and amorphous interface layer 28, and an additional semiconductor layer 38.
  • amorphous layer 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above. Monocrystalline semiconductor layer 38 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer. Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus, layer 36 may comprise one or two amorphous layers. Formation of amorphous layer 36 between substrate 22 and semiconductor layer 38 (subsequent to layer 38 formation) relieves stresses between layers 22 and 38 and provides a true compliant substrate for subsequent processing ⁇ e.g., compound semiconductor layer 26 formation.
  • Semiconductor layer 38 may include any of the materials described throughout this application in connection with either of compound semiconductor material layer 26 or additional buffer layer 32.
  • layer 38 may include monocrystalline Group rV or monocrystalline compound semiconductor materials.
  • semiconductor layer 38 serves as an anneal cap during layer 36 formation and as a template for subsequent semiconductor layer 26 formation. Accordingly, layer 38 is preferably thick enough to provide a suitable template for layer 26 growth (at least one monolayer) and thin enough to allow layer 38 to form as a substantially defect free monocrystalline semiconductor compound.
  • semiconductor layer 38 comprises compound semiconductor material (e.g., a material discussed above in connection with compound semiconductor layer 26) that is thick enough to form devices within layer 38.
  • compound semiconductor material e.g., a material discussed above in connection with compound semiconductor layer 26
  • a semiconductor structure in accordance with the present invention does not include compound semiconductor layer 26.
  • the semiconductor structure in accordance with this embodiment only includes one compound semiconductor layer disposed above amorphous oxide layer 36.
  • monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction.
  • the silicon substrate can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200-300 mm.
  • CMOS complementary metal oxide semiconductor
  • accommodating buffer layer 24 is a monocrystalline layer of Sr z Ba ⁇ _ z TiO 3 where z ranges from 0 to 1 and the amorphous intermediate layer is a layer of silicon oxide (SiO x ) formed at the interface between the silicon substrate and the accommodating buffer layer.
  • the value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer 26.
  • the accommodating buffer layer can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 10 nm. In general, it is desired to have an accommodating buffer layer thick enough to isolate the compound semiconductor layer from the substrate to obtain the desired electrical and optical properties.
  • the amorphous intermediate layer of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1.5-2.5 nm.
  • compound semiconductor material layer 26 is a layer of gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) having a thickness of about 1 nm to about 100 micrometers ( ⁇ m) and preferably a thickness of about 0.5 ⁇ m to 10 ⁇ m. The thickness generally depends on the application for which the layer is being prepared.
  • a template layer is formed by capping the oxide layer.
  • the template layer is preferably 1 - 10 monolayers of Ti-As, Sr-O-As, Sr-Ga-O, or Sr-Al-O.
  • 1-2 monolayers of Ti-As or Sr-Ga-O have been shown to successfully grow GaAs layers.
  • monocrystalline substrate 22 is a silicon substrate as described above.
  • the accommodating buffer layer is a monocrystalline oxide of strontium or barium zirconate or hafnate in a cubic or orthorhombic phase with an amorphous intermediate layer of silicon oxide formed at the interface between the silicon substrate and the accommodating buffer layer.
  • the accommodating buffer layer can have a thickness of about 2-100 nm and preferably has a thickness of at least 5 nm to ensure adequate crystalline and surface quality and is formed of a monocrystalline SrZrO 3 , BaZrO , SrHfO 3 , BaSnO 3 or BaHfO 3 .
  • a monocrystalline oxide layer of BaZrO 3 can grow at a temperature of about 700 degrees C.
  • the lattice structure of the resulting crystalline oxide exhibits a 45 degree rotation with respect to the substrate silicon lattice structure.
  • An accommodating buffer layer formed of these zirconate or hamate materials is suitable for the growth of compound semiconductor materials in the indium phosphide (InP) system.
  • the compound semiconductor material can be, for example, indium phosphide (InP), indium gallium arsenide (iGaAs), aluminum indium arsenide, (AlInAs), or aluminum gallium indium arsenic phosphide (AlGalnAsP), having a thickness of about 1.0 nm to 10 ⁇ m.
  • a suitable template for this structure is 1-10 monolayers of zirconium-arsenic (Zr-As), zirconium-phosphorus (Zr-P), hafnium- arsenic (Hf-As), hafnium-phosphorus (Hf-P), strontium-oxygen-arsenic (Sr-O-As), strontium-oxygen-phosphorus (Sr-O-P), barium-oxygen-arsenic (Ba-O-As), indium- strontium-oxygen (In-Sr-O), or barium-oxygen-phosphorus (Ba-O-P), and preferably 1- 2 monolayers of one of these materials.
  • the surface is terminated with 1-2 monolayers of zirconium followed by deposition of 1-2 monolayers of arsenic to form a Zr-As template.
  • a monocrystalline layer of the compound semiconductor material from the indium phosphide system is then grown on the template layer.
  • the resulting lattice structure of the compound semiconductor material exhibits a 45 degree rotation with respect to the accommodating buffer layer lattice structure and a lattice mismatch to (100) InP of less than 2.5%, and preferably less than about 1.0%.
  • Example 3 In accordance with a further embodiment of the invention, a structure is provided that is suitable for the growth of an epitaxial film of a II- VI material overlying a silicon substrate.
  • the substrate is preferably a silicon wafer as described above.
  • a suitable accommodating buffer layer material is Sr x Ba ⁇ . x TiO 3 , where x ranges from 0 to 1, having a thickness of about 2-100 nm and preferably a thickness of about 5-15 nm.
  • the II- VI compound semiconductor material can be, for example, zinc selenide (ZnSe) or zinc sulfur selenide (ZnSSe).
  • a suitable template for this material system includes 1- 10 monolayers of zinc-oxygen (Zn-O) followed by 1-2 monolayers of an excess of zinc followed by the selenidation of zinc on the surface.
  • a template can be, for example, 1-10 monolayers of strontium-sulfur (Sr-S) followed by the ZnSeS.
  • Example 4 This embodiment of the invention is an example of structure 40 illustrated in FIG. 2.
  • Substrate 22, monocrystalline oxide layer 24, and monocrystalline compound semiconductor material layer 26 can be similar to those described in example 1.
  • an additional buffer layer 32 serves to alleviate any strains that might result from a mismatch of the crystal lattice of the accommodating buffer layer and the lattice of the monocrystalline semiconductor material.
  • Buffer layer 32 can be a layer of germanium or a GaAs, an aluminum gallium arsenide (AlGaAs), an indium gallium phosphide (InGaP), an aluminum gallium phosphide (AlGaP), an indium gallium arsenide (InGaAs), an aluminum indium phosphide (AllnP), an indium gallium arsenide phosphide (InGaAsP), or an indium gallium phosphide (InGaP) strain compensated superlattice.
  • buffer layer 32 includes a GaAsJ x superlattice, wherein the value of x ranges from 0 to 1.
  • buffer layer 32 includes an i y Ga ⁇ y P superlattice, wherein the value of y ranges from 0 to 1.
  • the lattice constant is varied from bottom to top across the superlattice to create a match between lattice constants of the underlying oxide and the overlying compound semiconductor material.
  • the compositions of other materials, such as those listed above, may also be similarly varied to manipulate the lattice constant of layer 32 in a like manner.
  • the superlattice can have a thickness of about 50-500 nm and preferably has a thickness of about 100-200 nm.
  • the template for this structure can be the same of that described in example 1.
  • buffer layer 32 can be a layer of monocrystalline germanium having a thickness of 1-50 nm and preferably having a thickness of about 2-20 nm.
  • a template layer of either germanium-strontium (Ge-Sr) or germanium-titanium (Ge-Ti) having a thickness of about one monolayer can be used as a nucleating site for the subsequent growth of the monocrystalline compound semiconductor material layer.
  • the formation of the oxide layer is capped with either a monolayer of strontium or a monolayer of titanium to act as a nucleating site for the subsequent deposition of the monocrystalline germanium.
  • the monolayer of strontium or titanium provides a nucleating site to which the first monolayer of germanium can bond.
  • Example 5 This example also illustrates materials useful in a structure 40 as illustrated in FIG. 2.
  • Substrate material 22, accommodating buffer layer 24, monocrystalline compound semiconductor material layer 26 and template layer 30 can be the same as those described above in example 2.
  • a buffer layer 32 is inserted between the accommodating buffer layer and the overlying monocrystalline compound semiconductor material layer.
  • the buffer layer a further monocrystalline semiconductor material, can be, for example, a graded layer of indium gallium arsenide (InGaAs) or indium aluminum arsenide (InAlAs).
  • buffer layer 32 includes InGaAs, in which the indium composition varies from 0 to about 47%.
  • the buffer layer preferably has a thickness of about 10-30 nm.
  • Varying the composition of the buffer layer from GaAs to InGaAs serves to provide a lattice match between the underlying monocrystalline oxide material and the overlying layer of monocrystalline compound semiconductor material.
  • Such a buffer layer is especially advantageous if there is a lattice mismatch between accommodating buffer layer 24 and monocrystalline compound semiconductor material layer 26.
  • Example 6 This example provides exemplary materials useful in structure 34, as illustrated in FIG. 3.
  • Substrate material 22, template layer 30, and monocrystalline compound semiconductor material layer 26 may be the same as those described above in connection with example 1.
  • Amorphous layer 36 is an amorphous oxide layer that is suitably formed of a combination of amorphous intermediate layer materials (e.g., layer 28 materials as described above) and accommodating buffer layer materials (e.g., layer 24 materials as described above).
  • amorphous layer 36 may include a combination of SiO x and Sr z Ba ⁇ z TiO 3 (where z ranges from 0 to l),which combine or mix, at least partially, during an anneal process to form amorphous oxide layer 36.
  • amorphous layer 36 may vary from application to application and may depend on such factors as desired insulating properties of layer 36, type of semiconductor material comprising layer 26, and the like. In accordance with one exemplary aspect of the present embodiment, layer 36 thickness is about 2 nm to about 100 nm, preferably about 2-10 nm, and more preferably about 5-6 nm.
  • Layer 38 comprises a monocrystalline compound semiconductor material that can be grown epitaxially over a monocrystalline oxide material such as material used to form accommodating buffer layer 24.
  • layer 38 includes the same materials as those comprising layer 26.
  • layer 38 also includes GaAs.
  • layer 38 may include materials different from those used to form layer 26.
  • layer 38 is about 1 monolayer to about 100 nm thick.
  • substrate 22 is a monocrystalline substrate such as a monocrystalline silicon substrate.
  • the crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation.
  • accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation.
  • the lattice constants of the accommodating buffer layer and the monocrystalline substrate must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved, i this context the terms
  • substantially equal and substantially matched mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer.
  • FIG. 4 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal.
  • Curve 42 illustrates the boundary of high crystalline quality material. The area to the right of curve 42 represents layers that tend to be polycrystalline. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly.
  • substrate 22 is a (100) or
  • (111) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate.
  • Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material by 45° with respect to the crystal orientation of the silicon substrate wafer.
  • the inclusion in the structure of amorphous interface layer 28, a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer that might result from any mismatch in the lattice constants of the host silicon wafer and the grown titanate layer.
  • a high quality, thick, monocrystalline titanate layer is achievable.
  • layer 26 is a layer of epitaxially grown monocrystalline material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation.
  • the lattice constant of layer 26 differs from the lattice constant of substrate 22.
  • the accommodating buffer layer must be of high crystalline quality.
  • substantial matching between the crystal lattice constant of the host crystal, in this case, the monocrystalline accommodating buffer layer, and the grown crystal is desired.
  • the grown crystal is gallium arsenide, aluminum gallium arsenide, zinc selenide, or zinc sulfur selenide and the accommodating buffer layer is monocrystalline substantial matching of crystal lattice constants of the two materials is achieved, wherein the crystal orientation of the grown layer is rotated by 45° with respect to the orientation of the host monocrystalline oxide.
  • the host material is a strontium or barium zirconate or a strontium or barium hamate or barium tin oxide and the compound semiconductor layer is indium phosphide or gallium indium arsenide or aluminum indium arsenide
  • substantial matching of crystal lattice constants can be achieved by rotating the orientation of the grown crystal layer by 45° with respect to the host oxide crystal.
  • a crystalline semiconductor buffer layer between the host oxide and the grown compound semiconductor layer can be used to reduce strain in the grown monocrystalline compound semiconductor layer that might result from small differences in lattice constants: Better crystalline quality in the grown monocrystalline compound semiconductor layer can thereby be achieved.
  • the following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a semiconductor structure such as the structures depicted in FIGS. 1 - 3.
  • the process starts by providing a monocrystalline semiconductor substrate comprising silicon or germanium.
  • the semiconductor substrate is a silicon wafer having a (100) orientation.
  • the substrate is preferably oriented on axis or, at most, about 0.5° off axis.
  • At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures.
  • the term "bare" in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material.
  • bare silicon is highly reactive and readily forms a native oxide.
  • the term "bare" is intended to encompass such a native oxide.
  • a thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process in accordance with the invention.
  • the native oxide layer In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer must first be removed to expose the crystalline structure of the underlying substrate. The following process is preferably carried out by molecular beam epitaxy (MBE), although other epitaxial processes may also be used in accordance with the present invention.
  • MBE molecular beam epitaxy
  • the native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus.
  • strontium the substrate is then heated to a temperature of about 750° C to cause the strontium to react with the native silicon oxide layer.
  • the strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface.
  • the resultant surface which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon.
  • the ordered 2 1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide.
  • the template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer.
  • the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750°C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer.
  • an alkali earth metal oxide such as strontium oxide, strontium barium oxide, or barium oxide
  • the substrate is cooled to a temperature in the range of about 200-800°C and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy.
  • the MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources.
  • the ratio of strontium and titanium is approximately 1:1.
  • the partial pressure of oxygen is initially set at a minimum value to grow stoichiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value.
  • the overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer.
  • the growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate.
  • the strontium titanate grows as an ordered monocrystal with the crystalline orientation rotated by 45° with respect to the ordered 2x1 crystalline structure of the underlying substrate. Strain that otherwise might exist in the strontium titanate layer because of the small mismatch in lattice constant between the silicon substrate and the growing crystal is relieved in the amorphous silicon oxide intermediate layer.
  • the monocrystalline strontium titanate is capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of a desired compound semiconductor material.
  • the MBE growth of the strontium titanate monocrystalline layer can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen.
  • arsenic is deposited to form a Ti-As bond, a Ti-O-As bond or a Sr-O-As.
  • FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with the present invention.
  • Single crystal SrTiO 3 accommodating buffer layer 24 was grown epitaxially on silicon substrate 22. During this growth process, amorphous interfacial layer 28 is formed which relieves strain due to lattice mismatch.
  • GaAs compound semiconductor layer 26 was then grown epitaxially using template layer 30.
  • FIG. 6 illustrates an x-ray diffraction spectrum taken on structure
  • GaAs compound semiconductor layer 26 grown on silicon substrate 22 using accommodating buffer layer 24.
  • the peaks in the spectrum indicate that both the accommodating buffer layer 24 and GaAs compound semiconductor layer 26 are single crystal and (100) orientated.
  • the structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of an additional buffer layer deposition step.
  • the buffer layer is formed overlying the template layer before the deposition of the monocrystalline compound semiconductor layer. If the buffer layer is a compound semiconductor superlattice, such a superlattice can be deposited, by MBE for example, on the template described above. If instead the buffer layer is a layer of germanium, the process above is modified to cap the strontium titanate monocrystalline layer with a final layer of either strontium or titanium and then by depositing germanium to react with the strontium or titanium. The germanium buffer layer can then be deposited directly on this template.
  • Structure 34 may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate 22, and growing semiconductor layer 38 over the accommodating buffer layer, as described above.
  • the accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer 36.
  • the anneal process may be carried out subsequent to growth of layer 26.
  • layer 36 is formed by exposing substrate 22, the accommodating buffer layer, the amorphous oxide layer, and semiconductor layer 38 to a rapid thermal anneal process with a peak temperature of about 700°C to about 1000°C and a process time of about 10 seconds to about 10 minutes.
  • a rapid thermal anneal process with a peak temperature of about 700°C to about 1000°C and a process time of about 10 seconds to about 10 minutes.
  • other suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention.
  • laser annealing or "conventional" thermal annealing processes in the proper environment
  • an overpressure of one or more constituents of layer 30 may be required to prevent degradation of layer 38 during the anneal process.
  • the anneal environment preferably includes an overpressure of arsenic to mitigate degradation of layer 38.
  • layer 38 of structure 34 may include any materials suitable for either of layers 32 or 26. Accordingly, any deposition or growth methods described in connection with either layer 32 or 26 may be employed to deposit layer 38.
  • FIG. 7 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with the embodiment of the invention illustrated in FIG. 3.
  • TEM Transmission Electron Micrograph
  • a single crystal SrTiO 3 accommodating buffer layer was grown epitaxially on silicon substrate 22. During this growth process, an amorphous interfacial layer forms as described above.
  • GaAs layer 38 is formed above the accommodating buffer layer and the accommodating buffer layer is exposed to an anneal process to form amorphous oxide layer 36.
  • FIG. 8 illustrates an x-ray diffraction spectrum taken on a structure including GaAs compound semiconductor layer 38 and amorphous oxide layer 36 formed on silicon substrate 22.
  • the peaks in the spectrum indicate that GaAs compound semiconductor layer 38 is single crystal and (100) orientated and the lack of peaks around 40 to 50 degrees indicates that layer 36 is amorphous.
  • the process described above illustrates a process for forming a semiconductor structure including a silicon substrate, an overlying oxide layer, and a monocrystalline gallium arsenide compound semiconductor layer by the process of molecular beam epitaxy.
  • the process can also be carried out by the process of chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy (MEE), atomic layer epitaxy (ALE), physical vapor deposition (PVD), chemical solution deposition (CSD), pulsed laser deposition (PLD), or the like.
  • CVD chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • MEE migration enhanced epitaxy
  • ALE atomic layer epitaxy
  • PVD physical vapor deposition
  • CSSD chemical solution deposition
  • PLD pulsed laser deposition
  • monocrystalline accommodating buffer layers such as alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown.
  • perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide
  • MBE III-V and II- VI monocrystalline compound semiconductor layers can be deposited overlying the monocrystalline oxide accommodating buffer layer.
  • Each of the variations of compound semiconductor materials and monocrystalline oxide accommodating buffer layer uses an appropriate template for initiating the growth of the compound semiconductor layer.
  • the oxide can be capped by a thin layer of zirconium.
  • the deposition of zirconium can be followed by the deposition of arsenic or phosphorus to react with the zirconium as a precursor to depositing indium gallium arsenide, indium aluminum arsenide, or indium phosphide respectively.
  • the monocrystalline oxide accommodating buffer layer is an alkaline earth metal hafnate, the oxide layer can be capped by a thin layer of hafnium.
  • hafnium is followed by the deposition of arsenic or phosphorous to react with the hafnium as a precursor to the growth of an indium gallium arsenide, indium aluminum arsenide, or indium phosphide layer, respectively.
  • strontium titanate can be capped with a layer of strontium or strontium and oxygen and barium titanate can be capped with a layer of barium or barium and oxygen.
  • Each of these depositions can be followed by the deposition of arsenic or phosphorus to react with the capping material to form a template for the deposition of a compound semiconductor material layer comprising indium gallium arsenide, indium aluminum arsenide, or indium phosphide.
  • FIG. 9 illustrates schematically, in cross section, a device structure 900 in accordance with a further embodiment of the invention.
  • Device structure 900 includes a monocrystalline semiconductor substrate 901 , preferably a monocrystalline silicon wafer.
  • Monocrystalline semiconductor substrate 901 includes two regions, 902 and 903.
  • An electrical semiconductor component generally indicated by the dashed line 911 is formed in region 902.
  • Electrical component 911 can be a resistor, a capacitor, an active semiconductor component such as a diode or a transistor, or an integrated circuit such as a MOS integrated circuit.
  • electrical component 911 can be a MOS circuit configured to perform digital signal processing or another function for which silicon integrated circuits are well suited.
  • the electrical semiconductor component in region 902 can be formed by conventional semiconductor processing as well known and widely practiced in the semiconductor industry.
  • a layer of insulating material 904 such as a layer of silicon dioxide or the like may overlie electrical semiconductor component 911.
  • Insulating material 904 and any other layers that may have been formed or deposited during the processing of semiconductor component 911 in region 902 are removed from the surface of region 903 to provide a bare substrate surface in that region, for example, a bare silicon surface.
  • bare silicon surfaces are highly reactive and a native silicon oxide layer can quickly form on the bare surface.
  • a layer of barium or barium and oxygen maybe deposited onto the native oxide layer on the surface of region 903 and then reacted with the oxidized surface to form a template layer 907.
  • a monocrystalline oxide layer 906 is formed overlying the template layer by a process of molecular beam epitaxy (MBE).
  • reactants including barium, titanium, and oxygen are deposited on the template layer to form the monocrystalline oxide layer.
  • the partial pressure of oxygen is kept near the minimum necessary to fully react with the barium and titanium to form a monocrystalline barium titanate layer 906.
  • the partial pressure of oxygen is then increased to provide an overpressure of oxygen and to allow oxygen to diffuse through the growing monocrystalline oxide layer.
  • the oxygen diffusing through the barium titanate reacts with silicon at the surface of region 903 to form an amorphous layer 905 at the interface between the silicon substrate and the monocrystalline oxide.
  • an amorphous oxide layer comprising material from layer 905 and 906 can be formed by epitaxially forming a monocrystalline oxide layer 906 and subsequently heat treating the resulting structure to convert the monocrystalline oxide to an amorphous oxide, as discussed below.
  • the step of depositing the monocrystalline oxide layer 906 is followed by depositing an intermediate oxide transition layer 908.
  • Transition layer 908 generally comprises an ordered, crystalline metal oxide, such as magnesium oxide (MgO), tantalum oxide (TaO), or manganese oxide (MnO), and is preferably grown by an MBE process.
  • the step of depositing the transition layer 908 is followed by depositing a second template layer 909, which can be, for example, 1-10 monolayers of gallium antimonide (GaSb), InMgO, or MgAsO.
  • Template layer 909 serves as a "seed" layer to aid in formation of an overlying monocrystalline compound semiconductor layer 910.
  • monocrystalline compound semiconductor layer 910 comprises a semiconductor material particularly suitable for use in the formation of highly reliable, sensitive Hall sensor devices, such as InAs or GaAsSb.
  • the monocrystalline titanate layer and the silicon oxide layer which is interposed between substrate 901 and the titanate layer, are exposed to an anneal process such that the titanate and oxide layers form an amorphous oxide layer.
  • An additional compound semiconductor layer 910 is then epitaxially grown over layers 908 and 909.
  • the above described anneal process can be performed after formation of template layer 909 or compound semiconductor layer 910.
  • a semiconductor component is formed in compound semiconductor layer 910.
  • Semiconductor component 912 can be formed by processing steps conventionally used in the fabrication of indium arsenide or other III-V compound semiconductor material devices.
  • Semiconductor component 912 may be any active or passive component, and preferably is a Hall sensor, tunnel diode, light emitting diode, semiconductor laser, photodetector, heterojunction bipolar transistor (HBT), high frequency MESFET, or other component that utilizes and takes advantage of the physical properties of compound semiconductor materials.
  • HBT heterojunction bipolar transistor
  • a metallic conductor schematically indicated by the line 913 can be formed to electrically couple device 912 and device 911, thus implementing an integrated device that includes at least one component formed in the silicon substrate and one device formed in the monocrystalline compound semiconductor material layer.
  • illustrative structure 900 has been described as a structure formed on a silicon substrate 901 and having a barium titanate layer 906 and an InAs or GaAsSb layer 910, similar devices can be fabricated using other monocrystalline substrates, monocrystalline oxide layers and other monocrystalline compound semiconductor layers as described elsewhere in this disclosure.
  • FIG. 10 illustrates a semiconductor structure 1000 in accordance with a further embodiment of the invention
  • structure 1000 is a Hall sensor formed of monocrystalline epitaxial layers of compound semiconductor material on a monocrystalline silicon substrate.
  • Structure 1000 includes a monocrystalline semiconductor substrate 1001, such as a monocrystalline silicon wafer.
  • An amorphous oxide layer 1002 is preferably formed overlying substrate 1001, in accordance with the process described above.
  • An accommodating buffer layer 1003 is formed overlying substrate 1001 and amorphous oxide layer 1002.
  • amorphous oxide layer 1002 may be grown at the interface between substrate 1001 and the growing accommodating buffer layer 1003 by the oxidation of substrate 1001 during the growing of layer 1003.
  • Accommodating buffer layer 1003 is preferably a monocrystalline oxide material selected for its crystalline compatibility with the underlying substrate and with the overlying compound semiconductor material.
  • layer 1003 may comprise, for example, an alkali earth metal titanate such as barium titanate or strontium titanate, an alkali earth metal hafnate such as barium hamate or strontium hafnate, or an alkali earth metal zirconate such as barium zirconate or strontium zirconate.
  • Transition layer 1004 is preferably formed overlying layer 1003 to alleviate any strains that might result from a mismatch of the crystal lattice of accommodating buffer layer 1003 and the lattice of the monocrystalline semiconductor material layer.
  • Transition layer 1004 can comprise any suitable oxide material, such as manganese oxide (MnO), magnesium oxide (MgO), or tantalum oxide (TaO).
  • MnO manganese oxide
  • MgO magnesium oxide
  • TaO tantalum oxide
  • transition layer 1004 is a layer of MgO and can have a thickness of about 10 to about 100 nm and preferably a thickness of about 50 nm. The thickness generally depends on the application for which the layer is being prepared.
  • a template layer 1005 may be formed by capping the oxide layer.
  • the template layer is preferably 1-10 monolayers of Ga-Sb, Ga-Mg-O-Sb, In-Mg-O, or Mg-As-O.
  • a monocrystalline compound semiconductor material layer 1006 is then formed overlying template layer 1005, preferably by MBE.
  • Compound semiconductor material layer 1006 preferably comprises a material that is highly sensitive and has a large electron mobility over a wide temperature range, such as InAs or GaAsSb.
  • layer 1006 comprises a layer of InAs having a thickness of from about 10 to 1000 nm.
  • semiconductor device structure 1000 comprises an InAs Hall sensor device. Structures and methods of fabricating InAs Hall sensor devices are well known to those skilled in the art. As illustrated in FIG. 10, after formation of InAs layer 1006, spaced- apart conductive electrodes 1007 and 1008 are formed overlying layer 1006 in accordance with well-known fabrication techniques. A passivation layer 1009 is formed overlying electrodes 1007 and 1008 and insulates the region between the electrodes. A floating semiconductor device 1010 is then formed on passivation layer 1009 and may comprises any suitable device known in the art, such as, for example, an accelerometer. Electrical connections may then be made to the devices according to conventional techniques available to those skilled in the art. If device 1010 is desirably formed of monocrystalline material, then layer 1009 is preferably monocrystalline.
  • Monolithic integrated circuit 1100 generally includes a MOS circuit 1140 electrically coupled to a Hall sensor.
  • MOS circuit 1140 is electrically coupled to an InAs Hall sensor 1130, such as that exhibited in FIG. 10.
  • semiconductor substrate 1101 is a monocrystalline silicon substrate, such as a silicon wafer, and has two regions, 1102 and 1103.
  • template layer 1108, amorphous oxide layer 1109, monocrystalline oxide layer 1110, intermediate oxide transition layer 1111, template layer 1112, monocrystalline compound semiconductor material layer 1113, and electrodes 1114 and 1115 are formed of the same materials and by the same processing steps as those described with reference to the fabrication of the Hall sensor device of FIG. 10. For sake of brevity, formation of these components will not be discussed additionally with relation to FIG. 11.
  • MOS circuit 1140 is first formed in semiconductor substrate 1101 using conventional processing steps and techniques well known to those skilled in the art.
  • MOS circuit 1140 generally comprises a gate electrode 1107, a gate dielectric layer 1106, and n+ doped regions 1104 and 1105.
  • Gate dielectric layer 1106 is formed in region 1102 of substrate 1101, and gate electrode 1107 is then formed over gate dielectric layer 1106.
  • Selective n-type doping is performed to form n+ doped regions 1104 and 1105 within substrate 1101 along adjacent sides of gate electrode 1107 and are source, drain, or source/drain regions for the MOS transistor.
  • the n+ doped regions 1104 and 1105 have a doping concentration of at least about 1E18 atoms per cubic centimeter.
  • Ohmic contacts 1118 and 1119 may be formed on gate electrode 1107 and electrode 1114, respectively, using standard processing techniques well known in the art.
  • An insulating layer 1121 is formed over substrate 1101, MOS circuit 1140, and Hall sensor 1130. Portions of insulating layer 1121 are then removed to define contact openings where the devices are to be interconnected. Interconnect trenches are formed within insulating layer 1121 to provide the lateral connections between the contacts. As illustrated in FIG. 11, interconnect 1120 connects the gate electrode of the MOS transistor to an electrode 1114 of Hall sensor 1130.
  • a passivation layer 1116 is foraied over the interconnect 1120 and insulating layer 1121. Following formation of passivation layer 1116, device 1117 may be formed on Hall sensor 1130 in the region defined by electrodes 1114 and 1115. Device 1117 maybe any floating device suitable for use in connection with Hall sensor 1130, such as, for example, an accelerometer. Other electrical connections may be made to the devices and/or other electrical or electronic components within the integrated circuit 1100 but not illustrated in the figure according to conventional techniques available to those skilled in the art.
  • the compound semiconductor portion may include light emitting diodes, photodetectors, diodes, or the like
  • the Group IV semiconductor portions can include digital logic, memory arrays, and most structures that can be formed in conventional MOS integrated circuits.
  • a monocrystalline Group IV wafer can also be used in forming only compound semiconductor electrical components over the wafer.
  • the wafer is essentially a "handle" wafer used during the fabrication of the compound semiconductor electrical components within a monocrystalline compound semiconductor layer overlying the wafer. Therefore, electrical components can be formed within II-V or II-IV semiconductor materials over a wafer of at least approximately 200 millimeters in diameter and possibly at least approximately 300 millimeters.
  • a relatively inexpensive "handle" wafer overcomes the fragile nature of the compound semiconductor wafers by placing them over a relatively more durable and easy to fabricate base material. Therefore, an integrated circuit can be formed such that all electrical components, and particularly all active electronic devices, can be formed within the compound semiconductor material even though the substrate itself may include a Group IV semiconductor material. Fabrication costs for compound semiconductor devices should decrease because larger substrates can be processed more economically and more readily compared to relatively smaller and more fragile conventional compound semiconductor wafers.
  • Sb-based materials such as indium antimonide (InSb), aluminum antimonide (AlSb), indium aluminum antimonide (InAlSb), gallium antimonide (GaSb), indium gallium antimonide (InGaSb), and aluminum gallium antimonide (AlGaSb) for a Hall-effect active layer is possible in accordance with the present invention.
  • the present invention may be applicable to any Hall effect device or other semiconductor device structures in any III- V or other compound semiconductor that can be lattice-matched to silicon using a perovskite or other appropriate oxide.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

Selon la présente invention, on peut faire croître des couches épitaxiales de matériaux semi-conducteurs composés (1113) de grande qualité aptes à être utilisés dans des dispositifs à effet Hall sur de grandes tranches de silicium (1101) en faisant d'abord croître une couche tampon de réception (1110) sur une tranche de silicium. La couche tampon de réception est une couche d'oxyde monocristallin qui est séparée de la tranche de silicium par une couche d'interface amorphe (1109) en oxyde de silicium. La couche d'interface amorphe dissipe les tensions mécaniques et permet la croissance d'une couche tampon de réception en oxyde monocristallin de grande qualité. La couche d'interface amorphe permet de résoudre tout mésappariement de réseau pouvant se produire entre la couche tampon et le substrat en silicium sous-jacent.
PCT/US2001/024559 2000-08-18 2001-08-03 Capteur de hall a semi-conducteurs composes WO2002016955A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001279196A AU2001279196A1 (en) 2000-08-18 2001-08-03 Compound semiconductor hall sensor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US64255800A 2000-08-18 2000-08-18
US09/642,558 2000-08-18

Publications (2)

Publication Number Publication Date
WO2002016955A2 true WO2002016955A2 (fr) 2002-02-28
WO2002016955A3 WO2002016955A3 (fr) 2002-06-27

Family

ID=24577094

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/024559 WO2002016955A2 (fr) 2000-08-18 2001-08-03 Capteur de hall a semi-conducteurs composes

Country Status (3)

Country Link
AU (1) AU2001279196A1 (fr)
TW (1) TW515097B (fr)
WO (1) WO2002016955A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016181391A1 (fr) * 2015-05-11 2016-11-17 Technion Research & Development Foundation Limited Capteur d'image et son procédé de fabrication

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3670213A (en) * 1969-05-24 1972-06-13 Tokyo Shibaura Electric Co Semiconductor photosensitive device with a rare earth oxide compound forming a rectifying junction
US5406202A (en) * 1991-12-21 1995-04-11 Deutsche Itt Industries Gmbh Offset-compensated hall sensor having plural hall detectors having different geometrical orientations and having switchable directions
EP0682266A1 (fr) * 1994-05-09 1995-11-15 General Motors Corporation Capteur pour champs magnétiques
US5528067A (en) * 1995-05-08 1996-06-18 Hughes Aircraft Company Magnetic field detection
US5883564A (en) * 1994-04-18 1999-03-16 General Motors Corporation Magnetic field sensor having high mobility thin indium antimonide active layer on thin aluminum indium antimonide buffer layer
EP0964259A1 (fr) * 1997-02-28 1999-12-15 Asahi Kasei Electronics Co. Ltd. Detecteur magnetique

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57118683A (en) * 1981-01-17 1982-07-23 Toshiba Corp Manufacture of callium arsenide hall device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3670213A (en) * 1969-05-24 1972-06-13 Tokyo Shibaura Electric Co Semiconductor photosensitive device with a rare earth oxide compound forming a rectifying junction
US5406202A (en) * 1991-12-21 1995-04-11 Deutsche Itt Industries Gmbh Offset-compensated hall sensor having plural hall detectors having different geometrical orientations and having switchable directions
US5883564A (en) * 1994-04-18 1999-03-16 General Motors Corporation Magnetic field sensor having high mobility thin indium antimonide active layer on thin aluminum indium antimonide buffer layer
EP0682266A1 (fr) * 1994-05-09 1995-11-15 General Motors Corporation Capteur pour champs magnétiques
US5528067A (en) * 1995-05-08 1996-06-18 Hughes Aircraft Company Magnetic field detection
EP0964259A1 (fr) * 1997-02-28 1999-12-15 Asahi Kasei Electronics Co. Ltd. Detecteur magnetique

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016181391A1 (fr) * 2015-05-11 2016-11-17 Technion Research & Development Foundation Limited Capteur d'image et son procédé de fabrication

Also Published As

Publication number Publication date
WO2002016955A3 (fr) 2002-06-27
TW515097B (en) 2002-12-21
AU2001279196A1 (en) 2002-03-04

Similar Documents

Publication Publication Date Title
US7105866B2 (en) Heterojunction tunneling diodes and process for fabricating same
US6638838B1 (en) Semiconductor structure including a partially annealed layer and method of forming the same
US6673646B2 (en) Growth of compound semiconductor structures on patterned oxide films and process for fabricating same
US6559471B2 (en) Quantum well infrared photodetector and method for fabricating same
EP1346399A2 (fr) Substrat adaptatif a semi-conducteur comportant une couche monocristalline calibree
US6667196B2 (en) Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method
US20020140012A1 (en) Semiconductor structures and devices for detecting far-infrared light and methods for fabricating same
US20020195599A1 (en) Low-defect semiconductor structure, device including the structure and method for fabricating structure and device
US20030027409A1 (en) Germanium semiconductor structure, integrated circuit, and process for fabricating the same
US20030013218A1 (en) Structure and method for fabricating semiconductor structures and devices for detecting chemical reactant
US20030013319A1 (en) Semiconductor structure with selective doping and process for fabrication
US20020076906A1 (en) Semiconductor structure including a monocrystalline film, device including the structure, and methods of forming the structure and device
US20030020121A1 (en) Semiconductor structure for monolithic switch matrix and method of manufacturing
US20030089921A1 (en) Structure and method for fabricating semiconductor structures and devices utilizing the formation of a compliant substrate having a niobium concentration
US20030020114A1 (en) Metal-insulator-transition field-effect transistor utilizing a compliant substrate and method for fabricating same
US20020000584A1 (en) Semiconductor structure and device including a monocrystalline conducting layer and method for fabricating the same
US20030038299A1 (en) Semiconductor structure including a compliant substrate having a decoupling layer, device including the compliant substrate, and method to form the structure and device
US20030034545A1 (en) Structure and method for fabricating semiconductor structures with switched capacitor circuits
US20020167070A1 (en) Hybrid semiconductor structure and device
US20030015711A1 (en) Structure and method for fabricating semiconductor structures and devices utilizing the formation of a complaint substrate with an intermetallic layer
WO2002016955A2 (fr) Capteur de hall a semi-conducteurs composes
US20020180049A1 (en) Structure and method for fabricating semiconductor devices
US20030020137A1 (en) Structure and method for fabricating semiconductor inductor and balun structures utilizing the formation of a compliant substrate
WO2003007353A1 (fr) Structures a semi-conducteurs comprenant une couche de semi-conducteurs de composes dopes a l'oxygene
US20030122130A1 (en) Structure and method for fabricating semiconductor structures and devices utilizing the formation of a compliant substrate having a mechanical decoupling layer

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP