TW515097B - Compound semiconductor hall sensor and process for fabricating same - Google Patents

Abstract

High quality epitaxial layers of compound semiconductor materials (1113) suitable for use in connection with Hall-effect devices can be grown overlying large silicon wafers (1101) by first growing an accommodating buffer layer (1110) on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (1109) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Description

515097 A7 B7 V. Description of the invention (1) This application has been filed in the United States under the patent ‘Application No. 09 = 642558 on August 18, 2000. Scope of the Invention The present invention is generally related to semiconductor structures and devices and methods of making the same, and more specifically to the use of synthetic semiconductor films, such as indium arsenide (InAs) and / or gallium arsenide (GaAsSb) films, grown on monocrystalline silicon. The manufacture and use of Hall sensors on semiconductor substrates are related.

Background of the Invention

The vast majority of individual semiconductor devices and integrated circuits are made of silicon, at least in part because of the availability of inexpensive, southern-quality pre-crystallized substrates. Other materials, such as synthetic semiconductor materials, have physical properties including energy steps that are wider than silicon and / or higher mobility or direct energy steps that make these materials more advantageous than some forms of semiconductor devices. Unfortunately, synthetic semiconductor materials are usually more expensive than silicon and are not available as large wafers as silicon. Gallium arsenide (GaAs), the most readily available synthetic semiconductor material, is only available on wafers with a diameter of about 150 millimeters (mm). In contrast, silicon wafers are available up to about 300 mm, and are widely available at 200 mm. 150mm GaAs wafers are many times more expensive than their silicon counterparts. Wafers of other synthetic semiconductor materials are even less available and more expensive than GaAs. Because of the required properties of synthetic semiconductor materials and because of their generally high cost and low availability now in bulk, there have been many years of attempts to grow thin films of synthetic semiconductor materials on heterogeneous substrates. In order to achieve the best characteristics of synthetic semiconductor materials, however, single crystal silicon films with high crystal quality are required. Attempts have been made, for example, to increase the layer of monocrystalline silicon synthetic semiconductor materials in germanium, -4- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 515097 A7 B7 V. Description of the invention (2) Silicon And many insulators. In general, these attempts were unsuccessful because the lattice mismatch between the host crystal and the growing crystal resulted in a thin film of synthetic semiconductor material of low crystalline silicon quality. If large-area thin films of high-quality monocrystalline silicon synthetic semiconductor materials can be obtained at low cost, many semiconductor devices can be advantageously fabricated on large wafers of synthetic semiconductor materials or epitaxially with such materials. Thin films are also manufactured on large wafers of synthetic semiconductor materials at low cost. In addition, if a thin film of high-quality single crystal silicon synthetic semiconductor material can be realized on a large wafer such as a silicon wafer, for example, an optoelectronic device such as a laser diode, a light emitting diode, Photodiodes or heterojunction piercing devices utilize the best properties of both silicon and synthetic semiconductor materials. Hall devices, such as Hall sensors, are usually four-pole devices used to detect magnetic fields. In a typical Hall sensor, the semiconductor layer has two electrodes for passing current in a first direction through the semiconductor layer and two additional electrodes for detecting and detecting when a detected magnetic field passes through the semiconductor layer. The voltage at which the current crosses. When cost is most important, Hall sensors usually use η-form silicon and GaAs at higher temperature capabilities because of their larger energy steps. In addition, inAs, indium antimonide (InSb), and other semiconductor materials have gained popularity because of their higher carrier mobility, resulting in the greater sensitivity and frequency response capabilities of silicon Hall sensors typically at 10-20 kHz . For example, the InAs Hall sensor has an output voltage that is not very dependent on temperature, has good stability against pulse voltage noise, low offset compensation, and low noise properties for low magnetic field sensing. -5- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Pretend

Line 515097 A7 B7 V. Description of the invention (3) Because of the developing electronics industry, the demand for Hall sensors is growing rapidly. As demand increases, there is a need for materials that are highly sensitive to large electron mobility over a wide temperature range. The compatibility of Hall sensor materials with semiconductor substrates is important because Hall sensors are often used in integrated devices that include other semiconductor substrates. InAs is a good material for use in Hall sensors because of its high electron mobility compared to other III-V synthetic semiconductor materials. One of the difficulties in using InAs in the past has been, however, the lack of an insulating substrate whose lattice matches that of InAs to enable the growth of high-quality InAs films. For example, the existing InAs film grown by molecular beam epitaxy (MBE) exhibits a 7% lattice mismatch on GaAs, which results in many uncomfortable differences in the InAs / GaAs interface, thus reducing the electronic properties of InAs films, such as Mobility. Therefore, there is a need for a peninsula structure that provides high-quality monocrystalline silicon synthetic semiconductor films, such as InAs, and another monocrystalline material, such as a semiconductor substrate of GaAs or silicon, and a process for manufacturing such a structure. Brief Description of the Drawings The present invention is illustrated by way of example but not limited to the accompanying drawings, in which similar reference numbers indicate similar elements, and in which: Figures 1-3 schematically illustrate many specific implementations according to the present invention in cross section. Example device structure; Figure 4 illustrates the relationship between the maximum achievable film thickness and the lattice mismatch between the parasitic crystal and the growing crystal structure cover; Figure 5 illustrates the inclusion of a single crystal silicon containing buffer layer Structure of high-resolution transmission electron micrograph; -6-This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 515097 A7 B7 V. Description of the invention (4) Figure 6 illustrates the inclusion of single crystal X-ray diffraction spectrum of the structure containing the buffer layer; Figure 7 illustrates a high-resolution transmission electron micrograph of a structure including an amorphous oxide layer; Figure 8 illustrates an X-ray structure including an amorphous broken oxide layer Diffraction spectrum; FIG. 9 schematically illustrates a single integrated circuit according to a specific embodiment of the present invention in a cross-section; and FIGS. 10-11 illustrate the specific embodiment according to a still further example of the present invention in a cross-section. Examples of the device configuration application. Those skilled in the art will understand that the components in the figure are illustrated for simplicity and clarity, so there is no need to draw to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of specific embodiments of the invention. Detailed description of the schema

The present invention provides a template that reduces the lattice misalignment between InAa and the underlying insulating substrate to less than about 2% and provides a method for growing InAs on a semiconductor substrate or layer, thereby allowing Hall sensors to be used. Single integration with complementary gold silicon oxide integrated circuits. Fig. 1 schematically illustrates a part of a semiconductor substrate 20 according to a specific embodiment of the present invention in a section. The semiconductor substrate 20 includes a single crystal silicon substrate 22, a buffer region 24 including a single crystal silicon material, and a layer 26 of a single crystal silicon synthetic semiconductor material. In this context, the word "single crystal silicon" has a meaning commonly used in the semiconductor industry. This term refers to single crystals or materials that are basically single crystals and includes those materials that are usually in silicon or germanium or a mixture of silicon and germanium. This paper applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 515097 A7 B7 V. The relatively small number of defects found in the base material of the invention description (5), such as the materials of the differential row, etc., and the epitaxial layer of such materials often found in the semiconductor industry. According to a specific embodiment of the present invention, the substrate 20 also includes an amorphous silicon intermediate layer 28 located between the substrate 22 and the accommodating buffer layer 24. The substrate 20 may also include a template layer 30 between the containment buffer layer and the synthetic semiconductor layer 26. As will be explained more fully below, the template layer helps initiate the growth of the synthetic semiconductor layer on the containment buffer layer. The amorphous silicon intermediate layer helps to release the pressure in the accommodating buffer layer and thereby helps the growth of the crystalline buffer layer of high crystalline silicon quality. According to a specific embodiment of the present invention, the substrate 22 is a single crystal silicon semiconductor wafer, preferably a large diameter. The wafer may be a material from the IV group of the periodic table and is preferably a material from the IVA group. Examples of Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like. Preferably, the substrate 22 is a wafer containing silicon or germanium, and is preferably a high-quality single crystal silicon wafer used in the semiconductor industry. The containing buffer layer 24 is preferably a single crystal silicon oxide or a nitrogen material epitaxially grown on the underlying substrate. According to a specific embodiment of the present invention, during the growth of the layer 24, the amorphous silicon intermediate layer 28 is grown on the substrate 22 by the oxidation of the substrate 22, and between the substrate 22 and the growing buffer zone layer. Interface. The release of the intermediate layer of amorphous silicon that might otherwise occur in the single-crystal silicon containing buffer layer is due to the difference in the lattice constants of the substrate and buffer layer. As used herein, the lattice constant refers to the distance between atoms of a unit as measured in the surface plane. If this pressure is not released by the amorphous silicon interlayer, the pressure may cause the crystalline silicon structure in the buffer layer to be accommodated. -8- This paper size applies to China National Standard (CNS) A4 (210X 297 mm)

Installation t 515097 A7 B7 V. Defects in the description of the invention (6). Defects in the spar structure that accommodates the buffer layer may, in turn, make it difficult to achieve a high-quality crystalline silicon structure system in the single crystal silicon synthetic semiconductor layer 26. The accommodating buffer layer 24 is preferably a single-crystal silicon oxide or a nitrogen material that is compatible with the underlying substrate and the crystalline silicon of the synthetic semiconductor material covered. For example, the material may be an oxide or nitride having a lattice structure that is substantially consistent with the substrate and / or the semiconductor material used successively. Materials suitable for containing the buffer layer include metal oxides, such as soil test element osmium salt, alkaline earth element hammer acid salt, alkaline earth element osmium salt, alkaline earth element thionate, alkaline earth element ruthenate, alkaline earth element niobate , Alkaline earth element vanadates, calcium mineral oxides such as soil-based element tin-based ore, lanthanate, lanthanum oxide, and chaotic oxides. In addition, many oxynitrides, such as gallium nitride, aluminum nitride, and boron nitride, can also be used to accommodate the buffer layer. Although gill ruthenates are conductors, most of these materials are insulators. Generally, these materials are metal oxides or metal nitrides, and more specifically, these metal oxides or nitrides usually include at least two different metal elements. In some specific applications, the metal oxide or nitride may include three or more different metal elements. The amorphous broken interface layer 28 is preferably an oxide formed by the oxidation of the surface of the substrate 22, and is preferably composed of silicon oxide. The thickness of the layer 28 is sufficient to release the pressure that causes the lattice constants between the substrate 22 and the buffer zone layer 24 to be inconsistent. Generally, layer 28 has a thickness in the range of approximately 0.5-5 nanometers. When special semiconductor substrates are needed, any of the IIIA and VA group elements (III-V semiconductor composites), mixed m-γ composites, Π (Α or B), and this paper size are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 515097 A.7 B7 V. Description of the invention (7) VIA group element (II-VI semiconductor composition) and mixed π-νΐ composition selected layer 26 of synthetic semiconductor material. Examples include GaAs, GalnAs, GaAlAa, InP, CdS, CdHgTe, Zinc Selenide (ZnSe), zinc sulfur selenide (ZnSSe), and so on. A suitable template material is chemically bonded to the surface of the containing buffer layer 24 at a selected location, and a location is provided for nucleation of the epitaxial growth of the successive synthetic semiconductor layer 26. Suitable materials for the template 30 are discussed below. FIG. 2 illustrates, in cross section, a portion of a semiconductor structure 40 according to a further embodiment of the present invention. The structure 40 is similar to the semiconductor structure 20 previously described, except that an additional buffer layer 32 is located between the layer containing the buffer layer 24 and the layer of the single crystal silicon composite semiconductor material 26. Specifically, the additional buffer layer is located between the template layer 30 and the cover layer of the synthetic semiconductor material. When the lattice constant of the buffer region layer does not properly fit the covered single crystal silicon synthetic semiconductor material layer ', an additional buffer region layer formed of a semiconductor or a synthetic semiconductor material is used to provide lattice compensation. Fig. 3 schematically illustrates a part of a semiconductor structure 34 according to another exemplary embodiment of the present invention in a cross section. Structure 34 is similar to structure 20, except that structure 34 includes an amorphous silicon layer 36 instead of containing the buffer layer 24, the amorphous silicon interface layer 28, and the additional semiconductor layer 38. As explained in more detail below, the amorphous silicon layer 36 may be formed by first forming a receiving buffer layer and an amorphous silicon interface layer in a manner similar to that described above. The single crystal second semiconductor layer 38 is then formed (by the growth of the system crystal) to cover the single crystal fragment holding buffer layer. The storage buffer layer is then exposed to the tempering system. -10- This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 515097 A7 B7. 5. Description of the invention (8) process to convert the single crystal silicon Hold the buffer layer to the amorphous silicon layer. The amorphous silicon layer 36 formed in this manner includes materials from both the containment buffer and the interface layer, where the amorphous shredded layer may or may not be amalgamated. Therefore, the sound level is low. 乂 contains one or two amorphous silicon layers. The formation of the amorphous stone layer 36 (subsequent to the formation of layer 38) between the substrate 22 and the semiconductor layer 38 releases the pressure between the layers 22 and% and provides a compatible substrate in a sequential process. For example, Formation of a synthetic half-effect layer 26. Together with the previously described processes of Figures 1 and 2, the process is suitable for growing single crystal dreams. A synthetic semiconductor layer is on a single crystal second substrate. However, the process described in conjunction with Figure 3, including the conversion of the single crystal silicon containing buffer layer to the amorphous silicon oxide layer, is better for growing single crystal silicon synthetic semiconductor layers because it allows any pressure in the layer to be released. ㈢ The semiconductor layer 38 may include any material described in this application in relation to the synthetic semiconductor material layer 26 or the additional buffer layer 32. For example, the layer 38 may include a group of single crystal silicon ... or a single crystal silicon composite semiconductor material. According to a specific embodiment of the present invention, the semiconductor layer 38 serves as a tempered cover during the formation of the layer 36 and serves as a template for the subsequent formation of the semiconductor layer 26. Therefore, the 'layer 38 is preferably thick enough to provide a suitable template for the growth of the layer 26 (at least a single layer) and thin enough to allow the layer 38 to form a single crystal shredded semiconductor composition that is substantially free of defects. According to another specific embodiment of the present invention, the semiconductor layer 38 includes a synthetic semiconductor material that is thick enough to form a device within the layer 38 (e.g., the materials discussed above in relation to the synthetic semiconductor layer 26). In this case, the semiconductor structure according to the present month does not include the synthetic semiconductor layer 26. In other words -11-This paper size applies the Chinese National Standard (CNS) A4 specification (21 × 297 mm) 515097 A7 B7 V. Description of the invention (9) Said that the semiconductor structure according to this specific embodiment includes only one synthesis The semiconductor layer is disposed on the amorphous silicon oxide layer 36. The following non-limiting illustrative examples illustrate a number of specific embodiments in accordance with the present invention having many material combinations for use in structures 20, 40, and 34. These examples are merely illustrative and do not mean that the present invention is limited to these illustrative examples. Example 1 According to a specific embodiment of the present invention, the single crystal silicon substrate 22 is a silicon substrate in the (100) direction. The silicon substrate may be, for example, a silicon substrate having a diameter of about 200 to 3 00 nanometers which is commonly used in manufacturing complementary metal-oxide-semiconductor (CMOS) integrated circuits. According to this specific embodiment of the present invention, the containing buffer layer 24 is a single-layered silicon layer with a thickness of 3m: ζΒα1-ζΊΠ03, and the z-range is a fragmented oxide layer (SiOx ) Forming an interface between the broken substrate and the buffer layer. The 値 of Z is selected to obtain one or more lattice constants that closely correspond to the corresponding lattice constants of successively formed layers 26. The buffer layer may have a thickness of about 2 to about 100 nanometers (nm) and preferably a thickness of about 10 nanometers. Generally, the buffer layer needs to be thick enough to isolate the synthetic semiconductor layer from the substrate to obtain the required electrical and optical properties. Layers below 100 nanometers usually provide very little additional benefit and at the same time increase costs unnecessarily; however, thicker layers can be made if needed. The amorphous silicon interlayer of silicon oxide may have a thickness of about 0.5-5 nanometers and preferably a thickness of about 1.5-2.5 nanometers. According to the specific embodiment of the present invention, the synthetic semiconductor material layer 26 is made of gallium arsenide (GaAs) or aluminum gallium with a thickness of about 1 nanometer to about 100 micrometers. The paper size is applicable to the Chinese National Standard (CNS) A4 specification. (210 X 297 mm) 515097 A7 B7 V. Description of the invention (10) A layer of arsenide (AlGaAs) and preferably a thickness of about 0.5 microns to 10 microns. In order to facilitate the epitaxial growth of gallium oxide or aluminum gallium arsenide on single crystal silicon oxide, a template layer is formed by covering the silicon oxide layer. The sample layer is preferably a single layer of Qin-Kun, iron-oxygen-broken, Wei-married-oxygen or 1-10 of total- | g-oxygen. By way of a better example, titanium-arsenic or gill-gallium-oxygen 1-2 monolayers have been shown to successfully grow gallium halide layers. Example 2 According to a specific embodiment of the present invention, the single crystal silicon substrate 22 is a crushed substrate as described above. The accommodating buffer layer system is a single crystal oxide of strontium or barium sulphate or osmium salt in cubic or cubic phase, and an amorphous silicon intermediate layer having silicon oxide is formed on the silicon substrate and contains Interface between buffer layers. The buffer zone layer has a thickness of about 2-100 nanometers, and preferably has a thickness of at least 5 nanometers to ensure suitable crystalline silicon and surface quality and is formed of single crystal silicon SrZr03, BaZr03, SrHf03, BaSn03 or BaHF03 . For example, a single crystal silicon oxide layer of BaZr03 can grow at a temperature of about 700 ° C. The lattice structure of the resulting crystalline silicon oxide exhibits a 45-degree rotation relative to the substrate silicon lattice structure. The containment buffer layer formed from these zirconate or osmium salt materials is suitable for the growth of synthetic semiconductor materials in indium phosphonium (InP) systems. The synthetic semiconductor material may be, for example, indium discrimination (InP), indium dopant (InGaAs), aluminum indium arsenide (AllnAs), or aluminum gallium indium arsenide phosphide (AlGalnAsP), which has a thickness of 1.0 nanometer to 10%. Thickness in microns. Suitable samples for this structure are hammer-arsenic (Zr-As), hammer-phosphorus (Zr-P), thorium-arsenic (Hf-As), donor-thorium (Hf-P), gill-oxygen-arsenic (Sr -0-As), gill-oxygen-squat (Sr-0-P), barium--13- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Binding

515097 A7

__ B7 T invention description (11): ~ " Milk = Shen (Ba-0-As), Indium-Total_Oxygen (In_Sr-〇) or Barium_Oxygen_Scale (np) and preferably these materials among them One of the Bu 2 single layer. By the method used as an example of the barium hammer acid salt containing buffer layer, the surface was terminated with a single layer of zirconium, and then a 1-2 single layer of arsenic was deposited to form a zirconium-arsenic template. A single crystal silicon layer of a synthetic semiconductor material from an indium phosphide system is then grown on the template layer. The resulting lattice structure of the synthetic semiconductor material exhibits a 45-degree rotation relative to the lattice structure of the containing buffer layer and is less than 2.5% and preferably less than about 100% of the lattice of (100) InP. 〇. Example 3 According to a specific embodiment of the present invention, a structure is provided, which is suitable for the growth of epitaxial films of II-VI group materials to cover a silicon substrate. The substrate is preferably a shixi wafer as described above. A suitable material for containing the buffer layer is 3] ^: ^ 1 ^ 丁 丨 〇3, which in turn ranges from 0 to 1, which has a thickness of 2-100 nanometers and preferably about 5-15 nanometers. thickness. The Π_νι synthetic semiconductor material may be, for example, zinc selenide (ZnSe) or zinc sulfur selenide (ZnSSe). A suitable model for this material system includes a 1-1 single layer of zinc-oxygen (Zn-O), followed by a 1-2 single layer of zinc, followed by selenization of zinc on the surface. Alternatively, the template may be, for example, a gill-sulfur monolayer of ^ 0, followed by ZnSeS. Example 4 A specific embodiment of the present invention is an example of the structure 40 illustrated in FIG. 2. The single crystal silicon oxide layer 24 and the single crystal silicon synthetic semiconductor material layer 26 may be similar to those described in Example 1. In addition, the additional buffer layer 3 2 serves as a crystal lattice and single crystal that may be eliminated by the buffer layer containing the buffer layer. Silicon Semiconductor • 14- This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X 297 mm) 515097 A7 B7 V. Description of the invention (12) Any pressure caused by the lattice of the material does not match. The buffer layer 3 2 can Is it wrong or GaAs, AlGaAs, InGaP, AlGaP, InGaAs, AllnP, InGaAs (InGaAsP) or indium gallium phosphide (InGaP) pressure-compensated superlattice layer. According to one aspect of this embodiment, the buffer layer 32 includes a GaAs XP x ^ x superlattice, where X 値The range is from 0 to 1. According to another perspective, the buffer layer 32 includes IiiyGa ^ y P superlattice, where y 値 ranges from 0 to 1. By changing the X or y 値, if this is possible, the lattice constant changes from the bottom to the top beyond the superlattice to produce the underlying oxide and overlay synthesis The correspondence between the lattice constants of semiconductor materials. Compositions of other materials, such as those listed above, can also be similarly changed to manipulate the lattice constants of layer 32 in the same way. Superlattices can have a range of 50-500 nm And preferably has a thickness of about 100-200 nm. The template for this structure may be the same as that described in Example 1. Alternatively, the buffer layer 32 may be a single crystal silicon germanium having a thickness of 1-50 nm. And preferably has a thickness of about 2-20 nanometers. In the case of using a germanium buffer layer, whether it is a sample of germanium-gill (Ge-Sr) or germanium-titanium (Ge-Ti) with a single layer The layer can be used as a nucleation site for the successive growth of the single crystal silicon synthetic semiconductor material layer. The formation of the oxide layer is covered with either a single layer of gills or a single layer of titanium for subsequent deposition of single crystal silicon germanium Nucleation site. A single layer of gill or titanium provides the first order of germanium A nucleation site that can be bonded. Example 5 This example also illustrates the material used in the structure 40 illustrated in Figure 2. Base material 22, containing buffer layer 24, monocrystalline silicon synthetic semiconductor material layer 26, and -15.-This paper The dimensions apply to the Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 515097 A7 B7 V. Description of the invention (13) The template layer 30 can be the same as described above in Figure 2. In addition, the buffer layer 32 is inserted Between the containing buffer layer and the layer covering the single crystal silicon synthetic semiconductor material. The buffer layer, and further the single crystal broken semiconductor material, may be, for example, a grade layer of InGaAs or InAlAs. According to one aspect of this embodiment, the buffer layer 32 includes InGaAs, where the indium composition varies from 0 to about 47%. The buffer layer preferably has a thickness of about 10-30 nm. The composition of the variable buffer layer ranges from GaAs to InGaAs as a lattice conformation between the cover layers that provide the underlying single crystal silicon oxide material and the single crystal silicon composite semiconductor material. Such a buffer layer is particularly advantageous if there is a lattice mismatch between the containing buffer layer 24 and the single crystal silicon composite semiconductor material layer 26. Example 6 This example provides illustrative materials useful in Structure 34, as illustrated in Figure 3. The suitable material 22, the template layer 30, and the single crystal silicon composite semiconductor material layer 26 may be the same materials as those described in Example 1 above. The amorphous silicon layer 36 is formed by a mixture of an amorphous silicon intermediate layer material (for example, the material of layer 28 as described above) and a buffer layer material (for example, the material of layer 24 as described above). Amorphous silicon oxide layer. For example, the amorphous silicon layer 36 may include a mixture of SiOx and SrzBabzTiOd, where z ranges from 0 to 1), which is combined or mixed during the tempering process to form an amorphous shredded oxide layer 36. The thickness of the amorphous shredded layer 36 may vary for different applications and may depend on factors such as the required insulating properties of the layer 36, the type of semiconductor material including the layer 26, and so on. According to an exemplified viewpoint of this specific embodiment, the thickness of the layer 36 is 16 and the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm). Binding 5. Description of the invention (14) about 2 nm to about 100 Nanometers, preferably about 2-10 nanometers and most preferably about 5-6 nanometers. The layer 38 includes a monocrystalline silicon oxide material which can be epitaxially grown on the monocrystalline silicon oxide material, like a monocrystalline silicon synthetic semiconductor material used to form a material for containing the buffer layer 24. According to a specific embodiment of the present invention, the layer 38 includes the same materials as those including the layer 26. For example, if layer 26 includes GaAs, layer 38 also includes GaAs. However, according to other embodiments of the present invention, the layer 38 may include materials other than those used to form the layer 26. According to an exemplary embodiment of the present invention, the layer 38 is about 1 single layer and about 100 nanometers thick. Referring again to Figures 1-3 ', the substrate 22 is a single crystal crushed substrate such as a single crystal crushed substrate. The crystalline silicon structure of a single crystal silicon substrate is characterized by a lattice constant and a lattice direction. In a similar manner, the accommodating buffer layer 24 is also a single crystal silicon material and the lattice of the single crystal fragment material is characterized by a lattice constant and a crystal orientation. The lattice constants that contain the buffer zone layer and the single crystal silicon substrate must closely match, or, must basically achieve the lattice constants in rotation relative to one of the crystal directions of the other crystal direction. In this context, the terms "substantially equal" and "substantially coincide" mean that there is sufficient similarity between the lattice constants to allow the crystalline fragmentation layer of south quality to grow on the underlying layer. Figure 4 illustrates The relationship between the achievable thickness of the growing crystal layer of high-crystalline silicon quality is a function of the discrepancy between the lattice constants of the parasitic crystal and the growing crystal. Curve 42 illustrates the boundary of high-crystalline silicon quality materials. The area to the right of curve 42 represents the Layers of polycrystalline silicon. If there is no lattice mismatch, theoretically it is possible to grow infinitely thick, southern-quality shame crystal layers on parasitic crystals. When the lattice constant discrepancy increases, the thickness of the high-quality crystalline silicon that can be achieved rapidly decreases. As a reference point, for example, if the lattice between the parasitic crystal and the growth layer is often -17- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 515097 A7 B7 V. Description of the invention (15) When the number does not exceed about 2%, a single crystal silicon epitaxial layer exceeding about 20 nanometers cannot be achieved. # According to a specific embodiment of the present invention, the substrate 22 is a single crystal in the (100) or (111) direction. Crystal Silicon The circular buffer zone 24 is a layer of gill barium titanate. The lattice constants between the two materials are basically consistent with each other by rotating the crystal orientation of the acetic acid salt material relative to that of the Shixi substrate wafer. The crystal orientation is reached at 45 °. Addition, in this example is the Shi Xi oxide layer, in the structure of the amorphous broken interface layer 28, if it has a sufficient thickness, as a possible reduction from parasitic silicon wafers and growth of titanium The difference in the lattice constant of the acid salt layer causes a pressure in the titanate single crystal silicon layer. As a result, according to a specific embodiment of the present invention, a high-quality, thick, single-crystal Mengqin salt layer is acceptable. Reached.

Still referring to Figures 1-3, layer 26 is a layer of epitaxially grown single crystal silicon material, and the characteristics of the crystal silicon material are also the crystal lattice constant and crystal orientation. According to a specific embodiment of the present invention, the lattice constant of the layer 26 is different from the lattice constant of the substrate 22. In order to achieve the high-crystalline silicon quality in the epitaxially grown single-crystal silicon layer, the containing buffer layer must have high-crystalline silicon quality. In addition, in order to achieve high crystalline silicon quality in the layer 26, parasitic crystals, in this case, a single crystal silicon containing buffer layer and a growth crystal are basically required. Appropriate selection of the material and rotation of the crystal with respect to the direction of the parasitic crystal can basically achieve the lattice constant. If the growth crystal is a gallium compound, a chain compound, a zinc compound or a zinc-sulfur magnetide, and the buffer layer is a single-crystal silicon SrxBa1-xTi03, the crystal lattice constants of the two materials can be basically met. The crystal orientation of the growth layer is rotated 45 relative to the direction of the parasitic single crystal silicon oxide. . Similarly, -18- This paper size applies to the Chinese National Standard (CNS) A4 (210 X 297 mm) 515097 A7 B7 V. Description of the invention (16 If the parasitic material is strontium or barium hammer salt or strontium or When it is a barium salt or a barium tin oxide and the synthetic semiconductor layer is indium phosphide, gallium indium arsenide, or aluminum indium halide, the crystal lattice constant basically matches the direction in which the crystal layer can be grown by rotation. Relative to parasitic oxide crystal 45. In some cases, the crystal dream semiconductor buffer layer between the parasitic oxide and the growing synthetic semiconductor layer can be used to reduce the possibility of crystal growth in the growing monocrystalline silicon synthetic semiconductor layer. The pressure caused by the small difference in constants can be used to achieve a better quality of crystalline silicon in growing a single crystal silicon synthetic semiconductor layer. According to a specific embodiment of the present invention, the following example illustrates the process for manufacturing a semiconductor structure, such as The structure depicted in Figures 1-3. The process begins by providing semiconductor substrates including pre-crushed or pre-crushed semiconductor substrates. According to a preferred embodiment of the present invention, semiconductor substrates It is a broken wafer with a (100) direction. The substrate is preferably in the direction of the axis, at most, offset from the axis by about 0.5 °. At least one part of the semiconductor substrate has a bare surface, although other parts of the substrate, As described below, other structures may be included. The term "naked" in this context means that the surface in a portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign materials. As is well known Bare silicon is highly reactive and easily forms its own oxides. The word "naked" is meant to include such own oxides. Although such growing oxides are not essential to the process according to the invention However, thin oxides may also be intentionally grown on semiconductor substrates. In order to epitaxially grow a single crystal silicon oxide layer to cover the single crystal silicon substrate, the own oxide layer must first be removed to expose the underlying substrate Material silicon structure. Although other epitaxial processes can also be used according to the present invention, it is best to perform the following processes by molecular beam epitaxy (MBE). Since -19- This paper standard applies Chinese National Standard (CNS) A4 Grid (210 X 297 mm) 515097 A7 B7 V. Description of the invention (17) There can be oxides by first thermally depositing a thin layer of gills, barium, a mixture of gills and barium or other alkaline earth elements or a mixture of alkaline earth elements Removed in MBE device. In the case of gill use, the substrate is then heated to a temperature of about 750 ° C to cause the gill to react with its own silicon oxide layer. The gill acts to reduce silicon oxide to leave no silicon oxide The surface of the object. The resulting surface presents an ordered 2x1 structure including gills, oxygen, and silicon. The ordered 2x1 structure forms a template for the orderly growth of a monocrystalline silicon oxide overlay. The template Provide the required chemical and physical properties to grow crystalline silicon with a nucleation coating. According to another embodiment of the present invention, the own silicon oxide can be converted and the substrate surface can be MBE, at low temperature, by Deposition of alkaline earth element oxides, such as gill oxide, gill barium oxide, or barium oxide, onto the surface of the substrate and prepare the single crystal silicon oxide layer by successively heating the structure to a temperature of about 750 ° C Growth. At this temperature, a solid state reaction occurs between the oxide and its own fragmented oxide, resulting in the reduction of its own fragmented oxide and leaving an ordered 2x1 structure with gills, oxygen, and silicon on the substrate surface . Again, this formation template grows sequentially in the ordered single crystal dream oxide layer. According to a specific embodiment of the present invention, after the silicon oxide is removed from the surface of the substrate, the substrate is cooled to a temperature in the range of about 200-800 ° C and the gill titanate is grown by molecular beam epitaxy. Layer on the template layer. MBE is activated by opening a movable shutter in the MBE device to expose gills, titanium and oxygen sources. The sum 'ratio is close to 1: 1. The partial pressure of oxygen is initially set to a minimum level to grow stoichiometric gills, titanates at about 0.3-0.5 nanometers per minute. After the initial growth of gill titanate, the partial pressure of oxygen increased by more than -20- This paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm) 515097 A7 B7 V. Description of the invention (18) Beginning 値. The excessive pressure of oxygen leads to the growth of the amorphous silicon silicon oxide layer at the interface between the underlying substrate and the gill titanate layer. The growth of the silicon oxide layer results from the diffusion of oxygen through the growing ferric acid salt layer to where the oxygen reacts with the surface of the broken substrate. Gill titanate grows into an ordered single crystal with a crystal orientation rotated 45 ° with respect to the ordered 2x1 crystalline silicon structure of the underlying substrate. Otherwise, because the lattice constant between the silicon substrate and the growing crystal is small, there may be pressure in the ferrite layer, which is released in the intermediate layer of amorphous and broken silicon oxide. After the gill titanate layer has grown to the required thickness, the single crystal silicon gill titanate is covered by its successively growing pattern layer that conducts electricity to the epitaxial layer of the required synthetic semiconductor material. In order to increase the growth rate of the complex layer, the MBE growth of the ferrous monocrystalline silicon layer can be terminated by a titanium 1-2 single layer, a chin-oxygen 1-2 early layer, or a Ming-Rubber 1 -2 single-layer growth and coverage. After the capping layer is formed, arsenic is deposited to form a Khin-arsenic energy level, an oxygen-arsenic energy level, or a gill-oxygen-arsenic level. Any of these forms a suitable template for the deposition and formation of germanium arsenic single crystal silicon layers. After the template was formed, germanium was successively introduced to react with thorium and germanium arsenide. Alternatively, germanium can be deposited on the cover layer to form a gill-oxygen-germanium energy level and arsenic is subsequently introduced with germanium to form GaAs. Fig. 5 is a high-resolution transmission electron micrograph of a semiconductor material manufactured according to the present invention. A single crystal SrTi03 containing buffer layer 24 is epitaxially grown on a silicon substrate 22. During this growth process, an amorphous fractured interface layer 28 is formed which releases the pressure caused by the lattice mismatch. GaAs is used to synthesize the semiconductor layer 26 and then epitaxially grown using the template layer 30. Figure 6 illustrates the use of a holding buffer in a structure that includes a GaAs synthetic semiconductor layer 26.-This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) A7 B7 V. Description of the invention (19) Punch layer 24 The X-ray diffraction spectrum of the silicon substrate 22 is increased. A peak at this spectrum indicates that both the containing buffer layer 24 and the GaAs synthetic semiconductor layer 26 are single crystals and the direction is (100). The structure illustrated in Figure 2 can be formed by discussing the above process plus additional buffer layer deposition steps. Prior to the deposition of the single crystal silicon synthetic semiconductor layer, the buffer layer was formed to cover the sample layer. If the buffer layer is a synthetic semiconductor superlattice, such a lattice can be deposited by MBE, such as on a template as described above. In other words, if the buffer layer is a layer of germanium, modify the above process to cover the gill titanate single crystal silicon layer with the last layer of gill or titanium, and then deposit germanium to react with gill or titanium . The germanium buffer layer can then be deposited directly on the template. As shown in Fig. 3, the structure 34 can be formed by growing the holding buffer layer, which forms an amorphous silicon oxide layer on the substrate 22 and the growing semiconductor layer 38 on the holding buffer layer as described above. The exposure buffer layer and the amorphous silicon oxide layer are subsequently exposed to the tempering process to sufficiently change the crystalline silicon structure of the accommodation buffer layer from single-crystal silicon to amorphous silicon, thereby forming an amorphous silicon layer such that the amorphous silicon oxide The combination of the layers and now the amorphous silicon containing buffer forms a single amorphous silicon emulsion layer 36. Layer 26 subsequently grows on layer 38 in succession. Alternatively, the tempering process may be performed after the layer 26 has grown. According to one aspect of this specific embodiment, the layer 36 is exposed to the substrate 22, the buffer layer, the amorphous silicon oxide layer, and the semiconductor layer 38 to a rapid thermal tempering process of about 700 ° C to about 1000 ° C It is formed at the highest temperature and a processing time of about 10 seconds to about 10 minutes. However, according to the present invention, other suitable tempering processes may be used to convert the containing buffer layer to the amorphous silicon layer. For example, -22- This paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm) 515097 A7 B7 V. Description of the invention (2Q) Laser tempering or "traditional" thermal tempering process (where appropriate Environment) can be used to form the layer 36. When conventional thermal tempering is used to form layer 36, pressurization of one or more of the components of layer 30 may be required during the tempering process to prevent degradation of layer 38. For example, when the layer 38 includes GaAs, the tempering environment preferably includes a pressure of arsenic to mitigate the degradation of the layer 38. As reminded above, layer 38 of structure 34 may include any material suitable for layer 32 or 26. Therefore, any method of deposition or growth described with layers 32 or 26 may be utilized to deposit layers 38. FIG. 7 is a TEM diagram illustrating high-resolution transmission electrons of the semiconductor material manufactured in FIG. 3 according to a specific embodiment of the present invention. According to this embodiment, a single crystal SfTi03 containing buffer layer 24 is epitaxially grown on a silicon substrate 22. During this growth process, the 'amorphous dream interface layer is formed as described above. Next, a GaAs layer 38 is formed on the receiving buffer layer and the receiving buffer layer is exposed to a tempering process to form an amorphous silicon oxide layer 36. Fig. 8 illustrates an X-ray diffraction spectrum of a structure including a GaAs synthetic semiconductor layer 38 and an amorphous silicon oxide layer 36 formed on a silicon substrate 22. The peak in the spectrum indicates that the GaAs synthetic semiconductor layer 38 is a single crystal with a direction of (100) and the absence of the peak indicating layer 36 near 40 to 50 degrees is amorphous silicon. The process described above illustrates a process for forming a semiconductor structure including a silicon substrate, an overlying oxide layer, and a single crystal broken germanium compound by a process of epitaxial beam indexing. This process can also be performed by chemical vapor deposition (C VD), metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy (MEE), atomic layer epitaxy (ALE), physical vapor deposition (PVD), chemical The solution deposition (CSD), pulsed laser deposition (PLD) and other manufacturing processes are implemented. -23- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) 515097 A7 B7 V. Description of the invention ( 21) OK. Further, by a similar process, other single crystal silicon accommodates the buffer layer, such as soil test element's salt, acid salt, osmium salt, acid salt, old salt, nail salt and weirate, number # 5 Mineral oxides, such as titanite, lanthanum aluminate, lanthanum oxide, and ytterbium oxide, which are based on soil test element tin, can also grow. Further, by a similar process as MBE, other III-V and II-VI single crystal chip composite semiconductor layers can be deposited to cover the single crystal chip oxide containing buffer layer. Each change in the synthetic semiconductor material and single crystal silicon oxide containing buffer layer uses a suitable template for the growth of the starting synthetic semiconductor layer. For example, if the containment buffer layer is an alkaline earth element zirconate, the oxide may be covered by a thin layer of a knot. Hammer deposition can be followed by crushing or phosphorous deposition with zirconium as a precursor to deposit indium germanium arsenide, indium aluminum arsenide, or indium phosphide, respectively. Similarly, if the single crystal silicon oxide containing buffer layer is an alkaline earth element osmium salt, the oxide layer may be covered by a thin layer of rhenium. Thallium deposition can be followed by deposition of arsenic or phosphorus with a reaction with thorium as a precursor to grow indium germanium arsenide, indium aluminum arsenide, or indium phosphide, respectively. In a similar manner, gill titanate can be covered with gills or a layer of gills and oxygen while pinate can be covered by barium or a layer of oxygen and oxygen. Each of these deposits can then be deposited with arsenic or phosphorus to react with the covering material to form a template for the deposition of a layer of synthetic semiconductor material including indium germanium arsenide, indium aluminum arsenide, or indium phosphide. Fig. 9 schematically illustrates, in cross section, a device structure 900 according to still another embodiment of the present invention. The device structure 900 includes a single crystal chipped semiconductor substrate 901 ', which is taken as a chipped chip wafer. Pre-crushed semiconductor substrate 901 includes two -24-This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm)

Installation t 515097 A7 B7 V. Description of the invention (22) Areas 902 and 903. An electronic semiconductor element substantially indicated by a dotted line 911 is formed in the region 902. The electronic component 911 may be a resistor, a capacitor, an active semiconductor component, such as a diode or a transistor, or an integrated circuit such as a MOS integrated circuit. For example, the electronic component 911 may be a MOS circuit configured to perform digital signal processing or other functions that are completely suitable for a silicon integrated circuit. The electronic semiconductor elements in region 902 can be formed by conventional semiconductor processing as is well known and widely used in the semiconductor industry. A layer of insulating material 904, such as a layer of silicon dioxide, may cover the electronic semiconductor element 911. The insulating material 904 and any other layers that have been formed or deposited during semiconductor element 911 processing during region 902 are removed from the surface of region 903 to provide a bare substrate surface in that region, such as a bare silicon surface. As is well known, the bare silicon surface is highly reactive and its own silicon oxide layer can be quickly formed on the bare surface. Alternatively, barium or a layer of barium and oxygen may be deposited on the native oxide layer, on the surface of the region 903 and thereafter reacting with the oxidized surface to form a template layer 907. According to a specific embodiment of the present invention, a single crystal silicon oxide layer 906 is formed by a molecular beam epitaxy (MBE) process to cover the template layer. In one aspect of this illustrated embodiment, a reactant comprising barium, titanium, and oxygen is deposited on a template layer to form a single crystal silicon oxide layer. Initially during deposition, the partial pressure of oxygen remained close to the minimum required to fully react with barium and titanium to form a single crystal barium titanate layer 906. Partial pressure of oxygen is then increased to provide oxygen pressurization and allow oxygen to diffuse through the growing single crystal silicon oxide layer. Diffusion via barium titanate oxygen reacts with silicon on the surface of region 903 to form an amorphous silicon layer 905 on a silicon substrate and a single crystal silicon oxide 25 This paper is sized to Chinese National Standard (CNS) A4 (210X 297) (Mm) 515097 A7 B7___ V. Interface between invention description (23). Alternatively, an amorphous shattered oxide layer containing materials from layers 905 and 906 may be formed by forming a single crystal hard oxide layer 906 and sequentially heat-treating the resulting structure to convert the single crystal silicon oxide to a non-crystalline silicon oxide. Crystalline silicon oxide is formed as discussed below. According to a specific embodiment of the present invention, after the step of depositing the single crystal silicon oxide layer 906, an intermediate oxide conversion layer 908 is deposited. The conversion layer 908 typically includes ordered, crystalline and broken metal oxides, such as erroneous oxides (MgO), button oxides (TaO), or manganese oxides (MnO), and is preferably grown by the MBE process. After the step of depositing the conversion layer 908, a second template layer 909, which may be, for example, a 1-10 single layer of germanium antimonide (GaSb), InMgO, or MgAsO, is deposited. The template layer 909 serves as a "seed" layer to help cover the formation of the single crystal silicon synthetic semiconductor layer 910. In a preferred embodiment, the single crystal silicon synthetic semiconductor layer 910 includes a semiconductor material, which is particularly suitable for use in the formation of a highly reliable and sensitive Hall sensor device, such as InAs or GaAsSb. According to one aspect of the present invention, after the layer 908 is formed, the single crystal titanate layer and the silicon oxide layer interposed between the substrate 901 and the titanate layer are exposed to a tempering process such that the salt and The oxide layer forms an amorphous broken oxide layer. The epitaxial growth is then followed by an additional synthetic semiconductor layer 910 on layers 908 and 909. Alternatively, the aforementioned tempering process may be performed after the template layer 909 or the synthetic semiconductor layer 910 is formed. According to yet another embodiment of the present invention, a semiconductor element substantially indicated by a broken line 912 is formed in the composite semiconductor layer 910. The semiconductor element 912 can be loaded with indium arsenide or other III-V synthetic semiconductor materials. This paper is sized to the Chinese National Standard (CNS) A4 (210 X 297 mm) 515097 A7 B7 V. Description of the invention ( 24) It is formed by processing steps traditionally used in manufacturing. The semiconductor element 912 may be any active or passive element and is preferably a Hall sensor, a tunneling diode, a light emitting diode, a semiconductor laser, a photodetector, a heterojunction diode (HBT) ), High-frequency MESFETs, or other components that take advantage of the physical properties of synthetic semiconductor materials. The metal conductor indicated generally by the line 913 can be formed to the electrical coupling device 912 and the device 911, thereby performing an integrated device including at least one element formed in a silicon substrate and a device formed in a single-crystal silicon synthetic semiconductor material layer . Although the illustrated structure 900 has been described as a structure formed on a silicon substrate 901 and has a barium titanate layer 906 and an InAs or GaAsSb layer 910, other single crystal silicon substrates and single crystal silicon oxide layers may be used. And other monocrystalline silicon synthetic semiconductor layers are fabricated as described elsewhere herein. FIG. 10 illustrates a semiconductor structure 1000 according to yet another embodiment of the present invention. In this embodiment, the structure 1000 is a Hall sensor formed from a single crystal silicon epitaxial layer of a synthetic semiconductor material on a single crystal silicon substrate. The structure 1000 includes a single crystal silicon semiconductor substrate 1001, such as a single crystal silicon wafer. According to the above process, the amorphous silicon oxide layer 1002 is preferably formed to cover the substrate 1001. The accommodating buffer layer 1003 is formed to cover the substrate 1001 and the amorphous crushed oxide layer 1002. As described above, the amorphous crushed oxide layer 1002 can be grown by the oxidation of the substrate 1001 during the growth of the layer 1003, the interface between the substrate 1001 and the growth-accommodating buffer layer 1003. The buffer layer 1003 is preferably a single crystal silicon oxide material selected for its compatibility with the underlying substrate and the crystalline silicon of the synthetic semiconductor material covering it. In this specific embodiment, the substrate 1001 is a monocrystalline silicon and covered synthetic semiconductor material. -27- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm)

Outfit

515097 A7 B7 V. Description of the invention (25) The material layer is single crystal In As. The layer 1003 may include, for example, soil test element titanate, such as barium titanate or gill titanate, alkaline earth element. Acid salts such as lock acid salts or salt acid salts or soil test element acid salts such as barium sulphate or gill hammer salt. The intermediate oxide conversion layer 1004 is preferably formed to cover the layer 1003 to reduce the pressure generated from the mismatch between the crystal lattice of the buffer layer 1003 and the crystal lattice of the single crystal silicon semiconductor material layer. The conversion layer 1004 may include any suitable oxide material, such as manganese oxide (MnO), magnesium oxide (MgO), or thallium oxide (TaO). In this illustrated embodiment, the conversion layer 1000 is a layer of MgO and has a thickness of about 10 to about 100 nanometers, and preferably a thickness of about 50 nanometers. The thickness usually depends on the application for which the layer is intended to be used. In order to facilitate the epitaxial growth of indium sulfide on single crystal silicon oxide, the sample layer 1005 can be formed by covering the oxide layer. The sample layer is preferably a single layer of gallium-antimony, gallium-magnesium-antimony, indium-magnesium-oxygen, or magnesium-arsenic-oxygen. The single crystal silicon synthetic semiconductor material layer 1006 is preferably formed by MBE to cover the template layer 1005. The synthetic semiconductor material layer 1006 preferably includes a material that is highly sensitive and has a large electron mobility such as InAs or GaAsSb over a wide temperature range. In a preferred embodiment of the present invention, layer 1006 includes a layer of InAs having a thickness from about 10 to 1000 nanometers. According to an illustrative embodiment of the invention illustrated in FIG. 10, the semiconductor device structure 1000 includes an InAs Hall sensor device. The structure and method of manufacturing an InAs Hall sensor device are known to those skilled in the art. As illustrated in FIG. 10, according to well-known manufacturing techniques, after forming the InAs layer 1006, the spaced-apart conductive electrodes 1007 and 1008 are formed to cover -28- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 Mm)

Binding f 515097 A7 B7 V. Description of the invention (26) A cover layer 1006 ° passivation layer 1009 is formed to cover the electrodes 1007 and 1008 and to isolate the area between the electrodes. The floating semiconductor device 1010 is then formed on the passivation layer 1009 and may include any suitable device known in the art, such as an 'accelerometer. Electrical connections are then made to the device based on traditional techniques available to those skilled in the art. If the device is intended to be formed from a single crystal material, the layer 1009 is preferably a single crystal silicon. Referring now to FIG. 11, a single integrated circuit is provided in accordance with one embodiment of the present invention. The single integrated circuit 1 100 typically includes a MOS circuit 1140 electrically connected to a Hall sensor. In the figure, it is for illustrative purposes only, and there is no limitation. The MOS circuit 1140 is electrically connected to the Hall sensor 113 0, for example, as shown in FIG. In this embodiment, the semiconductor substrate 110 is a single crystal hard rock substrate, such as a silicon wafer, and has two regions 1102 and 1103. According to the specific embodiment of the present invention, the template layer 1108, the amorphous silicon oxide layer 1109, the single crystal silicon oxide layer 1110, the intermediate oxide transition layer 1111, the template layer 1112, and the single crystal silicon synthetic semiconductor material layer 1113 The and electrodes 1114 and 1115 are formed from the same materials and the same process steps described by the fabrication of these Hall sensor devices with reference to FIG. 10. For the sake of brevity, the formation of these elements will not be discussed additionally with FIG. According to a specific embodiment of the present invention, the MOS circuit 1140 is first formed in a semi-conductor substrate 1101 using traditional process steps and techniques familiar to those skilled in the art. The MOS circuit 1140 generally includes a gate electrode 1107, a gate dielectric layer 1106, and n + doped regions 1104 and 1105. The gate dielectric layer 1106 is formed in the region 102 of the substrate no !, and the gate electrode η "shape -29-This paper is suitable for SS Home Standard (CNS) A4 (21GX 297 public love) 515097 A7 B7 V. Description of the invention (27) is formed on the gate dielectric layer 1106. Selective η-type doping is performed to form η + doped regions 1104 and 1105 in the substrate 110, along the gate Adjacent sides of electrode 1107 are the source, drain, or source / drain regions of the MOS transistor. The η + doped regions 1104 and 1105 have a doping concentration of at least about 1E18 atoms per cubic centimeter. After the m0s portion 1140 of the integrated circuit is formed, all the formed layers are removed from the surface of the substrate 1101 in the area 丨 〇3 during the manufacturing process, in which the Hall sensor 113 will be formed. Therefore,

Mounting the bare silicon substrate provides a sequential process for Hall sensors 113 °, such as the method proposed above. f After both the MOS circuit 1140 and the Hall sensor 113 are formed on the substrate 110, the process is continued to form a substantially completed integrated circuit 110. The ohmic contacts 111 8 and 1119 can be formed on the gate electrode 1107 and the electrode 1114 using standard process techniques well known in the art, respectively. An insulating layer 1121 is formed on the substrate 1101, the MOS circuit 1140, and the Hall sensor 113. The insulation layer 1121 is then removed to define the contact where the devices are interconnected in an open circuit. An interconnecting trench is formed within the insulating layer 2 to provide a lateral connection between the contacts. As illustrated in FIG. 11, the internal connection 112 is connected to the gate electrode of the Mos transistor to the electrode 1114 of the Hall sensor 1130. A passivation layer 1116 is formed on the interconnects 1120 and the insulating layer 1121. After the passivation layer 1116 is formed, the device 1117 may be formed on the Hall sensor 丨 丨 3 〇 in a region defined by the electrodes 丨 i 4 and 1115. The device 1117 may be any floating device suitable for use with a Hall sensor, such as an accelerometer. According to the traditional technology of the person who can be familiar with this technology, other electrical connections to the device and / or other electrical < electronic components in integrated circuits can be made -30- This paper size applies to China National Standard (CNS) A4 specifications (21〇X 297) 515097 A7 B7 5. In the description of the invention (28), but it is not illustrated in the figure. Clearly, these specific embodiments of an integrated circuit having a synthetic semiconductor portion and a semiconductor portion of an IV group are intended to illustrate specific embodiments of the invention and not to limit the invention. The diversity of other combinations of semiconductor devices and other specific embodiments of the present invention fall within this disclosure. For example, the synthetic semiconductor part may include light emitting diodes, photodetectors, diodes, etc. and the group IV semiconductor part may include digital logic, memory arrays, and most structures that can be formed in traditional MOS integrated circuits. By using specific embodiments of the present invention, it is relatively simple to integrate devices that work better in synthetic semiconductor materials and other elements that work better and are easily and / or inexpensively formed in group IV semiconductor materials. This allows for reduced device size, lower manufacturing costs and increased yield and reliability.蠓 As considered in the above description, single crystal silicon IV group wafers can also be used to form only synthetic semiconductor electronic components on the wafer. In this way, the wafer is basically a "processing" wafer used during the manufacture of synthetic semiconductor electronic components while the monocrystalline silicon synthetic semiconductor layer covers the wafer. Therefore, electronic components can be formed on II-V or II-IV semiconductor materials on wafers with a diameter of at least 200 mm and possibly at least 300 mm. With the use of this type of substrate, a relatively cheap "processing", the wafer overcomes the fragile nature of synthetic semiconductor wafers by placing it on a relatively more durable and easier to manufacture base material. Therefore, it can form Integrated circuits allow all electronic components, and in particular all active electronic devices, to be formed in synthetic semiconductor materials, even though the substrate itself may include semiconductor materials of group IV. The manufacturing cost for synthetic semiconductor devices should be reduced, as compared to -31 -This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 515097 A7 B7 V. Description of the invention (29) For the relatively small and more fragile traditional synthetic semiconductor wafers, larger substrates It can be processed more economically and faster. In the previous specifications, the present invention has been described with reference to specific embodiments. However, those skilled in the art will understand that many modifications and changes can be made without departing from the following. The scope of the invention as set forth in the claims. Therefore, the specifications and drawings are to be regarded as illustrative rather than restrictive, and Proper modification is considered to be included within the scope of the present invention. According to the present invention, for example, the use of antimony-based materials such as indium antimonide (InSb), aluminum antimonide (A1Sb), indium aluminum antimonide ( ] [nAisb), gallium antimonide (GaSb), indium gallium antimonide (InGaSb), and aluminum gallium antimonide (A) iGaSb) are possible in Hall's political system. Those familiar with this technology will understand The present invention can be applied to the non-Hall effect "device or other semiconductor device structure in any III-V or other synthetic semiconductors using accurate or other suitable oxides that can conform to the silicon lattice. Benefits' Other advantages and problems The solution has been described above with specific examples. However, any benefit, advantage, or solution to the problem = any element that can cause any benefit, advantage, or solution to occur or become clear is not to be understood as any Or all important, required features or elements of the patentable scope. As used herein, the term "comprising," "including," or any other variation is intended to cover non-limiting inclusion, To include a list of Yuan Xinzhi ^ σ. U, various methods, provisions or devices do not include only these elements but may include lists without expressions or other elements inherent to the process, methods, provisions or devices .

Claims (1)

AB c D 515097 6. Scope of patent application 1. A single integrated circuit including: • a MOS circuit formed at least partially in a single crystal substrate; a single crystal synthetic semiconductor layer covering the single crystal substrate; and a huo An ear sensor is formed at least partially on the single crystal synthetic semiconductor layer, and the Hall sensor is electrically connected to the MOS circuit. 2. The single integrated circuit according to item 1 of the application, wherein the MOS circuit includes a MOS transistor having a gate electrode and the Hall sensor is electrically connected to the gate electrode. 3. The single integrated circuit according to item 1 of the patent application scope, wherein the MOS circuit includes a digital circuit. 4. A single integrated circuit as described in claim 1 wherein the Hall sensor includes an InAs layer. 5. The single integrated circuit as described in claim 1 wherein the Hall sensor includes a GaAsSb layer. 6. A semiconductor device comprising: a single crystal semiconductor substrate; an oxide layer is formed to cover the substrate; a single crystal synthetic semiconductor layer is formed to cover the oxide layer; and a Hall sensor is at least The formed portion is in a single crystal synthetic semiconductor layer. 7. The semiconductor device as claimed in claim 6 further comprising an intermediate crystalline silicon oxide conversion layer interposed between the oxide layer and the single crystal synthetic semiconductor layer. 8. The semiconductor device according to item 6 of the application, further comprising a template layer interposed between the conversion layer and the single crystal synthetic semiconductor layer. -33- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 515097 A8 B8 C8 D8 6. Scope of Patent Application 9. If a semiconductor device is applied for patent_Scope item 6, the single crystal synthesis semiconductor layer includes materials selected from the group consisting of InAs, GaAsSb, and InSb. 10. The semiconductor device as claimed in claim 7 wherein the intermediate crystalline silicon oxide conversion layer includes a material selected from the group consisting of MgO, TaO, and MnO. 11. The semiconductor device according to item 8 of the application, wherein the template layer includes a material selected from the group consisting of GaSb, InMgO, and MgAsO. 12. The semiconductor device according to item 6 of the patent application, wherein the oxide layer includes one selected from the group consisting of a soil test element acid salt, a soil test element acid salt, and a soil test element donor acid salt. Oxide. 13. The semiconductor device as claimed in claim 6, wherein the oxide layer includes an oxide selected from the group consisting of TaTi03, BaZr03, BaHf03, SrHf03, and SrZr03. 14. The semiconductor device as claimed in claim 6, wherein the oxide layer includes an amorphous silicon oxide layer. 15. The semiconductor device according to item 14 of the application, wherein the oxide layer includes an amorphous stone oxide formed by epitaxial formation as a single crystal oxide layer and successively heat-treated to convert the single crystal oxide to amorphous Silicon oxide. 16. The semiconductor device according to item 6 of the patent application, wherein the substrate comprises 17. The semiconductor device according to item 16 of the patent application, further comprising amorphous silicon oxide formed under the oxide layer. -34-This paper size is applicable to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 515097 A8 B8 C8 D8 VI. Application for patent scope 18 · If you apply for the semiconductor device in the scope of specialty No. 6, the oxide layer It includes an amorphous silicon oxide formed by heat-treating a single crystal oxide layer. 19. A method of manufacturing a semiconductor device, comprising the steps of: providing an early crystal semiconductor substrate; epitaxially growing a single crystal oxide layer to cover the substrate; growing a single crystal synthetic semiconductor structure to cover the single crystal oxide, the The single crystal synthetic semiconductor structure includes an intermediate oxide conversion layer, a template layer, and a single crystal synthetic semiconductor layer; and forming a Hall sensor is at least partially in the single crystal synthetic semiconductor structure. 20. The method of claim 19 in the scope of patent application, further comprising the step of forming an amorphous silicon oxide layer so as to be positioned under the single crystal oxide layer during the epitaxial growth step. 21. The method of claim 20, further comprising the step of thermally annealing the single crystal oxide layer to convert the single crystal oxide to a further layer of amorphous silicon oxide. 22. The method of claim 19, wherein the step of growing a single crystal synthetic semiconductor structure includes selecting from a group consisting of MBE, MOCVD, CVD, MEE, ALE, PVD, PLD, and CSD Steps to process growth. 23. The method of claim 19, wherein the step of providing a semiconductor substrate includes the step of providing a single crystal substrate including silicon. 24. The method of claim 23, further comprising the steps of: forming a digital integrated circuit at least partially in the substrate; and forming an interconnect to electrically connect the digital integrated circuit and the Hall sensing -35- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 515097 A8 B8 C8 D8 6. Applicants for patent scope. 25. The method of claim 24, wherein the step of forming a digital integrated circuit includes the step of forming a MOS transistor having a gate electrode and the Hall sensor is electrically connected to the gate electrode. 26 · A method for manufacturing a semiconductor device, comprising the steps of: providing a single crystal semiconductor substrate; a worm crystal growing a single crystal oxide layer to cover the substrate; growing a single crystal synthetic semiconductor structure to cover the single crystal oxide, The single crystal synthetic semiconductor structure includes an intermediate oxide conversion layer, a template layer, and a single crystal synthetic semiconductor layer, wherein the single crystal synthetic semiconductor layer includes InAs; and a Hall sensor is formed at least partially in the single crystal synthetic semiconductor structure. 27. The method of claim 26, further comprising the step of forming an amorphous oxide oxide layer under the single crystal oxide layer during the epitaxial growth step. 28. The method of claim 27, further comprising the step of thermally annealing the single crystal oxide layer to convert the single crystal oxide to a further layer of amorphous silicon oxide. 29. The method of claim 26, wherein the step of growing a single crystal synthetic semiconductor structure includes selecting from a group consisting of MBE, MOCVD, CVD, MEE, ALE, PVD, PLD, and CSD Steps to process growth. 30. The method according to item 26 of the patent application scope, further comprising the steps of: forming a digital integrated circuit at least partially in the substrate; and -36- this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public) (Centi) 515097 AB c D 々 The scope of the patent application forms an interconnector to electrically connect the digital integrated circuit and the Hall sensor. 31. The method of claim 30, wherein the step of forming a digital integrated circuit includes the step of forming a MOS transistor having a gate electrode and the Hall sensor is electrically connected to the gate electrode. 32 · A method for manufacturing a semiconductor device, comprising the steps of: providing a single crystal silicon substrate; forming a CMOS circuit at least partially in the silicon substrate, the CMOS circuit including a MOS transistor having a gate electrode; and an epitaxial growth single A crystalline oxide layer to cover the substrate; during the epitaxial growth step, an amorphous silicon layer of silicon oxide is formed under the single crystal oxide layer; an intermediate oxide conversion layer is formed to cover the single crystal oxide Layers; growing a single crystal synthetic semiconductor structure to cover the conversion layer; heat treating the single crystal oxide layer to convert the single crystal oxide to an additional layer of amorphous silicon oxide; forming a Hall sensor at least partially from the single crystal A synthetic semiconductor structure; and an electrical connection formed between the Hall sensor and the gate electrode. 33. The method of claim 32, wherein the step of epitaxial growth of the single crystal oxide layer includes epitaxial growth from a group consisting of an alkaline earth element titanate, an alkaline earth element osmate, and an alkaline earth element hammer salt. Step of selecting the oxide layer in the group. 34. The method according to item 33 of the scope of patent application, in which epitaxial growth single crystal oxidation -37- This paper size is applicable to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 515097 AB c D 6. Scope of patent application The physical layer step includes the step of epitaxially growing the BaTi03 layer. 35. The method of claim 32, further comprising the step of forming a template layer interposed between the conversion layer and the single crystal synthetic semiconductor structure. 36. The method of claim 35, wherein the step of forming the template layer includes forming a template layer of a material selected from the group consisting of GaSb, InMgO, and MgAsO. 37. The method of claim 32, wherein the step of forming the intermediate oxide conversion layer includes forming a conversion layer of an oxide selected from the group consisting of MgO, MnO, and Ta0. -38- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)