WO2002014932A2 - Circuit d'attaque a recyclage d'energie pour charge capacitive - Google Patents

Circuit d'attaque a recyclage d'energie pour charge capacitive Download PDF

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Publication number
WO2002014932A2
WO2002014932A2 PCT/US2001/025648 US0125648W WO0214932A2 WO 2002014932 A2 WO2002014932 A2 WO 2002014932A2 US 0125648 W US0125648 W US 0125648W WO 0214932 A2 WO0214932 A2 WO 0214932A2
Authority
WO
WIPO (PCT)
Prior art keywords
power supply
high voltage
voltage power
supply
inductor
Prior art date
Application number
PCT/US2001/025648
Other languages
English (en)
Other versions
WO2002014932A3 (fr
Inventor
Herbert S. Gass, Jr.
Alan D. Cleland
Original Assignee
Accelight Investments, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Accelight Investments, Inc. filed Critical Accelight Investments, Inc.
Priority to AU2001290534A priority Critical patent/AU2001290534A1/en
Publication of WO2002014932A2 publication Critical patent/WO2002014932A2/fr
Publication of WO2002014932A3 publication Critical patent/WO2002014932A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/03—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on ceramics or electro-optical crystals, e.g. exhibiting Pockels effect or Kerr effect
    • G02F1/0327—Operation of the cell; Circuit arrangements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/007—Plural converter units in cascade

Definitions

  • the present invention is a driver for a capacitive load and, more specifically, a driver for a capacitive electro-optic device.
  • drivers for capacitive loads such as a capacitive electro-optic device, utilized "a totem pole" arrangement of field effect transistor (FET's) that were connected across a high voltage power supply. Each FET would turn on at an appropriate time to set the voltage across the capacitive load to a high voltage, e.g., 800 volts, or to a low voltage, e.g., zero volts.
  • the FET's would have resistors in series with their power terminals to dissipate some of the energy used to charge or discharge the capacitive load. Without these resistors, the energy utilized to charge or discharge the capacitive load was dissipated by the FET's themselves.
  • the driver includes a first flyback converter connected between a low voltage power supply and a capacitive electro-optic device.
  • the first flyback converter is configured to charge the capacitive electro-optic device from the low voltage power supply.
  • a second flyback converter is connected between the low voltage power supply, the capacitive electro-optic device and a high voltage power supply.
  • the second flyback converter is configured to charge the high voltage power supply from the capacitive electro-optic device.
  • the first and second flyback converters are controlled to charge and discharge the capacitive electro-optic device to first and second predetermined voltages, respectively.
  • a boost/buck converter is connected to the low voltage power supply and the high voltage power supply.
  • the boost/buck converter is configured to transfer charge between the low voltage power supply and the high voltage power supply for maintaining the high voltage power supply at a predetermined high voltage.
  • a driver for a capacitive load that includes a first converter connected between a low voltage supply and the capacitive load for charging the capacitive load to a first voltage from the low voltage power supply.
  • a second converter is connected between the capacitive load and the high voltage power supply for discharging the capacitive load into the high voltage power supply and to a second voltage.
  • a recovery supply is connected between the high voltage power supply and the low voltage power supply for transferring charge therebetween to maintain the high voltage power supply at its operating voltage.
  • Fig. 1 is a schematic drawing of a driver circuit for a capacitive load, such as a capacitive electro-optic device, in accordance with the present invention
  • FIGs. 2a and 2b are schematic drawings showing the connection of inputs to outputs of a capacitive electro-optic device in response to a first voltage and a second voltage, respectively;
  • FIG. 3 is a detailed schematic drawing of the energy recovery power supply shown in Fig. 1.
  • a driver 2 for a capacitive load such as a capacitive electro-optic device 4 includes a low voltage power supply 6, a high voltage power supply 8, a first flyback converter 10, a second flyback converter 12 and a pulse generator 14 for controlling first flyback converter 10 and second flyback converter 12.
  • driver 2 can include a first ring catching circuit 16 associated with first flyback converter 10 and a second ring catching circuit 18 associated with second flyback converter 12.
  • driver 2 includes an energy recovery power supply 20 connected between low voltage power supply 6 and high voltage power supply 8.
  • First flyback converter 10 includes a first flyback transformer 22 having a primary side 24 connected between low voltage power supply 6 and a reference voltage or ground 26, and a secondary side 28 connected between capacitive electro-optic device 4 and ground 26.
  • a transistor switch 30 is connected in series with primary side 24 between primary side 24 and ground 26.
  • a first rectifier 32 is connected in series with secondary side 28.
  • Second flyback converter 12 includes a second flyback transformer 34 having a primary side 36 connected between low voltage power supply 6 and ground 26, and a secondary side 38 connected between high voltage power supply 8 and capacitive electro-optic device 4.
  • a transistor switch 40 is connected in series with primary side 36 between primary side 36 and ground 26.
  • a second rectifier 40 is connected in series with secondary side 38.
  • Capacitive electro-optic device 4 can essentially be considered a capacitor 42 having one end connected to the cathode side of first rectifier 32 and the anode side of second rectifier 40. The other end of capacitor 42 is connected to ground 26.
  • Each rectifier 32 and 40 includes a plurality of low capacitance, fast reverse recovery diodes 44 connected in series.
  • the number of diodes 44 forming each rectifier 32 and 40 is selected so that during operation of flyback converters 10 and 12, the voltage drop across each diode 44 does not exceed the maximum rated voltage of each diode 44.
  • flyback transformers 22 and 34 have matched transformer properties. To the extent flyback transformers 22 and 34 do not have matched transformer properties, control signals supplied to transistors 30 and 40 by pulse generator 14 can be controlled to cause flyback transformers 22 and 34 to have matched responses.
  • an exemplary capacitive electro-optic device 4 is an optical switch which includes first and second inputs 44 and 46 and first and second outputs 48 and 50.
  • capacitor 42 When capacitor 42 is charged to a first voltage, e.g., zero volts, capacitive electro-optic device 4 will route an optical signal received on first input 44 to first output 48 and will route an optical signal received on second input 46 to second output 50.
  • a second voltage e.g. 800 volts
  • capacitive electro-optic device 4 routes an optical signal received on first input 44 to second output 50 and routes an optical signal received on second input 46 to first output 48.
  • capacitive electro-optic device 4 selectively routes optical signals therethrough.
  • Capacitive electro-optic devices of this type are well known in the art.
  • Low voltage power supply 6 includes a direct current (DC) source 52 and one or more capacitors 54 connected in parallel with DC source 52.
  • DC source 52 and capacitor 54 are connected to supply and receive power to and from energy recovery power supply 20.
  • High voltage power supply 8 includes one or more capacitors 56 which are connected to supply and receive power from energy recovery power supply 20 and to receive power from capacitive electro-optic device 4.
  • DC source 52 receives power from an external source (not shown).
  • energy recovery power supply 20 operates in a boost mode to charge high voltage power supply 8 to its operating voltage, e.g., 800 volts, from the operating voltage, e.g., 96 volts, of low voltage power supply 6.
  • pulse generator 14 can control flyback converter 10 to charge capacitor 42 to a high voltage, e.g., 800 volts, or can control flyback converter 12 to discharge capacitor 42 to a low voltage, e.g., zero volts.
  • pulse generator 14 In order to charge capacitor 42 to a high voltage, pulse generator 14 outputs a first pulse control signal which causes transistor 30 to switch on for a brief interval. During this brief interval, current flows through primary side 24 of first flyback transformer 22 from low voltage power supply 6, through transistor 40 to ground 26. This current produces a magnetic field in first flyback transformer 22. When the first pulse control signal switches off, the magnetic energy stored in first flyback transformer 22 dissipates itself as a first current which flows from first flyback transformer 22, through first rectifier 32 and into capacitor 42 whereupon capacitor 42 is charged to a high voltage related to the pulse width of the first pulse control signal. Preferably, this high voltage matches the operating voltage of high voltage power supply 8.
  • high voltage power supply 8 outputs a voltage that is equal to or greater than the voltage on capacitor 42, essentially all of the first current output by first flyback transformer 22 flows into capacitor 42.
  • the rise time of the voltage developed across first flyback transformer 22 when transistor 30 switches off is essentially one-fourth (1/4) of the resonant period of the magnetic inductances at secondaries 28 and 38 of first and second flyback transformers 22 and 34, the parasitic capacitances of first and second flyback transformers 22 and 34 and the capacitance of capacitor 42.
  • the first control signal is supplied to transistor 30 as a refresh pulse control signal having a duration which is capable of causing first flyback transformer 22 to supply to capacitor 42 a charging current which maintains capacitor 42 at its high voltage.
  • pulse generator 14 In order to discharge or set capacitor 42 to a low voltage, e.g., zero volts, pulse generator 14 outputs a second pulse control signal which causes transistor 40 to turn on for a brief interval. Importantly, to avoid unintended discharge of capacitor 42, the first and second pulse control signals are not switched on at the same time.
  • transistor 40 When transistor 40 is on for this brief interval, current flows through primary side 36 of second flyback transformer 34 from low voltage power supply 6, through transistor 40 to ground 26. This current produces a magnetic field in second flyback transformer 34.
  • the second pulse control signal switches off, the magnetic energy stored in second flyback transformer 34 dissipates itself as second current which flows from capacitor 42, through second rectifier 40, through second flyback transformer 34 and into high voltage power supply 8.
  • This second current is produced in response to the voltage that develops across second flyback transformer 34 when the second pulse control signal turns off.
  • This voltage is sufficient in amplitude to cause the second current to flow from capacitor 42 into high voltage power supply 8 either when capacitor 42 is operating at its high voltage or when capacitor 42 is operating at its low voltage.
  • the rise time of the voltage developed across second flyback transformer 34 when transistor 40 switches off is essentially one-fourth (1/4) of the resonant period of the magnetic inductances at secondaries 28 and 38 of the first and second flyback transformers 22 and 34, the parasitic capacitances of the first and second flyback transformers 22 and 34 and the capacitance of capacitor 42.
  • the second pulse control signal is supplied to transistor 40 as a refresh pulse control signal having a duration which is capable of causing second flyback transformer 34 to charge high voltage power supply 8 with a charging current from capacitor 42 of capacitive electro-optic device 4. Drawing this current from capacitor 42 to charge high voltage power supply 8 maintains capacitor 42 at its low voltage.
  • the voltage of capacitive electro-optic device 4 can be set to any desired voltage.
  • first and second pulse control signals switch off, most of the energy stored in first flyback transformer 22 and second flyback transformer 34 dissipates as the first current flowing into capacitor 42 or as the second current flowing out of capacitor 42, respectively.
  • each flyback transformer 22 and 34 includes parasitic capacitances which coact with the inductance of the flyback transformer and capacitor 42 to produce undesirable electrical ringing.
  • first ring catching circuit 16 is associated with first flyback converter 10 and second ring catching circuit 18 is associated with second flyback converter 12.
  • First ring catching circuit 16 includes a transistor 58 connected across primary 24 of first flyback transformer 22.
  • Transistor 58 has a first power terminal connected to the side of primary 24 which is comiected to low voltage power supply 6 and a second power terminal is connected to the other side of primary 24 through a diode 60.
  • Diode 60 has its anode connected to the second power terminal of transistor 58 and its cathode comiected to the other side of primary 24 opposite low voltage power supply 6.
  • a zener diode 62 has its anode comiected to the control input of transistor 58 and its cathode connected to the first power terminal of transistor 58. Zener diode 62 sets the bias on transistor 58 to avoid excessive current flowing therethrough.
  • ring catching circuit 16 includes a capacitor 64 connected between pulse generator 14 and the control input of transistor 58.
  • Second ring catching circuit 16 includes a transistor 68, diode 70, zener diode 72 and a capacitor 74 connected in the same manner as like named elements of first ring catching circuit 16. Second ring catching circuit 18, however, is connected across primary 36 of second flyback transformer 34.
  • pulse generator 14 In order to dissipate or avoid ringing in first flyback transformer 22, pulse generator 14 outputs a third pulse control signal which causes transistor 58 to switch on and remain on whenever transistor 30 is switched off. When transistor 58 is switched on, any ringing in first flyback transformer 22 will dissipate across transistor 58 and diode 60. Similarly, pulse generator 14 outputs a fourth pulse control signal which causes transistor 68 to switch on and remain on whenever transistor 40 is switched off. When transistor 68 is switched on, any ringing in second flyback transformer 34 will dissipate across transistor 68 and diode 70.
  • First switching circuit 78 includes one or more transistors 82 connected to conduct current between high voltage power supply 8 and inductor 76.
  • a control input of each transistor 82 is connected to a pulse transformer 84.
  • the other side of pulse transformer 84 is connected to a buck control circuit 86.
  • buck control circuit 86 is a Unitrode UCC 2813-0 DC-to-DC fixed frequency current-mode switching power supply manufactured by Texas Instruments Incorporated.
  • Buck control circuit 86 outputs a buck pulse control signal which causes transistor 82 to turn on for a brief interval.
  • the power terminal of transistor 82 opposite inductor 76 is connected to high voltage power supply 8 via a current transformer 88.
  • Current transformer 88 is responsive to current flowing therethrough from high voltage power supply 8 toward inductor 76 for outputting a current feedback to buck control circuit 86.
  • a diode 90 is connected between the power lead of transistor 82 connected to inductor 76 and high voltage power supply 8 and is oriented to conduct current from inductor 76 to high voltage power supply 8.
  • Second switching circuit 80 includes one or more transistors 92 having their power terminals comiected between the end of inductor 76 opposite low voltage power supply 6 and a low voltage return 94 of low voltage power supply 6.
  • Each fransistor 92 has a control input connected to receive a boost pulse control signal from a boost confrol circuit 96.
  • boost control circuit 96 is a Unitrode UCC 2813-0 DC-to-DC fixed frequency current-mode switching power supply manufactured by Texas Instruments Incorporated.
  • a low resistance, high power resistor 98 is connected to detect current flowing between inductor 76 and low voltage return 94 through second switching circuit 80. The voltage drop across resistor 98 in response to current flowing therethrough is supplied as a current feedback to boost control circuit 96.
  • a resistor 100 is connected between low voltage return
  • a difference amplifier 104 is connected to detect a voltage drop across resistor 100 and to supply to buck control circuit 86 a feedback control signal indicative thereof.
  • a Feedback/PID control circuit 106 compares the operating voltage of high voltage power supply to a reference voltage and provides to buck confrol circuit 86 a feedback control signal which has a proportional-integral- derivative (PID) relationship to the difference between the operating voltage of high voltage power supply 8 and the reference voltage.
  • PID proportional-integral- derivative
  • a biasing circuit 108 is connected to supply to boost control circuit 96 a current command signal which is utilized to control the turn off threshold of boost confrol circuit 96 based on the current feedback from resistor 98.
  • the feedback control signals received by buck control circuit 86 from differential amplifier 104 and Feedback/PID confrol circuit 106 are utilized to control the turn off threshold of buck control circuit 86 based on the current feedback from current transformer 88.
  • Energy recovery power supply 20 includes a buck zero crossing comparator 110 and a boost zero crossing comparator 112 connected for detecting the voltage on the side of inductor 76 opposite low voltage power supply 6 and for outputting a buck sync signal and a boost sync signal, respectively, as a function thereof.
  • the buck sync signal and the boost sync signal control when buck control circuit 86 and boost confrol circuit 96 turn on the one or more transistors 82 and the one or more transistors 92, respectively.
  • a voltage monitor circuit 114 is connected to detect the operating voltages of low voltage power supply 6 and high voltage power supply 8 for controlling the operation of boost and buck confrol circuits 86 and 96.
  • This boost pulse control signal causes transistor 92 to conduct a first current from low voltage power supply 6 through inductor 76 and resistor 96 to ground 26 for the brief interval transistor 92 is conducting.
  • the duration of this brief interval is based on the inputs to boost control circuit 96 by biasing circuit 108 and the current feedback into boost confrol circuit 96 from resistor 98. More specifically, when the current feedback from resistor 98 achieves a predetermined relationship to the bias applied to boost control circuit 96 by biasing circuit 108, boost control circuit 96 terminates the boost pulse control signal whereupon transistor 92 turns off.
  • inductor 76 In response to transistor 92 turning off, the magnetic energy stored in inductor 76 in response to the first current flowing therethrough causes inductor 76 to charge high voltage power supply 8 through diode 90.
  • the voltage drop across resistor 100 in response to this first current is detected by difference amplifier 104 which provides an appropriate feedback control signal to buck control circuit 86 as a function thereof.
  • Feedback/PID control circuit 108 monitors the operating voltage of high voltage power supply 8 and outputs an appropriate feedback confrol signal to buck control circuit 86 as a function thereof.
  • buck zero crossing comparator 110 outputs a buck sync signal whereupon buck control circuit 86 outputs a buck pulse control signal to pulse transformer 84 which causes transistor 82 to turn on for a brief interval.
  • a second current flows from high voltage power supply 8 to capacitor 54 of low voltage power supply 6 through current transformer 88, transistor 82 and inductor 76.
  • the duration of tins brief interval is based on the feedback control signals received at the inputs of buck control circuit 86 and the current feedback into buck control circuit 86 from current transformer 88. More specifically, when the current feedback from current transformer 88 achieves a predetermined relationship to the bias applied to buck confrol circuit 86 by the feedback confrol signals, buck control circuit 86 terminates the buck confrol signal whereupon transistor 82 turns off.
  • the feedback control signals and the current feedback received by buck confrol circuit 86 cause the duration of buck pulse control signals to increase with the increase in the voltage of high voltage power supply 8 to its operating voltage.
  • each buck pulse control signal turns off, the second current terminates flowing through inductor 76 whereupon the voltage across inductor 76 decreases.
  • boost zero crossing comparator 112 causes boost control circuit 96 to output a boost pulse control signal which causes fransistor 92 to turn on for the brief interval determined by the current command signal and current feedback into boost control circuit 96.
  • inductor 76 charges high voltage power supply 8 through diode 90 with the first current that is flowing in inductor 76 at the moment transistor 92 turns off.
  • buck zero crossing comparator 110 causes buck control circuit 86 to output a buck pulse control signal which causes fransistor 82 to turn on for the brief interval determined by the feedback confrol signals and the current feedback into buck control circuit 86.
  • transistor 82 is on for this brief interval, high voltage power supply 8 charges low voltage power supply 6 via inductor 76.
  • fransistor 82 turns off causing the voltage across inductor 76 to decrease to zero whereupon boost zero crossing comparator 112 causes boost control circuit to output another boost pulse control signal.
  • energy recovery power supply 20 continues in this manner to continuously and ongoingly transfer charge between high voltage power supply 8 and low voltage power supply 6.
  • the combination of zero crossing comparators 110 and 112, and buck and boost control circuits 86 and 96 implement resonant fransition switching where the edges of the rise and fall times of the voltage across inductor 76 during no load switching, i.e., when no current flows into or out of high voltage power supply 8, are each essentially one-fourth (1/4) the resonant frequency of the output capacitances of fransistors 82 and 92 in combination with the inductance of inductor 76.
  • the present invention is a driver 2 for a capacitive electro-optic device 4.
  • the driver 2 includes a first flyback converter 10 comiected between low voltage power supply 6 and capacitive electro-optic device 4 for charging capacitive electro-optic device 4 to its operating voltage from low voltage power supply 6.
  • a second flyback converter 12 is connected between capacitive electro-optic device 4 and high voltage power supply 8 for discharging capacitive electro-optic device 4 into high voltage power supply 8 and to a second voltage.
  • a recovery power supply 20 is connected between high voltage power supply 8 and low voltage power supply 6 for transferring charge therebetween to maintain high voltage power supply 8 at its operating voltage.
  • recovery power supply 20 charges high voltage power supply 8 to its operating voltage from the operating voltage of low voltage power supply 6.

Abstract

L'invention concerne un circuit d'attaque (2) destiné à une charge capacitive (4) et comprenant un premier convertisseur (10) conçu pour charger la charge capacitive (4) jusqu'à une première tension à partir d'une alimentation basse tension (6), un second convertisseur (12) conçu pour décharger la charge capacitive (4) dans une alimentation haute tension (8) jusqu'à une seconde tension, ainsi qu'une alimentation de récupération d'énergie (20) destinée à transférer la charge entre l'alimentation haute tension (8) et l'alimentation basse tension (6) en vue de maintenir de l'alimentation haute tension (8) à sa tension de fonctionnement.
PCT/US2001/025648 2000-08-16 2001-08-16 Circuit d'attaque a recyclage d'energie pour charge capacitive WO2002014932A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001290534A AU2001290534A1 (en) 2000-08-16 2001-08-16 Energy recirculating driver for capacitive load

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US22569400P 2000-08-16 2000-08-16
US60/225,694 2000-08-16

Publications (2)

Publication Number Publication Date
WO2002014932A2 true WO2002014932A2 (fr) 2002-02-21
WO2002014932A3 WO2002014932A3 (fr) 2002-05-10

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Application Number Title Priority Date Filing Date
PCT/US2001/025648 WO2002014932A2 (fr) 2000-08-16 2001-08-16 Circuit d'attaque a recyclage d'energie pour charge capacitive

Country Status (2)

Country Link
AU (1) AU2001290534A1 (fr)
WO (1) WO2002014932A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3719563A1 (fr) * 2019-04-01 2020-10-07 UAB Light Conversion Contrôle arbitraire de l'amplitude, de la polarisation et de la phase de la lumière dans des systèmes à laser pulsé

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3568095A (en) * 1967-10-19 1971-03-02 Sits Soc It Telecom Siemens Self-balancing modulator for suppression of carrier wave
US5982644A (en) * 1998-12-16 1999-11-09 Hughes Electronics Corporation Voltage boost circuit for a high voltage converter
US6191957B1 (en) * 2000-01-31 2001-02-20 Bae Systems Controls, Inc. Extended range boost converter circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3568095A (en) * 1967-10-19 1971-03-02 Sits Soc It Telecom Siemens Self-balancing modulator for suppression of carrier wave
US5982644A (en) * 1998-12-16 1999-11-09 Hughes Electronics Corporation Voltage boost circuit for a high voltage converter
US6191957B1 (en) * 2000-01-31 2001-02-20 Bae Systems Controls, Inc. Extended range boost converter circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3719563A1 (fr) * 2019-04-01 2020-10-07 UAB Light Conversion Contrôle arbitraire de l'amplitude, de la polarisation et de la phase de la lumière dans des systèmes à laser pulsé

Also Published As

Publication number Publication date
WO2002014932A3 (fr) 2002-05-10
AU2001290534A1 (en) 2002-02-25

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