WO2002003471A1 - Dispositif et structure semi-conductrice hybride - Google Patents
Dispositif et structure semi-conductrice hybride Download PDFInfo
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- WO2002003471A1 WO2002003471A1 PCT/US2001/016733 US0116733W WO0203471A1 WO 2002003471 A1 WO2002003471 A1 WO 2002003471A1 US 0116733 W US0116733 W US 0116733W WO 0203471 A1 WO0203471 A1 WO 0203471A1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02513—Microstructure
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
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Definitions
- This inventio relates generally to semiconductor structures' ' ' ' and devices and to a method for their fabrication, and more specifically to semiconductor structures'-and devices each of which is a hybrid of a monocrystalline semiconductor material and a monocrystalline compound semiconductor material.
- GaAs Gallium arsenide
- silicon wafers are available up to about 300 mm and are widely available at 200 mm.
- the 150 mm GaAs wafers are many times more expensive than are their silicon counterparts. Wafers of other compound semiconductor materials are even less available and are more expensive than GaAs.
- compound semiconductor materials have desirable characteristics that make them useful for certain types of applications.
- silicon or other non-compound semiconductor materials are more useful for other types of applications, and it is sometimes desirable to have a single device with some of its circuitry made in silicon and some of its circuitry made in a compound semiconductor material such as GaAs.
- FIGs. 1, 2 , 3, 9, 10 illustrate schematically, in cross section, device structures that can be used in accordance with various embodiments of the invention.
- FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer.
- FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of illustrative semiconductor material manufactured in accordance with what is shown herein.
- FIG. 6 is an x-ray diffraction taken on an illustrative semiconductor structure manufactured in accordance with what is shown herein.
- TEM Transmission Electron Micrograph
- FIG. 7 illustrates a high resolution Transmission Electron Micrograph of a structure including an amorphous oxide layer.
- FIG. 8 illustrates an x-ray diffraction spectrum of a structure including an amorphous oxide layer.
- FIGs. 11-15 include illustrations of cross- sectional views of a portion of an integrated circuit that includes a compound semiconductor portion, a bipolar portion, and an MOS portion in accordance with what is shown herein.
- FIG. 16 shows a cross-sectional view of a hybrid semiconductor structure including silicon semiconductor islands on a compound semiconductor substrate.
- FIGs. 17 and 18 show a cross-sectional and a plan view, respectively, of a hybrid semiconductor structure including silicon semiconductor islands in a compound semiconductor substrate.
- FIG. 19 shows an intermediate step in the formation of the hybrid structure of FIGs. 17 and 18.
- FIG. 20 shows a further optional processing step in the formation of the hybrid structure of FIGs. 17 and 18.
- FIG. 21 shows a cross-sectional view of a portion of an integrated circuit that includes a compound semiconductor portion and an MOS portion in accordance with what is shown herein.
- FIGs. 22 and 23 show, in cross-sectional and plan views, respectively, an inductor formed in accordance with what is shown herein.
- FIG. 24 shows a cross-sectional view of a first embodiment of a capacitor formed in accordance with what is shown herein.
- FIG. 25 shows a cross-sectional view of a second embodiment of a capacitor formed in accordance with what is shown herein.
- the present invention involves semiconductor structures of particular types.
- these semiconductor structures are sometimes referred to as "composite semiconductor structures" or “composite integrated circuits” because they include two (or more) significantly different types of semiconductor devices in one integrated structure or circuit.
- one of these two types of devices may be silicon-based devices such as CMOS devices, and the other of these two types of devices may be compound semiconductor devices such GaAs devices.
- Illustrative composite semiconductor structures and methods for making such structures are disclosed in Ra dani et al. U.S. patent application No. 09/502,023, filed February 10, 2000, which is hereby incorporated by reference herein in its entirety. Certain material from that reference is substantially repeated below to ensure that there is support herein for references to composite semiconductor structures and composite integrated circuits.
- FIG. 1 illustrates schematically, in cross section, a portion of a semiconductor structure 20 which may be relevant to or useful in connection with certain embodiments of the present invention.
- Semiconductor structure 20 includes a monocrystalline substrate 22, accommodating buffer layer 24 comprising a monocrystalline material, and a layer 26 of a monocrystalline compound semiconductor material.
- monocrystalline shall have the meaning commonly used within the semiconductor industry.
- the term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.
- structure 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24.
- Structure 20 may also include a template layer 30 between accommodating buffer layer 24 and compound semiconductor layer 26.
- template layer 30 helps to initiate the growth of compound semiconductor layer 26 on accommodating buffer layer 24.
- Amorphous intermediate layer 28 helps to relieve the strain in accommodating buffer layer 24 and by doing so, aids in the growth of a high crystalline quality accommodating buffer layer 24.
- Substrate 22 in accordance with one embodiment, is a monocrystalline semiconductor wafer, preferably of large diameter.
- the wafer can be of a material from Group IV of the periodic table, and preferably a material from Group IVA.
- Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like.
- substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry.
- Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate 22.
- amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer 24 by the oxidation of substrate 22 during the growth of layer 24.
- Amorphous intermediate layer 28 serves to relieve strain that might otherwise occur in monocrystalline accommodating buffer layer 24 as a result of differences in the lattice constants of substrate 22 and buffer layer 24.
- lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by amorphous intermediate layer 28, the strain may cause defects in the crystalline structure of accommodating buffer layer 24. Defects in the crystalline structure of accommodating buffer layer 24, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline compound semiconductor layer 26.
- Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with underlying substrate 22 and with overlying compound semiconductor material 26.
- the material could be an oxide or nitride having a lattice structure matched to substrate 22 and to the subsequently applied semiconductor material 26.
- Materials that are suitable for accommodating buffer layer 24 include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for accommodating buffer layer 24.
- metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates
- a orphous interface layer 28 is preferably an oxide formed by the oxidation of the surface of substrate 22, and more preferably is composed of a silicon oxide. The thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating ' buffer layer 24. Typically, layer 28 has a thickness in the range of approximately 0.5-5 nm.
- the compound semiconductor material of layer 26 can be selected, as needed for a particular semiconductor structure, from any of the Group IIIA and VA elements (III-V semiconductor compounds) , mixed III- V compounds, Group II (A or B) and VIA elements (II-VI semiconductor compounds), and mixed II-VI compounds.
- Examples include gallium arsenide (GaAs) , gallium indium arsenide (GalnAs) , gallium aluminum arsenide (GaAlAs) , indium phosphide (InP) , cadmium sulfide (CDs) , cadmium mercury telluride (CdHgTe) , zinc selenide (ZnSe) , zinc sulfur selenide (ZnSSe) , and the like.
- Suitable template 30 materials chemically bond to the surface of the accommodating buffer layer 24 at selected sites and provide sites for the nucleation of the epitaxial growth of the subsequent compound semiconductor layer 26. Appropriate materials for template 30 are discussed below.
- FIG. 2 illustrates, in cross section, a portion of a semiconductor structure 40 in accordance with a further embodiment.
- Structure 40 is similar to the previously described semiconductor structure 20 except that an additional buffer layer 32 is positioned between accommodating buffer layer 24 and layer of monocrystalline compound semiconductor material 26. Specifically, additional buffer layer 32 is positioned between the template layer 30 and the overlying layer 26 of compound semiconductor material.
- Additional buffer layer 32 formed of a semiconductor or compound semiconductor material, serves to provide a lattice compensation when the lattice constant of accommodating buffer layer 24 cannot be adequately matched to the overlying monocrystalline compound semiconductor material layer 26.
- FIG. 3 schematically illustrates, in cross section, a portion of a semiconductor structure 34 in accordance with another exemplary embodiment of the invention.
- Structure 34 is similar to structure 20, except that structure 34 includes an amorphous layer 36, rather than accommodating buffer layer 24 and amorphous interface layer 28, and an additional semiconductor layer 38.
- amorphous layer 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above.
- Monocrystalline semiconductor layer 26 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer.
- the accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer.
- Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate.
- layer 36 may comprise one or two amorphous layers. Formation of amorphous layer 36 between substrate 22 and semiconductor layer 38 (subsequent to layer 38 formation) relieves stresses between layers 22 and 38 and provides a true compliant substrate for subsequent processing— e . g. , compound semiconductor layer 26 formation
- semiconductor layer 38 may include any of the materials described throughout this application in connection with either of compound semiconductor material layer 26 or additional buffer layer 32.
- layer 38 may include monocrystalline Group IV or monocrystalline compound semiconductor materials.
- semiconductor layer 38 serves as an anneal cap during layer 36 formation and as a template for subsequent semiconductor layer 26 formation. Accordingly, layer 38 is preferably thick enough to provide a suitable template for layer 26 growth (at least one monolayer) and thin enough to allow layer 38 to form as a substantially defect free monocrystalline semiconductor compound.
- semiconductor layer 38 comprises compound semiconductor material (e.g., a material discussed above in connection with compound semiconductor layer 26) that is thick enough to form devices within layer 38.
- compound semiconductor material e.g., a material discussed above in connection with compound semiconductor layer 26
- a semiconductor structure in accordance with the present invention does not include compound semiconductor layer 26.
- the semiconductor structure in accordance with this embodiment only includes one compound semiconductor layer disposed above amorphous oxide layer 36.
- the layer formed on substrate 22, whether it includes only accommodating buffer layer 24, accommodating buffer layer 24 with amorphous intermediate or interface layer 28, or an amorphous layer such as layer 36 formed by annealing layers 24 and 28 as described above in connection with FIG. 3, may be referred to generically as an "accommodating layer. "
- monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction.
- Silicon substrate 22 can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200-300 mm.
- accommodating buffer layer 24 is a monocrystalline layer of Sr z Ba ⁇ - z Ti ⁇ 3 where z ranges from 0 to 1 and amorphous intermediate layer 28 is a layer of silicon oxide (SiO x ) formed at the interface between silicon substrate 22 and accommodating buffer layer 24. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer 26.
- Accommodating buffer layer 24 can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 10 nm. In general, it is desired to have an accommodating buffer layer 24 thick enough to isolate compound semiconductor layer 26 from substrate 22 to obtain the desired electrical and optical properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed.
- the amorphous intermediate layer 28 of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1.5-2.5 nm.
- compound semiconductor material layer 26 is a layer of gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) having a thickness of about 1 nm to about 100 micrometers ( ⁇ m) and preferably a thickness of about 0.5 ⁇ m to 10 ⁇ m. The thickness generally depends on the application for which the layer is being prepared.
- a template layer 30 is formed by capping the oxide layer. Template layer 30 is preferably 1-10 monolayers of Ti-As, Sr-O-As, Sr-Ga-O, or Sr-Al-O. By way of a preferred example, 1-2 monolayers 30 of Ti-As or Sr-Ga-0 have been shown to successfully grow GaAs layers 26.
- monocrystalline substrate 22 is a silicon substrate as described above.
- Accommodating buffer layer 24 is a monocrystalline oxide of strontium or barium zirconate or hafnate in a cubic or orthorhombic phase with an amorphous intermediate layer 28 of silicon oxide formed at the interface between silicon substrate 22 and accommodating buffer layer 24.
- Accommodating buffer layer 24' can have a thickness of about 2-100 nm and preferably has a thickness of at least 5 nm to ensure adequate crystalline and surface quality and is formed of a monocrystalline SrZr0 3 , BaZr0 3 , SrHf0 3 , BaSn0 3 or BaHf0 3 :
- a monocrystalline oxide layer of BaZr0 3 can grow at a temperature of about 700 degrees C.
- the lattice structure of the resulting crystalline oxide exhibits a 45 degree rotation with respect to the substrate 22 silicon lattice structure.
- An accommodating buffer layer 24 formed of these zirconate or hafnate materials is suitable for the growth of compound semiconductor materials 26 in the indium phosphide (InP) system.
- the compound semiconductor material 26 can be, for example, indium phosphide (InP), indium gallium arsenide (InGaAs) , aluminum indium arsenide, (AlInAs) , or aluminum gallium indium arsenic phosphide (AlGalnAsP) , having a thickness of about 1.0 nm to 10 ⁇ m.
- a suitable template 30 for this structure is 1-10 monolayers of zirconium-arsenic (Zr-As) , zirconium-phosphorus (Zr-P) , hafnium-arsenic (Hf-As) , hafnium-phosphorus (Hf-P) , strontium-oxygen-arsenic (Sr-O-As) , strontium-oxygen- phosphorus (Sr-O-P) , barium-oxygen-arsenic (Ba-O-As) , indium-strontium-oxygen (In-Sr-O) , or barium-oxygen- phosphorus (Ba-O-P) , and preferably 1-2 monolayers of one of these materials.
- a barium zirconate accommodating buffer layer 24 the surface is terminated with 1-2 monolayers of zirconium followed by deposition of 1-2 monolayers of arsenic to form a Zr-As template 30.
- a monocrystalline layer 26 of the compound semiconductor material from the indium phosphide system is then grown on template layer 30.
- the resulting lattice structure of the compound semiconductor material 26 exhibits a 45 degree rotation with respect to the accommodating buffer layer 24 lattice structure and a lattice mismatch to (100) InP of less than 2.5%, and preferably less than about 1.0%.
- a structure is provided that is suitable for the growth of an epitaxial film of a II-VI material overlying a silicon substrate 22.
- the substrate 22 is preferably a silicon wafer as described above.
- a suitable accommodating buffer layer 24 material is Sr x Ba ⁇ - x Ti ⁇ 3 , where x ranges from 0 to 1, having a thickness of about 2-100 nm and preferably a thickness of about 5-15 nm.
- the II-VI compound semiconductor material 26 can be, for example, zinc selenide (ZnSe) or zinc sulfur selenide (ZnSSe) .
- a suitable template 30 for this material system includes 1-10 monolayers of zinc-oxygen (Zn-O) followed by 1-2 monolayers of an excess of zinc followed by the selenidation of zinc on the surface.
- a template 30 can be, for example, 1-10 monolayers of strontium-sulfur (Sr-S) followed by the ZnSeS.
- This embodiment of the invention is an example of structure 40 illustrated in FIG. 2.
- Substrate 22, monocrystalline oxide layer 24, and monocrystalline compound semiconductor material layer 26 can be similar to those described in example 1.
- an additional buffer layer 32 serves to alleviate any strains that might result from a mismatch of the crystal lattice of the accommodating buffer layer and the lattice of the monocrystalline semiconductor material.
- Buffer layer 32 can be a layer of germanium or a GaAs, an aluminum gallium arsenide (AlGaAs) , an indium gallium phosphide (InGaP), an aluminum gallium phosphide (AlGaP) , an indium gallium arsenide (InGaAs), an aluminum indium phosphide (AllnP) , a gallium arsenide phosphide (GaAsP) , or an indium gallium phosphide (InGaP) strain compensated superlattice.
- AlGaAs aluminum gallium arsenide
- InGaP aluminum gallium phosphide
- AlGaP aluminum gallium phosphide
- AllnP aluminum indium phosphide
- GaAsP gallium arsenide phosphide
- InGaP indium gallium phosphide
- buffer layer 32 includes a GaAs x P ⁇ _ x superlattice, wherein the value of x ranges from 0 to 1.
- buffer layer 32 includes an In y Ga ⁇ - y P superlattice, wherein the value of y ranges from 0 to 1.
- the lattice constant is varied from bottom to top across the superlattice to create a match between lattice constants of the underlying oxide and the overlying compound semiconductor material.
- the compositions of other materials, such as those listed above, may also be similarly varied to manipulate the lattice constant of layer 32 in a like manner.
- the superlattice can have a thickness of about 50-500 nm and preferably has a thickness of about 100-200 nm.
- buffer layer 32 can be a layer of monocrystalline germanium having a thickness of 1-50 nm and preferably having a thickness of about 2-20 nm.
- a template layer of either germanium-strontium (Ge-Sr) or germanium-titanium (Ge-Ti) having a thickness of about one monolayer can be used as a nucleating site for the subsequent growth of the monocrystalline compound semiconductor material layer.
- the formation of the oxide layer is capped with either a monolayer of strontium or a monolayer of titanium to act as a nucleating site for the subsequent deposition of the monocrystalline germanium.
- the monolayer of strontium or titanium provides a nucleating site to which the first monolayer of germanium can bond.
- buffer layer 32 is inserted between accommodating buffer layer 24 and overlying monocrystalline compound semiconductor material layer 26.
- Buffer layer 32 a further monocrystalline semiconductor material, can be, for example, a graded layer of indium gallium arsenide (InGaAs) or indium aluminum arsenide (InAlAs) .
- buffer layer 32 includes InGaAs, in which the indium composition varies from 0 to about 47%. Buffer layer 32 preferably has a thickness of about 10-30 nm.
- Varying the composition of buffer layer 32 from GaAs to InGaAs serves to provide a lattice match between the underlying monocrystalline oxide material 24 and the overlying layer 26 of monocrystalline compound semiconductor material.
- Such a buffer layer 32 is especially advantageous if there is a lattice mismatch between accommodating buffer layer 24 and monocrystalline compound semiconductor material layer 26.
- Substrate material 22, template layer 30, and monocrystalline compound semiconductor material layer 26 may be the same as those described above in connection with example 1.
- Amorphous layer 36 is an amorphous oxide layer which is suitably formed of a combination of amorphous intermediate layer materials (e.g., layer 28 materials as described above) and accommodating buffer layer materials (e.g., layer 24 materials as described above) .
- amorphous layer 36 may include a combination of SiOx and SrzBal-z Ti03 (where z ranges from 0 to 1) ,which combine or mix, at least partially, during an anneal process to form amorphous oxide layer 36.
- amorphous layer 36 may vary from -application to application and may depend on such factors as desired insulating properties of layer 36, type of semiconductor material comprising layer 26, and the like. In accordance with one exemplary aspect of the present embodiment, layer 36 thickness is about 2 nm to about 100 nm, preferably about 2-10 nm, and more preferably about 5-6 nm.
- Layer 38 comprises a monocrystalline compound semiconductor material that can be grown epitaxially over a monocrystalline oxide material such as material used to form accommodating buffer layer 24.
- layer 38 includes the same materials as those comprising layer 26.
- layer 26 includes GaAs
- layer 38 also includes GaAs.
- layer 38 may include materials different from those used to form layer 26.
- layer 38 is about 1 monolayer to about 100 nm thick.
- substrate 22 is a monocrystalline substrate such as a monocrystalline silicon substrate.
- the crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation.
- accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation.
- the lattice constants of accommodating buffer layer 24 and monocrystalline substrate 22 must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved.
- the terms "substantially equal” and “substantially matched” mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer.
- FIG. 4 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal.
- Curve 42 illustrates the boundary of high crystalline quality material. The area to the right of curve 42 represents layers that tend to be polycrystalline. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved.
- substrate 22 is a (100) or (111) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate.
- Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material 24 by 45° with respect to the crystal orientation of the silicon substrate wafer 22.
- layer 26 is a layer of epitaxially grown monocrystalline material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation.
- the lattice constant of layer 26 differs from the lattice constant of substrate 22.
- accommodating buffer layer 24 must be of high crystalline quality.
- substantial matching between the crystal lattice constant of the host crystal, in this case, monocrystalline accommodating buffer layer 24, and grown crystal 26 is desired.
- host material 24 is a strontium or barium zirconate or a strontium or barium hafnate or barium tin oxide and compound semiconductor layer 26 is indium phosphide or gallium indium arsenide or aluminum indium arsenide
- substantial matching of crystal lattice constants can be achieved by rotating the orientation of grown crystal layer 26 by 45° with respect to host oxide crystal 24.
- a crystalline semiconductor buffer layer 32 between host oxide 24 and grown compound semiconductor layer 26 can be used to reduce strain in grown monocrystalline compound semiconductor layer 26 that might result from small differences in lattice constants. Better crystalline quality in grown monocrystalline compound semiconductor layer 26 can thereby be achieved.
- the following example illustrates a process, in accordance with one embodiment, for fabricating a semiconductor structure such as the structures depicted in FIGS. 1-3.
- the process starts by providing a monocrystalline semiconductor substrate 22 comprising silicon or germanium.
- semiconductor substrate 22 is a silicon wafer having a (100) orientation.
- Substrate 22 is preferably oriented on axis or, at most, about 0.5° off axis.
- At least a portion of semiconductor substrate 22 has a bare surface, although other portions of the substrate, as described below, may encompass other structures.
- the term "bare" in this context means that the surface in the portion of substrate 22 has been cleaned to remove any oxides, contaminants, or other foreign material.
- bare silicon is highly reactive and readily forms a native oxide.
- the term "bare" is intended to encompass such a native oxide.
- a thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process.
- the native oxide layer In order to epitaxially grow a monocrystalline oxide layer 24 overlying monocrystalline substrate 22, the native oxide layer must first be removed to expose the crystalline structure of underlying substrate 22. The following process is preferably carried out by molecular beam epitaxy (MBE) , although other epitaxial processes may also be used in accordance with the present invention.
- MBE molecular beam epitaxy
- the native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus.
- the substrate 22 is then heated to a temperature of about 750°C to cause the strontium to react with the native silicon oxide layer.
- the strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface.
- the resultant surface which exhibits an ordered 2x1 structure, includes strontium, oxygen, and -silicon.
- the ordered 2x1 structure forms a template for the ordered growth of an overlying layer 24 of a monocrystalline oxide.
- the template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer 24.
- the native silicon oxide can be converted and the surface of substrate 22 can be prepared for the growth of a monocrystalline oxide layer 24 by depositing an alkali earth metal oxide, such as strontium oxide or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750°C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate 22 surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer 24.
- an alkali earth metal oxide such as strontium oxide or barium oxide
- the substrate is cooled to a temperature in the range of about 200-800°C and a layer 24 of strontium titanate is grown on the template layer by molecular beam epitaxy.
- the MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources.
- the ratio of strontium and titanium is approximately 1:1.
- the partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value.
- the overpressure of oxygen causes the growth of an amorphous silicon oxide layer 28 at the interface between underlying substrate 22 and the growing strontium titanate layer 24.
- the growth of silicon oxide layer 28 results from the diffusion of oxygen through the growing strontium titanate layer 24 to the interface where the oxygen reacts with silicon at the surface of underlying substrate 22.
- the strontium titanate grows as an ordered monocrystal 24 with the crystalline orientation rotated by 45° with respect to the ordered 2x1 crystalline structure of underlying substrate 22. Strain that otherwise might exist in strontium titanate layer 24 because of the small mismatch in lattice constant between silicon substrate 22 and the growing crystal 24 is relieved in amorphous silicon oxide intermediate layer 28.
- the monocrystalline strontium titanate is capped by a template layer 30 that is conducive to the subsequent growth of an epitaxial layer of a desired compound semiconductor material 26.
- the MBE growth of strontium titanate monocrystalline layer 24 can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen.
- arsenic is deposited to form a Ti-As bond, a Ti-O-As bond or a Sr-O-As. Any of these form an appropriate template 30 for deposition and formation of a gallium arsenide monocrystalline layer 26.
- gallium is subsequently introduced to the reaction with the arsenic and gallium arsenide 26 forms.
- gallium can be deposited on the capping layer to form a Sr-O-Ga bond, and arsenic is subsequently introduced with the gallium to form the GaAs.
- FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with the present invention.
- Single crystal SrTi03 accommodating buffer layer 24 was grown epitaxially on silicon substrate 22. During this growth process, amorphous interfacial layer 28 is formed which relieves strain due to lattice mismatch.
- GaAs compound semiconductor layer 26 was then grown epitaxially using template layer 30.
- FIG. 6 illustrates an x-ray diffraction spectrum taken on structure including GaAs compound semiconductor layer 26 grown on silicon substrate 22 using accommodating buffer layer 24.
- the peaks in the spectrum indicate that both the accommodating buffer layer 24 and GaAs compound semiconductor layer 26 are single crystal and (100) orientated.
- the structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of an additional buffer layer 32 deposition step.
- Buffer layer 32 is formed overlying template layer 30 before the deposition of monocrystalline compound semiconductor layer 26. If buffer layer 32 is a compound semiconductor superlattice, such a superlattice can be deposited, by MBE for example, on the template 30 described above.
- buffer layer 32 is a layer of germanium
- the process above is modified to cap strontium titanate monocrystalline layer 24 with a final layer of either strontium or titanium and then by depositing germanium to react with the strontium or- titanium.
- the germanium buffer layer 32 can then be deposited directly on this template 30.
- Structure 34 may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate 22, and growing semiconductor layer 38 over the accommodating buffer layer, as described above.
- the accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer 36.
- Layer 26 is then subsequently grown over layer 38.
- the anneal process may be carried out subsequent to growth of layer 26.
- layer 36 is formed by exposing substrate 22, the accommodating buffer layer, the amorphous oxide layer, and semiconductor layer 38 to a rapid thermal anneal process with a peak temperature of about 700°C to about 1000°C and a process time of about 1 to about 10 minutes.
- suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention.
- laser annealing or "conventional" thermal annealing processes in the proper environment
- an overpressure of one or more constituents of layer 30 may be required to prevent degradation of layer 38 during the anneal process.
- the anneal environment preferably includes an overpressure of arsenic to mitigate degradation of layer 38.
- layer 38 of structure 34 may include any materials suitable for either of layers 32 or 26. Accordingly, any deposition or growth methods described in connection with either layer 32 or 26, may be employed to deposit layer 38.
- FIG. 7 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with the embodiment of the invention illustrated in FIG. 3.
- TEM Transmission Electron Micrograph
- a single crystal SrTi03 accommodating buffer layer was grown epitaxially on silicon substrate 22. During this growth process, an amorphous interfacial layer forms as described above.
- GaAs layer 38 is formed above the accommodating buffer layer and the accommodating buffer layer is exposed to an anneal process to form amorphous oxide layer 36.
- FIG. 8 illustrates an x-ray diffraction spectrum taken on a structure including GaAs compound semiconductor layer 38 and amorphous oxide layer 36 formed on silicon substrate 22.
- the peaks in the spectrum indicate that GaAs compound semiconductor layer 38 is single crystal and (100) orientated and the lack of peaks around 40 to 50 degrees indicates that layer 36 is amorphous.
- the process described above illustrates a ' process for forming a semiconductor structure including a silicon substrate 22, an overlying oxide layer, and a monocrystalline gallium arsenide compound semiconductor layer 26 by the process of molecular beam epitaxy.
- the process can also be carried out by the process of chemical vapor deposition (CVD) , metal organic chemical vapor deposition (MOCVD) , migration enhanced epitaxy (MEE) , atomic layer epitaxy (ALE) , physical vapor deposition (PVD) , chemical solution deposition (CSD) , pulsed laser deposition (PLD) , or the like.
- CVD chemical vapor deposition
- MOCVD metal organic chemical vapor deposition
- MEE migration enhanced epitaxy
- ALE atomic layer epitaxy
- PVD physical vapor deposition
- CSSD chemical solution deposition
- PLD pulsed laser deposition
- monocrystalline accommodating buffer layers 24 such as alkaline .earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown.
- other III-V and II-VI monocrystalline compound semiconductor layers 26 can be deposited overlying monocrystalline oxide accommodating buffer layer 24.
- each of the variations of compound semiconductor materials 26 and monocrystalline oxide accommodating buffer layer 24 uses an appropriate template 30 for initiating the growth of the compound semiconductor layer.
- accommodating buffer layer 24 is an alkaline earth metal zirconate
- the oxide can be capped by a thin layer of zirconium.
- the deposition of zirconium can be followed by the deposition of arsenic or phosphorus to react with the zirconium as a precursor to depositing indium gallium arsenide, indium aluminum arsenide, or indium phosphide respectively.
- monocrystalline oxide accommodating buffer layer 24 is an alkaline earth metal hafnate, the oxide layer can be capped by a thin layer of hafnium.
- hafnium is followed by the deposition of arsenic or phosphorous to react with the hafnium as a precursor to the growth of an indium gallium arsenide, indium aluminum arsenide, or indium phosphide layer 26, respectively.
- strontium titanate 24 can be capped with a layer of strontium or strontium and oxygen
- barium titanate 24 can be capped with a layer of barium or barium and oxygen.
- Each of these depositions can be followed by the deposition of arsenic or phosphorus to react with the capping material to form a template 30 for the deposition of a compound semiconductor material layer 26 comprising indium gallium arsenide, indium aluminum arsenide, or indium phosphide.
- FIG. 9 illustrates schematically, in cross section, a device structure 50 in accordance with a further embodiment.
- Device structure 50 includes a monocrystalline semiconductor substrate 52, preferably a monocrystalline silicon wafer.
- Monocrystalline semiconductor substrate 52 includes two regions, 53 and 54.
- An electrical semiconductor component generally indicated by the dashed line 56 is formed, at least partially, in region 53.
- Electrical component 56 can be a resistor, a capacitor, an active semiconductor component such as a diode or a transistor or an integrated circuit such as a CMOS integrated circuit.
- electrical semiconductor component 56 can be a CMOS integrated circuit configured to perform digital signal processing or another function for which silicon integrated circuits are well suited.
- the electrical semiconductor component in region 53 can be formed by conventional semiconductor processing as well known and widely practiced in the semiconductor industry.
- a layer of insulating material 58 such as a layer of silicon dioxide or the like may overlie electrical semiconductor component 56.
- Insulating material 58 and any other layers that may have been formed or deposited during the processing of semiconductor component 56 in region 53 are removed from the surface of region 54 to provide a bare silicon surface in that region.
- bare silicon surfaces are highly reactive and a native silicon oxide layer can quickly form on the bare surface.
- a layer of barium or barium and oxygen is deposited onto the native oxide layer on the surface of region 54 and is reacted with the oxidized surface to form a first template layer (not shown) .
- a monocrystalline oxide layer is formed overlying the template layer by a process of molecular beam epitaxy. Reactants including barium, titanium and oxygen are deposited onto the template layer to form the monocrystalline oxide layer.
- the partial pressure of oxygen is kept near the minimum necessary to fully react with the barium and titanium to form monocrystalline barium titanate layer.
- the partial pressure of oxygen is then increased to provide an overpressure of oxygen and to allow oxygen to diffuse through the growing monocrystalline oxide layer.
- the oxygen diffusing through the barium titanate reacts with silicon at the surface of region 54 to form an amorphous layer of silicon oxide on second region 54 and at the interface between silicon substrate 52 and the monocrystalline oxide.
- Layers 60 and 62 may be subject to an annealing process as described above in connection with FIG. 3 to form a single amorphous accommodating layer.
- the step of depositing the monocrystalline oxide layer is terminated by depositing a second template layer 60, which can be 1-10 monolayers of titanium, barium, barium and oxygen, or titanium and oxygen.
- a layer 66 of a monocrystalline compound semiconductor material is then deposited overlying second template layer 64 by a process of molecular beam epitaxy. The deposition of layer 66 is initiated by depositing a layer of arsenic onto template 64. This initial step is followed by depositing gallium and arsenic to form monocrystalline gallium arsenide 66.
- strontium can be substituted for barium in the above example.
- a semiconductor component is formed in compound semiconductor layer 66.
- Semiconductor component 68 can be formed by processing steps conventionally used in the fabrication of gallium arsenide or other III-V compound semiconductor material devices.
- Semiconductor component 68 can be any active or passive component, and preferably is a semiconductor laser, light emitting diode, photodetector, heterojunction bipolar transistor (HBT) , high frequency MESFET, or other component that utilizes and takes advantage of the physical properties of compound semiconductor materials.
- HBT heterojunction bipolar transistor
- a metallic conductor schematically indicated by the line 70 can be formed to electrically couple device 68 and device 56, thus implementing an integrated device that includes at least one component formed in silicon substrate 52 and one device formed in monocrystalline compound semiconductor material layer 66.
- illustrative structure 50 has been described as a structure formed on a silicon substrate 52 and having a barium (or strontium) titanate layer 60 and a gallium arsenide layer 66, similar devices can be fabricated using other substrates, monocrystalline oxide layers and other compound semiconductor layers as described elsewhere in this disclosure.
- FIG. 10 illustrates a semiconductor structure 72 in accordance with a further embodiment.
- Structure 72 includes a monocrystalline semiconductor substrate 74 such as a monocrystalline silicon wafer that includes a region 75 and a region 76.
- An electrical component schematically illustrated by the dashed line 78 is formed in region 75 using conventional silicon device processing techniques commonly used in the semiconductor industry.
- a monocrystalline oxide layer 80 and an intermediate amorphous silicon oxide layer 82 are formed overlying region 76 of substrate 74.
- a template layer 84 and subsequently a monocrystalline semiconductor layer 86 are formed overlying monocrystalline oxide layer 80.
- an additional monocrystalline oxide layer 88 is formed overlying layer 86 by process steps similar to those used to form layer 80, and an additional monocrystalline semiconductor layer 90 is formed overlying monocrystalline oxide layer 88 by process steps similar to those used to form layer 86.
- at least one of layers 86 and 90 are formed from a compound semiconductor material. Layers 80 and 82 may be subject to an annealing process as described above in connection with FIG. 3 to form a single amorphous accommodating layer.
- a semiconductor component generally indicated by a dashed line 92 is formed at least partially in monocrystalline semiconductor layer 86.
- semiconductor component 92 may include a field effect transistor having a gate dielectric formed, in part, by monocrystalline oxide layer 88.
- monocrystalline semiconductor layer 90 can be used to implement the gate electrode of that field effect transistor.
- monocrystalline semiconductor layer 86 is formed from a group III-V compound and semiconductor component 92 is a radio frequency amplifier that takes advantage of the high mobility characteristic of group III-V component materials.
- an electrical interconnection schematically illustrated by the line 94 electrically interconnects component 78 and component 92. Structure 72 thus integrates components that take advantage of the unique properties of the two monocrystalline semiconductor materials.
- the illustrative composite semiconductor structure or integrated circuit 102 shown in FIGs. 6-10 includes a compound semiconductor portion 1022, a bipolar portion 1024, and a MOS portion 1026.
- a p-type doped, monocrystalline silicon substrate 110 is provided having a compound semiconductor portion 1022, a bipolar portion 1024, and an MOS portion 1026.
- the monocrystalline silicon substrate 110 is doped to form an N + buried region 1102.
- a lightly p-type doped epitaxial monocrystalline silicon layer 1104 is then formed over the buried region 1102 and the substrate 110.
- a doping step is then performed to create a lightly n-type doped drift region 1117 above the N + buried region 1102.
- the doping step converts the dopant type of the lightly p-type epitaxial layer within a section of the bipolar region 1024 to a lightly n-type monocrystalline silicon region.
- a field isolation region 1106 is then formed between the bipolar portion 1024 and the MOS portion 1026.
- a gate dielectric layer 1110 is formed over a portion of the epitaxial layer 1104 within MOS portion 1026, and the gate electrode 1112 is then formed over the gate dielectric layer 1110.
- Sidewall spacers 1115 are formed along vertical sides of the gate electrode 1112 and gate dielectric layer 1110.
- a p-type dopant is introduced into the drift region 1117 to form an active or intrinsic base region 1114.
- An n-type, deep collector region 1108 is then formed within the bipolar portion 1024 to allow electrical connection to the buried region 1102.
- Selective n-type doping is performed to form N + doped regions 1116 and the emitter region 1120.
- N + doped regions 1116 are formed within layer 1104 along adjacent sides of the gate electrode 1112 and are source, drain, or source/drain regions for the MOS transistor.
- the N + doped regions 1116 and emitter region 1120 have a doping concentration of at least 1E19 atoms per cubic centimeter to allow ohmic contacts to be formed.
- a p-type doped region is formed to create the inactive or extrinsic base region 1118 which is a P + doped region (doping concentration of at least 1E19 atoms per cubic centimeter) .
- several processing steps have been performed but are not illustrated or further described, such as the formation of well regions, threshold adjusting implants, channel punchthrough prevention implants, field punchthrough prevention implants, as well as a variety of masking layers.
- the formation of the device up to this point in the process is performed using conventional steps. As illustrated, a standard N-channel MOS transistor has been formed within the MOS region 1026, and a vertical NPN bipolar transistor has been formed within the bipolar portion 1024. As of this point, no circuitry has been formed within the compound semiconductor portion 1022.
- All of the layers that have been formed during the processing of the bipolar and MOS portions of the integrated circuit are now removed from the surface of compound semiconductor portion 1022.
- a bare silicon surface is thus provided for the subsequent processing of this portion, for example in the manner set forth above.
- An accommodating buffer layer 124 is then formed over the substrate 110 as illustrated in FIG. 12.
- the accommodating buffer layer will form as a monocrystalline layer over the properly prepared (i.e., having the appropriate template layer) bare silicon surface in portion 1022.
- the portion of layer 124 that forms over portions 1024 and 1026 may be polycrystalline or amorphous because it is formed over a material that is not monocrystalline, and therefore, does not nucleate monocrystalline growth.
- the accommodating buffer layer 124 typically is a monocrystalline metal oxide or nitride layer and typically has a thickness in a range of approximately 2-100 nanometers. In one particular embodiment, the accommodating buffer layer is approximately 5-15 nm thick.
- an amorphous intermediate layer 122 is formed along the uppermost silicon surfaces of the integrated circuit 102. This amorphous intermediate layer 122 typically includes an oxide of silicon and has a thickness and range of approximately 1-5 nm. In one particular embodiment, the thickness is approximately 2 nm.
- a template layer 126 is then formed and has a thickness in a range of approximately one to ten monolayers of a material.
- the material includes titanium-arsenic, strontium-oxygen-arsenic, or other similar materials as previously described with respect to FIGS. 1-5.
- Layers 122 and 124 may be subject to an annealing process as described above in connection with FIG. 3 to form a single amorphous accommodating layer.
- a monocrystalline compound semiconductor layer 132 is then epitaxially grown overlying the monocrystalline portion of accommodating buffer layer 124 (or over the amorphous accommodating layer if the annealing process described above has been carried out) as shown in FIG. 13.
- the portion of layer 132 that is grown over portions of layer 124 that are not monocrystalline may be polycrystalline or amorphous.
- the monocrystalline compound semiconductor layer can be formed by a number of methods and typically includes a material such as gallium arsenide, aluminum gallium arsenide, indium phosphide, or other compound semiconductor materials as previously mentioned.
- the thickness of the layer is in a range of approximately 1-5,000 nm, and more preferably 100-500 nm.
- each of the elements within the template layer are also present in the accommodating buffer layer 124, the monocrystalline compound semiconductor material 132, or both. Therefore, the delineation between the template layer 126 and its two immediately adjacent layers disappears during processing. Therefore, when a transmission electron microscopy (TEM) photograph is taken, an interface between the accommodating buffer layer 124 and the monocrystalline compound semiconductor layer 132 is seen.
- TEM transmission electron microscopy
- the insulating layer 142 can include a number of materials such as oxides, nitrides, oxynitrides, low-k dielectrics, or the like. As used herein, low-k is a material having a dielectric constant no higher than approximately 3.5.
- the insulating layer 142 After the insulating layer 142 has been deposited, it is then polished, removing portions of the insulating layer 142 that overlie monocrystalline compound semiconductor layer 132. A transistor 144 is then formed within the monocrystalline compound semiconductor portion 1022. A gate electrode 148 is then formed on the monocrystalline compound semiconductor layer 132. Doped regions 146 are then formed within the monocrystalline compound semiconductor layer 132. In this embodiment, the transistor 144 is a metal- semiconductor field-effect transistor (MESFET) . If the MESFET is an n-type MESFET, the doped regions 146 and monocrystalline compound semiconductor layer 132 are also n-type doped.
- MESFET metal- semiconductor field-effect transistor
- This particular embodiment includes an n-type MESFET, a vertical NPN bipolar transistor, and a planar n-channel MOS transistor. Many other types of transistors, including P-channel MOS transistors, p-type vertical bipolar transistors, p-type MESFETs, and combinations of vertical and planar transistors, can be used. Also, other electrical components, such as resistors, capacitors, diodes, and the like, may be formed in one or more of the portions 1022, 1024, and 1026.
- An insulating layer 152 is formed over the substrate 110.
- the insulating layer 152 may include an etch-stop or polish-stop region that is not illustrated in FIG. 15.
- a second insulating layer 154 is then formed over the first insulating layer 152. Portions of layers 154, 152, 142, 124, and 122 are removed to define contact openings where the devices are to be interconnected. Interconnect trenches are formed within insulating layer 154 to provide the lateral connections between the contacts.
- interconnect 1562 connects a source or drain region of the n-type MESFET within portion 1022 to the deep collector region 1108 of the NPN transistor within the bipolar portion 1024.
- the emitter region 1120 of the NPN transistor is connected to one of the doped regions 1116 of the n-channel MOS transistor within the MOS portion 1026.
- the other doped region 1116 is electrically connected to other portions of the integrated circuit that are not shown.
- a passivation layer 156 is formed over the interconnects 1562, 1564, and 1566 and insulating layer 154. Other electrical connections are made to the transistors as illustrated as well as to other electrical or electronic components within the integrated circuit 102 but are not illustrated in the FIGs. Further, additional insulating layers and interconnects may be formed as necessary to form the proper interconnections between the various components within the integrated circuit 102.
- active devices for both compound semiconductor and Group IV semiconductor materials can be integrated into a single integrated circuit. Because there is some difficulty in incorporating both bipolar transistors and MOS transistors within a same integrated circuit, it may be possible to move some of the components within bipolar portion into the compound semiconductor portion 1022 or the MOS portion 1024. Therefore, the requirement of special fabricating steps solely used for making a bipolar transistor can be eliminated. Therefore, there would only be a compound semiconductor portion and a MOS portion to the integrated circuit. Although not illustrated, a monocrystalline Group IV wafer can be used in forming only compound semiconductor electrical components over the wafer.
- the wafer is essentially a "handle" wafer used during the fabrication of the compound semiconductor electrical components within a monocrystalline compound semiconductor layer overlying the wafer. Therefore, electrical components can be formed within III-V or II-VI semiconductor materials over a wafer of at least approximately 200 millimeters in diameter and possibly at least approximately 300 millimeters.
- a relatively inexpensive "handle" wafer overcomes the fragile nature of the compound semiconductor wafers by placing them over a relatively more durable and easy to fabricate base material. Therefore, an integrated circuit can be formed such that all electrical components, and particularly all active electronic devices, can be formed within the compound semiconductor material even though the substrate itself may include a Group IV semiconductor material. Fabrication costs for compound semiconductor devices should decrease because larger substrates can be processed more economically and more readily, compared to the relatively smaller and more fragile, conventional compound semiconductor wafers.
- the process heretofore described can be carried out in reverse, as shown in FIGs. 15-21, to provide a semiconductor structure or integrated circuit having both (a) one or more compound semiconductor portions and (b) at least one non-compound semiconductor portion such as a monocrystalline silicon portion, as in FIGs. 11-15, but with the compound semiconductor portion as the substrate.
- the non-compound semiconductor portions resemble "mesas" sitting atop the surface of the compound semiconductor substrate .
- the non-compound semiconductor portions are flush with the surface of a compound semiconductor substrate.
- Hybrid semiconductor device 1150 is similar to hybrid semiconductor device 50 of FIG. 9, except that where semiconductor device 50 includes a non-compound semiconductor with a conventional non-compound semiconductor region 53 and a compound semiconductor "mesa" formed on region 54, hybrid semiconductor device 1150 has a compound semiconductor region 1153 and a non-compound semiconductor "mesa” formed on region 1154.
- device structure 1150 includes a monocrystalline compound semiconductor substrate 1152, preferably a monocrystalline GaAs wafer.
- the process described above preferably is carried out in reverse to form, preferably, template layer 1162 and accommodating buffer layer 1160, respectively similar to template layer 30 and accommodating buffer layer 24 described above.
- Monocrystalline non-compound semiconductor layer 1166 of, e.g., silicon, is then grown on accommodating buffer layer 1160, after which entry of oxygen into accommodating buffer layer 1160 results in the formation of amorphous layer 1164, similar to amorphous layer 28 described above.
- amorphous layer 1164 and accommodating buffer layer 1160 may be annealed to form a single amorphous accommodating layer.
- the layers deposited on monocrystalline compound semiconductor substrate 1152 preferably are removed in region 1153, leaving a "mesa" of monocrystalline non-compound semiconductor material in region 1154.
- a CMOS or other component 1156 may be formed in layer 1166 either before or after removal of material to form the "mesa.”
- An electrical semiconductor component generally indicated by the dashed line 1168 may then be formed in region 1153 of substrate 1152.
- Semiconductor component 1168 can then be formed by processing steps conventionally used in the fabrication of gallium arsenide or other III-V compound semiconductor material devices . ' Insulating material 1158 and any other layers that may be necessary can be formed or deposited during the processing of semiconductor component 1168 in region 1153.
- Semiconductor component 1168 can be any active or passive component, and preferably is a semiconductor laser, light emitting diode, photodetector, heterojunction bipolar transistor (HBT) , high frequency MESFET, or other component that utilizes and takes advantage of the physical properties of compound semiconductor materials.
- Components 1156 and 1168 may be connected by metallization 1170.
- hybrid semiconductor 200 includes a monocrystalline compound semiconductor (e.g., GaAs) substrate 201 in which depressions or wells 202 have been formed. Each well 202 is filled with a non- compound (e.g., silicon) semiconductor portion, which may be thought of as an "island" 204 of non-compound semiconductor in the compound semiconductor, as seen in the plan view of FIG. 18.
- Hybrid semiconductor 200 may be made by forming wells 202 in the compound -- e.g., monocrystalline GaAs -- semiconductor substrate 201.
- Wells 202 may be formed, e.g., by any well-known etching process including both wet and dry etching processes, operating on the compound semiconductor material. While wells 202 may be substantially circular or of other shapes, they preferably are substantially rectangular as shown, with dimensions on the order of hundreds of micrometers on a side, providing an area sufficient to form a useful amount of circuitry.
- Monocrystalline non- compound semiconductor layer 226 of, e.g., silicon, is then grown on accommodating buffer layer 224, after which entry of oxygen into accommodating buffer layer 224 results in the formation of amorphous layer 228, similar to amorphous layer 28 described above.
- the final result is a structure such as that shown in cross section in FIG. 19.
- amorphous layer 228 and accommodating buffer layer 224 may be annealed to form a single amorphous accommodating layer.
- Monocrystalline non-compound semiconductor layer 226 substantially follows the contours of monocrystalline compound semiconductor substrate 201, including the contours of wells 202.
- a polishing step which can be any conventional semiconductor polishing technique such as chemical/mechanical polishing (CMP) , is then used to remove monocrystalline non-compound semiconductor layer 226, amorphous layer 228, accommodating buffer layer 224, and template layer 230, down to the original surface 203 of substrate 201.
- CMP chemical/mechanical polishing
- a trench 206 may be cut around the periphery of island 204, using conventional semiconductor trench-forming techniques, and filled with a suitable insulating material 207, which may be, e.g., a silicon oxide, or one of the components of insulating layer 205.
- a suitable insulating material 207 which may be, e.g., a silicon oxide, or one of the components of insulating layer 205.
- each well 202 preferably is between about 0.5 ⁇ m and about 2 ⁇ m.
- hybrid structure 200 electronic circuitry can be created by forming electronic components 268 and 256 in substrate 201 and island 204, respectively.
- the components can be interconnected by appropriate metallization 270 as shown in FIG. 21, resulting in hybrid integrated circuit device 215.
- Component processing in materials such as monocrystalline silicon is typically carried out at temperatures above about 800° C, while component processing in compound semiconductor materials such as GaAs is typically carried out at lower temperatures, between about 300°C and about 800°C, and components formed in GaAs would be damaged by the higher temperatures of silicon processing (although the unprocessed GaAs itself would not be damaged) . Therefore, preferably components such as component 1156 or 256 are formed first in silicon layer 1166 or silicon island 204 using high-temperature processing. Components such as component 1168 or 268 are then formed in the GaAs substrate 1152 or 201 at the lower processing temperatures, which will not damage the already formed silicon components 1156 or 256.
- the present invention is particularly useful for forming low-loss reactive elements -- i.e., inductors and capacitors -- in semiconductor devices.
- the resistivity of the semiconductor substrate is relatively low, meaning that the electromagnetic fields in reactive elements formed in such semiconductor devices induce in the substrate currents of sufficient magnitude to cause significant losses in those reactive elements.
- the resistivity of the semiconductor substrate is relatively high, meaning that the electromagnetic fields in reactive elements formed in such semiconductor devices induce in the substrate currents, if any, of insufficient magnitude to cause significant losses in those reactive elements'.
- reactive elements may be formed in compound semiconductor portions but connected electrically to components in non-compound semiconductor portions, such as islands 204.
- the reactive element is formed over compound semiconductor substrate 201, the relatively high resistivity of substrate 201, particularly if it is GaAs, will minimize the formation of eddy currents, thereby minimizing losses.
- the reactive element is formed over island 204 which may have a relatively low resistivity, particularly if it is silicon, the majority of the material over which the reactive element is formed is not the material of island 204, but that of substrate 201, which is of relatively high resistivity, underlying island 204.
- island 204 may have low resistivity, it is formed in such a thin layer (about 0.5 ⁇ m to about 2 ⁇ m, as discussed above) that its bulk resistance, which is dependent on the cross section which is small, is relatively high. Thus, even in the material of island 204, the eddy currents induced, and therefore the losses, are relatively small.
- FIGs. 22 and 23 show a preferred embodiment of a square inductor 300 formed over GaAs substrate 201 as described above.
- Inductor 300 is essentially a number of square turns of a metallic line 301, spaced apart from substrate 201 by insulating oxide 302.
- a first contact 303 is provided at end 304 of line 301.
- a second contact 305 which contacts the other end 306 inside the square "spiral" of line 301, tunnels through oxide 302 to a point underneath end 306 (contact 305 may also extend over end 306 instead of under) , where a conductive material 307, formed using standard multilevel metallization techniques allows contact with end 306.
- Inductor 300 is formed completely overlying GaAs substrate 201, so that loss-generating eddy currents are minimized because of the relatively high resistivity of the GaAs.
- FIG. 24 shows a preferred embodiment of a capacitor 400 formed partially in GaAs substrate 201, using insulating layer 205 as a dielectric.
- a portion 2021 of the GaAs floor of well 2020 is doped in a conventional manner.
- Portion 2021 preferably extends to surface 203 of substrate 201 on one or both sides of well 2020 (only one side shown in FIG. 24) to facilitate making an electrical connection to portion 2021.
- Some or all of the three component layers of layer 205 are then formed and optionally annealed as described above (accommodating buffer layer 224 is required, but template layer 230 may not be required; amorphous layer 228 will not form if an oxidizable material is not deposited above it) .
- well 2020 instead of being filled with silicon or another non-compound monocrystalline semiconductor, well 2020 preferably is filled at least partially with metal 2022.
- Capacitor 400 includes as its two "plates" metal island 2022 and doped GaAs region 2021, with layer 205 serving as its dielectric. Loss-generating currents are minimized because of the relatively high resistivity of underlying GaAs substrate 201.
- a capacitor 450 also can be formed as shown in FIG. 25, which is similar to FIG. 16.
- a metal layer 451 (which may also be a doped GaAs region) is formed on GaAs substrate 1152 to serve as one plate of capacitor 450.
- layer 451 preferably extends past one or both ends of capacitor 450 (only the left end shown in FIG. 25) to facilitate making an electrical connection.
- template layer 1162 (optional) and accommodating buffer layer 1160 are formed.
- metal layer 452 (alternatively, a gate electrode material may be used) is formed atop accommodating buffer layer 1160 as the second plate of capacitor 450. Because there is no oxidizable material, no oxide layer forms, and accommodating buffer layer 1160 is the only component of the accommodating layer. Layer 1160 may. optionally be annealed as described above .
- a hybrid semiconductor structure comprising: a monocrystalline compound semiconductor substrate; an accommodating layer overlying said monocrystalline compound semiconductor substrate; and a monocrystalline non-compound semiconductor material overlying said accommodating layer.
- said monocrystalline compound semiconductor substrate has a substantially flat surface, and said substantially flat surface has at least one well therein; said accommodating layer overlies said monocrystalline compound semiconductor substrate in said at least one well; and said monocrystalline non-compound semiconductor material overlies said accommodating layer in said at least one well.
- said accommodating layer further comprises an amorphous layer between said monocrystalline non-compound semiconductor material and said monocrystalline oxide material.
- hybrid semiconductor structure of claim 1 further comprising a template layer between said accommodating layer and said monocrystalline compound semiconductor substrate.
- hybrid semiconductor structure of claim 1 further comprising a plurality of electronic components, wherein: at least one of said electronic components at least partially overlies said monocrystalline compound semiconductor substrate; and at least one of said electronic components at least partially overlies said monocrystalline non-compound semiconductor material.
- at least one of said electronic components comprises a reactive component.
- said monocrystalline compound semiconductor substrate has a substantially flat surface, and said substantially flat surface has at least one well therein; said accommodating layer overlies said monocrystalline compound semiconductor substrate in said at least one well; and said capacitor comprises a portion adjacent said monocrystalline compound semiconductor substrate and a portion in one of said at least one well, said portions being separated by said dielectric comprising said accommodating layer.
- said monocrystalline silicon substrate, said amorphous oxide material, and said monocrystalline perovskite oxide material are all overlaid by said monocrystalline compound semiconductor substrate.
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Abstract
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PCT/US2001/016733 WO2002003471A1 (fr) | 2000-06-30 | 2001-05-21 | Dispositif et structure semi-conductrice hybride |
Country Status (2)
Country | Link |
---|---|
AU (1) | AU2001261811A1 (fr) |
WO (1) | WO2002003471A1 (fr) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5995359A (en) * | 1994-06-18 | 1999-11-30 | U.S. Philips Corporation | Electronic component and method of manufacturing same |
US6146906A (en) * | 1998-09-16 | 2000-11-14 | Nec Corporation | DC magnetron sputtering method for manufacturing electrode of ferroelectric capacitor |
US6180252B1 (en) * | 1996-08-12 | 2001-01-30 | Energenius, Inc. | Semiconductor supercapacitor system, method for making same and articles produced therefrom |
-
2001
- 2001-05-21 AU AU2001261811A patent/AU2001261811A1/en not_active Abandoned
- 2001-05-21 WO PCT/US2001/016733 patent/WO2002003471A1/fr active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5995359A (en) * | 1994-06-18 | 1999-11-30 | U.S. Philips Corporation | Electronic component and method of manufacturing same |
US6180252B1 (en) * | 1996-08-12 | 2001-01-30 | Energenius, Inc. | Semiconductor supercapacitor system, method for making same and articles produced therefrom |
US6146906A (en) * | 1998-09-16 | 2000-11-14 | Nec Corporation | DC magnetron sputtering method for manufacturing electrode of ferroelectric capacitor |
Also Published As
Publication number | Publication date |
---|---|
AU2001261811A1 (en) | 2002-01-14 |
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