WO2002001638A2

WO2002001638A2 - Microelectronic packages including reactive components, and methods of fabricating the same

Info

Publication number: WO2002001638A2
Application number: PCT/IB2001/001157
Authority: WO
Inventors: Ramaswamy Mahadevan
Original assignee: Jds Uniphase Corporation
Priority date: 2000-06-30
Filing date: 2001-06-21
Publication date: 2002-01-03
Also published as: WO2002001638A3; AU2001274414A1

Abstract

Microelectronic packages include at least one reactive component, such as a capacitor, inductor and/or mutual inductor that may be of fixed or variable value. At least one reactive component is fabricated on a first face of a first substrate. The first face of the first substrate is placed adjacent a second face of a second substrate, with at least one solder bump between the at least one reactive component and the second face. The at least one solder bump is reflowed, to join the at least one reactive component to the second substrate. The reflowing may be followed by releasing the first substrate from the at least one reactive component.

Description

MICROELECTRONIC PACKAGES INCLUDING REACTIVE COMPONENTS, AND METHODS OF FABRICATING THE SAME

Cross-Reference to Provisional Application This application claims the benefit of provisional Application No. 60/215,553, filed June 30, 2000, entitled High Q Inductors and Capacitors and Methods of Fabricating Same, the disclosure of which is hereby incorporated herein in its entirety as if set forth fully herein.

Field of the Invention

This invention relates to microelectronic components and methods of fabricating the same, and more particularly to microelectronic packages and methods of fabricating the same.

Background of the Invention

Integrated circuits, also referred to as chips, are widely used in consumer and commercial applications. In many of these applications, it may be desirable to provide reactive components that can be used with the integrated circuit to form a microelectronic package. As is well known to those having skill in the art, reactive components include capacitors, inductors and mutual inductors, and may be of fixed value or variable value. Thus, for example, it may be desirable to provide high quality factor (Q) inductors and/or capacitors for use in Radio Frequency (RF) applications.

Microelectronic inductors and -fabrication methods are described, for example, in U.S. Patents 5,478,773 to Dow et al., entitled Methods of Making an Electronic Device Having an Integrated Inductor, 6,002,161 to Yamazaki, entitled Semiconductor Device Having Inductor Element Made of First Conductive Layer of Spiral Configuration Electrically Connected to Second Conductive Layer of Insular Configuration; 6,008,102 to Alford et al., entitled Method of Forming a Three-Dimensional Integrated Inductor, 6,030,877 to Lee et al., entitled Electroless Gold Plating Method for Forming Inductor Structures; and 6,057,202 to Chen et al., entitled Method for Manufacturing an Inductor with Resonant Frequency and Q value Increased in Semiconductor Process. Microelectronic capacitors and fabrication methods are described, for example, in U.S. Patent 6,215,644 to Dhuler, entitled High Frequency Tunable Capacitors.

Summary of the Invention Embodiments of the present invention provide methods of fabricating microelectronic packages that include at least one reactive component, such as a capacitor, inductor and/or mutual inductor that may be of fixed or variable value. According to embodiments of the invention, at least one reactive component is fabricated on a first face of a first substrate. The first face of the first substrate is placed adjacent a second face of a second substrate, with at least one solder bump between the at least one reactive component and the second face. The at least one solder bump is reflowed, to join the at least one reactive component to the second substrate. In other embodiments, the reflowing is followed by releasing the first substrate from the at least one reactive component. According to other embodiments, the at least one reactive component includes a capacitor. The capacitor is fabricated by forming a first capacitor electrode on or in the first face of the first substrate, forming a sacrificial layer on the first capacitor electrode opposite the first face and forming a second capacitor electrode on the sacrificial layer opposite the first capacitor electrode. At least some of the sacrificial layer is removed, to provide a variable capacitor.

Moreover, in other method embodiments, an inductor is formed on the first face of the first substrate, simultaneous with the forming of the second capacitor electrode, and spaced apart from the first capacitor electrode. According to other method embodiments, the at least one reactive component includes a variable mutual inductor. The variable mutual inductor is fabricated by forming a first mutual inductor coil on or in the first face of the first substrate, forming a sacrificial layer on the first mutual inductor coil opposite the first face, and forming a second mutual inductor coil on the sacrificial layer opposite the first mutual inductor coil. At least some of the sacrificial layer is removed, to thereby provide a variable mutual inductor. Microelectronic packages according to embodiments of the invention include a first substrate having a first face, at least one reactive component on the first face, and a second substrate having a second face that is adjacent the first face. At least one solder bump is provided between the at least one reactive component and the second face, and is configured to mechanically and electrically connect the at least one reactive component to the second substrate.

In some package embodiments of the present invention, the at least one reactive component includes a variable capacitor. The variable capacitor comprises a first capacitor electrode on or in the first face of the first substrate, and a second, movable, capacitor electrode facing and spaced apart from the first capacitor electrode. Moreover, in other package embodiments, an inductor also is provided on the first face of the substrate, spaced apart from the first capacitor electrode, wherein the second, movable, capacitor electrode and the inductor comprise portions of a single layer.

In yet other package embodiments, the at least one reactive component is a variable mutual inductor. The variable mutual inductor comprises a first mutual inductor coil on or in the first face of the first substrate, and a second mutual inductor coil facing and spaced apart from the first mutual inductor coil. Finally, in package embodiments that include an inductor, the at least one solder bump may comprise a pair of solder bumps between the respective pair of ends of the inductor and the second face of the second substrate. A third solder bump also may be provided between an intermediate portion of the inductor and the second face of the second substrate.

Brief Description of the Drawings

Figures 1-9 are cross-sectional views of microelectronic packages including at least one reactive component, and fabrication methods therefor, according to embodiments of the present invention.

Detailed Description of Preferred Embodiments

The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

When reactive components, such as inductors and/or capacitors are formed on a conventional silicon semiconductor substrate, the capacitance between the substrate and the inductor may limit the Q, the self-resonant frequency and/or the maximum operating frequency that is obtainable. According to embodiments of the invention, as illustrated in Figure 1, a reactive component such as a spiral inductor 110 may be formed on an insulating or semi-insulating substrate 120, such as quartz, glass, alumina, sapphire and/or gallium arsenide. Inductors 110 also may be formed on an insulating layer 130, such as silicon nitride, on the silicon substrate 120, wherein the silicon substrate is back-etched to remove the silicon substrate adjacent the inductor, as shown at 140, so that an inductor 110 on a silicon nitride or other diaphragm 130a may be formed.

Other reactive components, such as capacitors, also may be formed on the insulating or semi-insulating substrate 120, separate from or along with the one or more inductors 110. Capacitors also may be formed, alone or along with one or more inductors 110, on a back-etched 140 silicon substrate 120 having an insulating layer 130 thereon. Referring now to Figure 2, in other embodiments, a spiral inductor and/or a capacitor 210 may be formed on a conventional substrate 220, such as a silicon substrate, over a release layer 230, such as PMMA. As shown in Figure 3, the inductor and/or capacitor 210 may be bonded to a second substrate 320, for example using flip-chip (solder bump) bonding. The release layer 230 may be dissolved to remove the first substrate 220.

As also shown in Figure 3, solder bumps 340a and 340b may be configured to provide electrical connections between the inductor and/or capacitor 210 and the second substrate 320. As shown in Figure 3, as few as two solder bumps 340a and 340b may be used to provide electrical and mechanical connections from the inductor and/or capacitor 210 to the second substrate 320. Alternatively, more than two solder bumps may be used, where some of the solder bumps 340c may only provide mechanical support at intermediate portions of the inductor and or capacitor 210, whereas others of the solder bumps 340a and 340b may provide electrical connections at the ends of the inductor and/or capacitor 210 and also may provide mechanical support. The solder bumps 340c that only provide mechanical support may be of a different height and/or area than the solder bumps 340a and 340b that provide electrical connections. Alternatively, they all can be of the same height and/or area.

Accordingly, referring again to Figures 2 and 3, a microelectronic package may be fabricated by fabricating at least one reactive component 210 on a first face 220a of the first substrate 220. The first face 220a of the first substrate 220 is placed adjacent a second face 320a of the second substrate 320, with at least one solder bump 340a-340c between the at least one reactive component 210 and the second face 320a. The at least one solder bump 340a-340c is reflowed to join the at least one reactive component 210 to the second substrate 320. In other embodiments, after reflowing, the first substrate 220 may be released from the at least one reactive component 210, for example by dissolving the release layer 230. , Referring now to Figure 4, in yet other embodiments, if a reactive component such as an inductor 410 is formed on an insulating or semi-insulating substrate 420, the substrate 420 may need not be released when it is flip-chip bonded to a second substrate 440. Large solder bumps 450 may be used for mechanical support of the substrate, and smaller solder bumps 460 may be used for electrical connection. In yet other embodiments, substrates 120 of Figure 1, including an insulating layer 130 and a reactive component 110 may be used instead of the first substrate 220 of Figure 3 and/or the first substrate 420 of Figure 4.

Other embodiments for providing high Q capacitors and/or inductors fabricate the capacitor and/or inductor using conductors that are thicker than conventional thin film microelectronic layers. For example, thin film microelectronic layers may be on the order of lμm in thickness. In contrast, thick conductors may be formed that are greater than about 20μm in thickness and that may be, for example, about lOOμm in thickness. Electroplating, sputtering, silk screening, ceramic co-firing and/or other thick film technologies may be used to form the thick conductors. Referring to Figures 5A and 5B, a spiral high Q inductor 510 can be made by electroplating and/or depositing copper and/or gold on an insulating or semi-insulating substrate 520, such as alumina and/or other low loss ceramic. As shown in Figure 5B, which is a cross-section of Figure 5A, the thickness t, the width w and/or the intercoil space s may be chosen based on the desired Q and/or the desired intracoil capacitance. The inner and outer coil diameter Di, D₀, and t, w and s can determine the inductance L and/or the self-resonant frequency of the inductor 510. Inductors also may be made using a well known LIGA and or optical LIGA-like plating processes that are widely used to fabricate microelectromechanical systems (MEMS) devices. The reactive component may be fabricated on a silicon substrate, released from the substrate, and attached to a desired integrated circuit or board using flip-chip assembly as was described above and/or using conventional electronic assembly techniques.

Referring now to Figure 6, high Q capacitors 610 can be formed on quartz or other insulating or semi-insulating substrates 620 using a low loss dielectric 630 such as BCB and/or air. The dielectric 630 that is selected can influence the range of capacitance per unit area. Other dielectrics that may be used include low pressure CVD silicon dioxide. The lower electrode 640 may be thinner, for example about 2μ.m to about 6μm of gold/copper, whereas the upper electrode 650 may be thicker, for example greater than about 20μ.m and preferably about lOOμm of gold and/or chromium. In other embodiments, both the lower and upper electrodes may be made as thin or as thick as desired, so as to provide the desired Q at the desired operating frequency. Rather than using BCB for layer 630, a release or sacrificial layer, such as PMMA may be used to create a capacitor with an air dielectric. This also can provide a tunable or variable capacitor, and can be flip-chip-mounted on, or otherwise bonded to, a second substrate as was described in connection with Figures 3-4.

Inductors and capacitors may be fabricated on the same substrate using embodiments that are described in Figures 7A-7C. In Figure 7A, the capacitor lower electrode 740, such as about 2μm to about 6μm of gold and/or copper, and the capacitor dielectric 730, such as BCB, are formed on a substrate 720, which may be an insulating or semi-insulating substrate or may be any substrate if the structures are later released. In Figure 7B, a layer of thick metal 750, such as gold and/or copper, then is plated over the structure, hi Figure 7C, the plated layer then may be patterned to form the upper electrode 750a of the capacitor 760 and the coil 750b of the inductor 770. As was already described in connection with Figures 3 and 4, these structures may be formed on a release layer and then bonded to another substrate, for example using flip-chip technology. Same or different size solder bumps may be used. Moreover, the plating and patterning of Figures 7B and 7C may be replaced by a selective plating process, where a plating mask is used to prevent plating in undesired regions. Figure 8 illustrates an air coil RF transformer or mutual inductor according to embodiments of the invention, which may be fabricated by itself and/or with inductors and/or capacitors on a substrate. As shown in Figure 8, a lower coil 840 may be at least partially buried in an insulating or semi-insulating substrate 820, for example by etching trenches in the insulating/semi-insulating substrate 820, forming a thin layer of copper or gold by chemical vapor deposition, and then planarizing if necessary. Alternatively, the lower coil 840 can be formed on a substrate, then surrounded by an insulator such as silicon nitride and then planarized to form a buried lower coil. A layer 830, such as a sacrificial layer for an air gap and/or a dielectric layer for a dielectric gap, then may be formed. An upper coil 850 then may be plated, to provide high Q. The structure of Figure 8 thereby can form an RF transformer, or a mutual inductor, that can be used, for example, to couple RF signals together.

Another variable capacitor sttucture according to embodiments of the invention is illustrated in Figure 9. The lower (first) electrode 940 may be a continuous or patterned buried lower electrode that can be formed as was described for the buried lower coil 840 of Figure 8. A top (second) electrode layer 950 may be a plated bimorph or may be otherwise movable, to thereby allow the electrode spacing to be changed. Spacers 970 also may be included as shown to prevent the electrodes from touching. A sacrificial layer may be formed between the buried lower electrode 940 and the top electrode 950, and then removed to create the air gap 980. Combinations and subcombinations of any and all of the above-described structures and processes also may be provided. Many other variations may be contemplated by those having skill in the art.

In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims

What is Claimed is;

1. A method of fabricating a microelectronic package CHARACTERIZED BY: fabricating at least one reactive component (210) on a first face (220a) of a first substrate (220); placing the first face (220a) of the first substrate (220b) adjacent a second face (320a) of a second substrate (320b), with at least one solder bump (340a-340c) between the at least one reactive component (210) and the second face (320a); and reflowing the at least one solder bump (340a-340c) to join the at least one reactive component (210) to the second substrate (320).

2. A method according to Claim 1 wherein the reflowing is followed by releasing the first substrate (220) from the at least one reactive component (210).

3. A method according to Claims 1 or 2 wherein the fabricating comprises: forming a first capacitor electrode (740) on or in the first face of the first substrate (720); forming a sacrificial layer (730) on the first capacitor electrode (740) opposite the first face; and forming a second capacitor electrode (750a) on the sacrificial layer (730) opposite the first capacitor electrode (740); and wherein the method further comprises removing at least some of the sacrificial layer (730) to provide a variable capacitor (760).

4. A method according to Claim 3 wherein the following is performed simultaneous with the forming a second capacitor electrode (750a) on the sacrificial layer (730) opposite the first capacitor electrode (740): forming an inductor (770) on the first face of the first substrate (720), spaced apart from the first capacitor electrode (740).

5. A method according to Claims 1 or 2 wherein the fabricating comprises: forming a first mutual inductor coil (840) on or in the first face of the first substrate (820); forming a sacrificial layer (830) on the first mutual inductor coil (840) opposite the first face; and forming a second mutual inductor coil (850) on the sacrificial layer (830) opposite the first mutual inductor coil; and wherein the method further comprises removing at least some of the sacrificial layer (830) to provide a variable mutual inductor.

6. A microelectronic package CHARACTERIZED BY: a first substrate (220) having a first face (220a); at least one reactive component (210) on the first face (220a); a second substrate (320) having a second face (320a) that is adjacent the first face (220a); and at least one solder bump (340a-340c) between the at least one reactive component

(210) and the second face (320a) and configured to mechanically and electrically connect the at least one reactive component (210) to the second substrate (320).

7. A package according to Claim 6 wherein the at least one reactive component comprises: a first capacitor electrode (740) on or in the first face of the first substrate (720); and a second, movable, capacitor electrode (750a) facing and spaced apart from the first capacitor electrode (740).

8. A package according to Claim 7 further comprising: an inductor (770) on the first face of the first substrate (720), spaced apart from the first capacitor electrode (740), wherein the second, movable, capacitor electrode (750a) and the inductor (770) comprise portions of a single layer (750).

9. A package according to Claims 6, 7 or 8 wherein the at least one reactive component comprises: a first mutual inductor coil (840) on or in the first face of the first substrate (820); and a second mutual inductor coil (850) facing and spaced apart from the first mutual inductor coil (840).

10. A package according to Claim 6, 7 or 8 wherein the at least one reactive component comprises an inductor (210) having a pair of ends and wherein at least one solder bump comprises: a pair of solder bumps (340a, 340b) between the respective pair of ends and the second face (320a) of the second substrate (320); and a third solder bump (340c) between an intermediate portion of the inductor (210) and the second face (320a) of the second substrate (320).