WO2001097423A1

WO2001097423A1 - Receiving device and receiving method

Info

Publication number: WO2001097423A1
Application number: PCT/JP2001/005060
Authority: WO
Inventors: Tadahisa Kouyama
Original assignee: Sanyo Electric Co., Ltd.
Priority date: 2000-06-15
Filing date: 2001-06-14
Publication date: 2001-12-20
Also published as: EP1296474A1; US20040013218A1; AU2001274521A1; US7443942B2; EP1296474A4

Abstract

A receiving device for CDMA which has a small scale of a circuit including a matched filter and on which the processing load of despreading is lightened. A received signal quadruple-oversampled with respect to the chip rate is downsampled by a speed changing unit (10), so that a matched filter (20) is operated in a double oversampling mode to detect the pass timing. The pass timing detected is fed to a timing adjusting unit (60) of a finger (30) and corrected and used as a demodulation timing on the basis of a differential value calculated by a DLL (40). In this correction, the timing is shifted forward/backward by 1 clock of the quadruple oversampling frequency.

Description

Specification

Technical Field of the Invention

The present invention relates to a CDMA receiver in a direct sequence CDMA (Code Division Multiple Access) communication system. Background art

A CDMA receiver in the direct spread CDMA communication system is provided with a path search device for obtaining despreading timing, and this path search device is provided with a matched-filled or sliding correlator. In the case of matched fill, a delay device, a multiplier, an adder, and the like are provided.

Here, the higher the sampling frequency for the received signal, the more accurately the despread timing (path timing) can be detected. However, if oversampling is performed to increase the sampling frequency, the oversampling of A number of delays corresponding to the multiples are required in the multifill filter.

In order to solve the problem, in the CDMA receiver described in Japanese Patent Application No. 2000-82973, a first circuit section and a second circuit section are provided, and the first circuit section is provided with a low-speed overload. It is configured with a matched filter to input a received signal by sampling, and is used to obtain coarse despread timing. On the other hand, the second circuit unit includes an integrator and a multi-pass filter, and Based on the coarse despreading timing obtained by the circuit section, accurate despreading timing by high-speed over sampling is determined. However, in the CDMA receiver described in JP-A-2000-82973, the process by the second circuit unit is performed after the process by the first circuit unit. There is a problem that it takes time to perform the path search process, and as a result, it takes time to process the entire despreading. Further, although the circuit size of the first circuit unit can be reduced, The circuit section is required, and the overall problem is that the circuit scale cannot be reduced as much.

Therefore, the present invention provides a CDMA receiving apparatus that can reduce the size of a circuit including a multi-filter and reduce the processing load in despreading. It is the purpose. Disclosure of the invention

The present invention has been made to solve the above problems, and firstly, is a receiving device in a CDMA communication system, wherein the receiving device is 1 / n (n is an integer) of a sampling frequency of a received signal. A matched filter that operates at the frequency of the received signal, a matched filter that detects the path timing, and a finger that despreads the received signal, and a DLL that operates at the sampling frequency of the received signal. A DLL that calculates a difference value that is a value indicating a difference between a demodulation timing specified by the path timing detected by the matched filter and the received signal, and a path timing detected by the matched filter based on the DLL. A timing adjustment unit for outputting a timing signal having a predetermined period, wherein the position of the timing signal is determined based on the difference value calculated by the DLL. JP that has a timing adjustment unit that corrects the Fi Nga portion having a despreading unit, a performing despreading demodulation timing defined by the timing signal from 該夕 timing adjustment unit, the a To sign.

In the receiving device having the first configuration, the matched filter operates at a frequency that is 1 / n (n is an integer) of the sampling frequency of the received signal, and detects the path timing. Then, DLL in the finger section calculates a difference value that is a value indicating a difference between the demodulation timing and the received signal. The timing adjustment unit outputs a timing signal having a predetermined cycle based on the path timing detected by the multi-fill filter. The timing adjustment unit adjusts the phase of the timing signal based on the difference value. to correct. In other words, the timing adjustment unit determines whether to advance or delay the phase of the timing signal in a predetermined case, for example, when the absolute value of the difference value is larger than the predetermined threshold. In other words, if the demodulation timing is delayed with respect to the received signal, the phase is advanced, while if the demodulation timing is advanced with respect to the received signal, the phase is delayed. The despreading unit performs despreading at the demodulation timing specified by the evening adjustment unit. Therefore, according to the receiving device of the first configuration, the multi-filter is operated at a frequency that is 1 / n (n is an integer) of the sampling frequency of the received signal, so that the circuit size of the multi-filter is reduced. can do. In addition, since the demodulation timing roughly grasped by the matched filter is corrected based on the information from the DLL, the circuit size and processing load in the receiver are reduced by using the DLL originally provided in the CDMA receiver. It can be kept from growing. In addition, since the correlation peak position can be detected with the accuracy of the sampling frequency, a good S Z

Demodulation can be performed at the N ratio.

Secondly, in the first configuration, the timing adjustment unit according to a comparison result between the difference value calculated by the DLL and a predetermined threshold value, determines the timing signal in a predetermined case. Characterized by correcting the phase You. That is, for example, when the magnitude of the difference value is larger than a predetermined threshold value, the correction is performed.

Thirdly, in the first or second configuration, the magnitude of the difference value calculated by the DLL exceeds a predetermined threshold value, and the difference value is a demodulation time. If the timing indicates that the timing is behind the received signal, the timing adjustment unit advances the phase of the timing signal, while the magnitude of the difference value calculated by the DLL is If the difference exceeds a predetermined threshold value and the difference value indicates that the demodulation timing is advanced with respect to the received signal, the timing adjustment unit delays the phase of the timing signal It is characterized by the following. In this way, the phase of the evening timing signal can be corrected.

Fourth, in the first or second configuration, when the difference value calculated by the DLL is a positive value, the difference value exceeds a predetermined threshold value. In addition, the timing adjustment unit advances the phase of the timing signal. On the other hand, when the difference value calculated by the DLL is a negative value, the difference value sets the predetermined threshold value to a negative value. When the value is smaller than a second threshold value, the timing adjustment unit delays the phase of the evening imaging signal.

Fifth, in the first, second, third, or fourth configuration, the timing adjustment unit corrects the phase of the timing signal by using one or more ports at the sampling frequency of the received signal. It is characterized in that the phase is advanced or delayed by the amount of the clock.

Sixth, in the first, second, third, fourth, or fifth configuration, the timing adjustment unit is configured to execute the timing adjustment when a predetermined period elapses from the path timing detected by the matched fill. Output first, and thereafter, based on the difference value calculated by the above DLL, The phase of the evening signal is corrected.

Seventh, in the first or second or third or fourth or fifth or sixth configuration, the DLL may be configured to generate a spread code based on a timing signal output from the timing adjustment unit. And a third generator that outputs a spread code delayed from the output timing of the first generator by a delay period that is a period of two chips or less, and The spreader has a second generator that outputs a spread code with a delay of half the delay period from the output timing of the first generator.

Eighthly, in the first, second, third, fourth, fifth, sixth, or seventh configuration, the receiving apparatus further comprises: It is characterized by having a conversion unit that downsamples to a frequency of 1 / n of the frequency (n is an integer) and outputs the downsampled received signal to the matched filter. As a result, a down-sampled received signal can be sent to the multi-filler.

A ninth is a reception method in a CDMA communication system, which includes a path timing detection step of detecting a path timing by a matched filter operating at a frequency of 1 / n (n is an integer) of a sampling frequency of a reception signal. A differential value calculating step of calculating a differential value indicating a difference between the demodulation timing defined by the path timing detected in the above-described path timing detecting step and the received signal by a DLL operating at the sampling frequency of the received signal. A timing signal output step of outputting a timing signal having a predetermined cycle based on the path timing detected in the path timing detection step; and a difference value calculated in the difference value calculation step. A correction step for correcting the phase of the timing signal output in the timing signal output step; Characterized in that it has. Therefore, according to the reception method of the ninth configuration, the matched filter is operated at a frequency that is 1 / n (n is an integer) of the sampling frequency of the received signal. Can be reduced. In addition, since the demodulation timing roughly grasped by the matched filter is corrected based on the information from the DLL, the circuit size and processing load in the receiver are reduced by using the DLL originally provided in the CDMA receiver. It can be kept from growing. Also, since the correlation peak position can be detected with the accuracy of the sampling frequency, the demodulation processing can be performed with a good S / N ratio.

According to a tenth aspect, in the ninth configuration, in the correction step, the timing is determined in a predetermined case according to a comparison result between the difference value calculated in the difference value calculation step and a predetermined threshold value. It is characterized in that the phase of the mining signal is corrected. That is, for example, when the magnitude of the difference value is larger than a predetermined threshold value, the correction is performed.

Also, 11thly, in the ninth or 10th configuration, the magnitude of the difference value calculated in the difference value calculation step exceeds a predetermined threshold value, and Indicates that the demodulation timing is delayed with respect to the received signal, the timing signal is advanced in the correction step, and the magnitude of the difference value calculated in the difference value calculation step is When the difference exceeds a predetermined threshold value and the difference value indicates that the demodulation timing is advanced with respect to the received signal, the timing signal is delayed in the correction step. And

In a twelfth aspect, in the ninth or tenth configuration, when the difference value calculated in the difference value calculating step is a positive value, the difference value exceeds a predetermined threshold value. In the correction step, the phase of the timing signal is advanced in the correction step, while the phase is calculated in the difference value calculation step. In the case where the output difference value is a negative value, if the difference value is smaller than a second threshold value in which the predetermined threshold value is set to a negative value, the timing in the correction step It is characterized in that the phase of the signal is delayed. In the thirteenth aspect, in the ninth, tenth, tenth, or eleventh configuration, when correcting the phase of the timing signal in the correction step, the sampling frequency of the reception signal may be reduced. The phase is advanced or delayed by one or more clocks.

Fourteenth, in the ninth or tenth or eleventh or twelve or thirteenth configuration, when a predetermined period elapses from the path timing detected in the path timing detection step, In the timing signal output step, the timing signal is output first, and thereafter, the phase of the timing signal is corrected in the correction step based on the difference value calculated in the difference value calculation step. It is characterized by doing. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing a configuration of a receiving apparatus based on an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a multi-pass filter, and FIG. 3 is a detailed configuration of a finger. FIG. 4 is a block diagram showing a configuration of a spreading code generator. FIG. 5 is an explanatory diagram showing an operation of a receiving apparatus according to an embodiment of the present invention. FIG. 7 is an explanatory diagram showing the operation of the receiving device based on the embodiment of the present invention. FIG. 7 is an explanatory diagram showing the operation of the receiving device based on the embodiment of the present invention. FIG. FIG. 9 is an explanatory diagram showing the operation of the receiving device based on the embodiment of the invention, and FIG. 9 is an explanatory diagram showing the operation of the receiving device based on the embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. As shown in FIG. 1, receiving apparatus A based on the present invention includes a speed conversion unit (conversion unit) 10, a multi-pass filter 20, a finger (finger unit) 30, and a RAKE synthesis unit. 90 and a control unit 100.

Here, the speed conversion unit 10 is a circuit that performs down-sampling on the received signal. For example, the speed conversion unit 10 performs over-sampling on the received signal input to the chip plate by 4 times over 1 sampling. To the received signal. That is, the received signal input to the receiving apparatus A is a digital signal obtained by performing a four-fold oversampling on the received received signal. Then, the speed conversion unit 10 performs a thinning process or the like on the input received signal to obtain a received signal of double oversampling. The speed conversion unit may be expressed as “speed conversion means” or “speed conversion device”.

The matched filter 20 calculates the correlation value between the received signal and the spreading code, and outputs a path timing signal indicating the timing (path timing) of the peak position, as shown in FIG. The delay unit 2 1—1 to 2 1—n and the multiplier 2 2— :! ~ 2 2 -n, an adder 23, a memory 24, and a control unit 25. Received signals from the speed converter 10 are sequentially input to the delay units 21-1 to 21-n. A fixed spreading code is input to multipliers 22-1 to 22-n, and a delay unit 21-1 ;! Multiplication is performed on the received signal from 〜2 1-n. The adder 23 adds the multiplication results of the multipliers 22-1 to 22-ri. Then, the addition result from the adder 23 is stored in the memory 24. That is, the addition result for one symbol is stored in the memory 24. The control unit 25 detects the timing of the beak position based on the addition result stored in the memory 24, and outputs a path timing signal indicating the timing. This pass evening The signaling signal is basically output for each symbol, but may be output for a plurality of symbols.

This path timing signal is a signal indicating the time information of the peak position, and strictly speaking, is data of the time from when the matched filter 20 started operating (this is referred to as “relative time”). That is, the control unit 25 detects the peak position based on the data stored in the memory 24, calculates the relative time for the peak position, and transmits the relative time data. It is output as a timing signal.

In the present embodiment, since the received signal of double over sampling is input from the speed conversion unit 10, the matched filter 20 is a multi-filter of the double over sampling operation.

Note that the detected peak position includes the sub-vis. That is, the timing is detected for a plurality of paths in consideration of the reflected wave and the like, and the path timing signal for each timing is output.

In the above description, the pass filtering signal output from the matched filter 20 is time data for the peak position. However, the multifilter 20 converts the correlation value data for each time to the pass timing. The signal may be directly output to the control unit 100 as a signal. In other words, the multi-fill filter 20 outputs the correlation value de-corresponding to the double over-sampling timing to the control unit 100 as it is. In other words, as shown in FIGS. 5 (a :) and (b), the matched filter 20 calculates the correlation value at every two-fold over one sampling period, and transmits the data of the correlation value to the control unit 10. Output to 0. For example, taking FIG. 5 (b) as an example, the correlation value data is output every 1/2 chip. That is, in this case, the double oversampling period corresponds to 12 chips. In this case, In this case, a signal having a waveform as shown in FIG. 5 (a) is output from the multi-fill filter 20. Strictly speaking, as described above, every two-over sampling period Will be output. FIG. 5 (b) is an enlarged view of the beak position.

Note that the multi-pass filter 20 outputs the time data for the peak position (this is referred to as a “first method”), and the multi-pass filter 20 outputs the correlation value as it is (this Is referred to as the “second method”). However, the first method and the second method can be selectively used when one peak is detected in one symbol. When the first method is used, and when a plurality of peaks are detected in one symbol, the second method is used.

It is possible to use the second method.

Note that, as described above, the case where the matched filter 20 outputs a signal indicating the time delay of the beak position as a path timing signal is as follows. For example, the peak of the beak position PK in FIG. When outputting the time information of the position, the time data for Ta shown in Fig. 5 (b) will be output.

The finger 30 performs despreading for each path in the received signal, and a plurality of fingers 30 are provided so as to correspond to each path. Each finger 30 has a DLL (Delay Locked Loop) 40, a timing adjustment unit 60, and a despreading unit 80.

The DLL 40 calculates a difference value between the correlator output of the received signal and the correlator with E (E arl) one code of the spread code and the correlator output of L (Late) with one code. Is output. That is, this DLL 40 has multipliers 42 a and 42 b, detectors 44 a and 44 b, a subtractor 48, and a loop filter 50 shown in FIG. . Here, inspection Waveformer 44a integrates the signal from multiplier 42a and outputs a correlation output to subtractor 48 for each symbol period. The detector 44b integrates the signals from the multiplier 42b and outputs a correlation output to the subtractor 48 for each symbol period.

The spreading code generator 70 in FIG. 3 has a first generator 72, a second generator 74, and a third generator 76 as shown in FIG. The first generator 72 outputs a spreading code to the multiplier 42a, and the third generator 76 outputs a spreading code to the multiplier 42b. The 3 generator 76 also has the configuration in the DLL 40 described above. That is, the first generator 72 outputs a spread code as E-code, while the third generator 76 outputs a spread code as L-code. Further, the second generator 74 has a configuration of a despreading unit 80.

Note that the first generator 72, the second generator 74, and the third generator 76 output the spread code with a delay of the order of a half chip. That is, as shown in FIG. 7, at the time when the H 0 LD signal (described later) from the evening timing adjustment unit 60 becomes Low, that is, at the Low timing, the signal is spread from the second generator 74. A code is output (see Fig. 7 (b)), and a spreading code is output from the first generator 72 at a phase advanced by half a chip from the Low timing (Fig. 7 (a)). The spreading code is output from the third generator 76 at a phase delayed by half a chip from the Low timing (see FIG. 7 (c)). Here, the third generator 76 outputs the spread code with a delay of one chip period from the output timing of the first generator 72. In this case, the one chip period is the delay in the claims. Hit time.

Next, the timing adjustment unit 60 outputs a HOLD signal. This HO LD signal is a signal having the frequency of the chip plate as shown in FIGS. 6 (a) and 6 (b), and becomes Low at the cycle of the frequency. F in Fig. 6 s indicates the sampling frequency of the chip plate. Also, this HOLD signal is a signal in which each circuit (each part in the finger 30 or the RAKE combining unit 90, etc.) becomes operable at the timing when this signal becomes Low.

The timing at which the H 0 LD signal becomes Low is basically L 0 w for each cycle of the chip plate frequency, but is sent from the matched filter 20 via the control unit 100. According to the path timing signal and the difference value from the DLL 40, the phase of the Low timing is corrected in a predetermined case.

That is, when the difference value sent from the DLL 40 indicates the advanced phase, and the value exceeds a predetermined threshold value, the timing adjustment unit 60 outputs the timing signal from the matched filter 20. Is performed, the difference value sent from DLL 40 indicates the delay phase, and if the difference value exceeds a predetermined threshold value, the timing adjustment unit Numeral 60 controls the advance of the timing indicated by the path timing signal from the matched filter 20. As described above, when the difference value exceeds a predetermined threshold value, the phase is corrected. The period of delay or advance of the phase is the period of one clock. Here, one clock is one clock in the operation clock in which the finger 30 operates, that is, here, the one clock is based on the sampling frequency in four times over one sampling.

As described above, the HOLD signal basically becomes Low at a predetermined cycle. However, this HOLD signal, particularly, the signal of the Low timing is referred to as “based on path timing” in the claims. At a predetermined period. " In other words, “Matched Fill This corresponds to the “evening timing signal” in the “evening timing adjustment unit that outputs a timing signal of a predetermined cycle based on the path timing detected by the above. The evening timing adjustment unit may be expressed as “evening timing adjustment means” or “evening timing adjustment device”.

Next, the despreading section 80 performs despreading processing on the received signal. The despreading section 80 is connected to the second generator 74 shown in FIGS. 3 and 4. , A multiplier 82 and a detector 84. The despreading unit 80 performs despreading by demodulation timing (despreading timing) based on the H0LD signal from the timing adjustment unit 60. Details will be described later. Note that this despreading unit may be expressed as “despreading means” or “despreading device”.

Next, the: RAKE synthesizing section 90 is a circuit for performing processing for synthesizing the received signal despread in each finger 30. In other words, it performs processing such as compensating the amount of phase rotation for each path to make the signals of each path in-phase, and combining the signals of each path corrected to have the same phase. The finger 30 and the RAKE combining section 90 perform demodulation processing on the received signal.

Further, the control section 100 controls the operation of each section in the receiving apparatus A. In particular, when a pass timing signal is sent from the matched filter 20, the control unit 100 has a function of converting the relative time data indicated by the pass timing signal into absolute time data. Have. Here, the absolute time is a local time held in the receiving device A itself, a time (time) indicated by a local clock provided in the receiving device A, and is a reference for the receiving device A. Time. The control unit 100 expresses the evening at the peak position in absolute time, and then sends it to the timing adjustment unit 60.

When the matched filter 20 sends the correlation value data to the control unit 100 as it is, the control unit 100 The relative time is calculated. Further, the absolute time is calculated from the relative time, and information on the calculated absolute time is sent to the timing adjustment unit 60. In other words, the control unit 100 stores a program for calculating the relative time based on the transmitted relative value data and calculating the absolute time from the relative time. Therefore, the control unit 100 performs an operation according to the program. Note that the control unit 100 may calculate the absolute time directly from the correlation value data transmitted from the multi-fill filter 20.

In FIG. 1, each part surrounded by a region P, that is, the finger 30, the RAKE combining unit 90, and the speed converting unit 10 perform a four-fold over sampling operation. The matched filter 20 surrounded by Q is a double over-one sampling operation. That is, the operation of each unit surrounded by the region P is a four-fold over sampling operation, and the operation of the matched fill 20 surrounded by the region Q is a two-fold over sampling operation.

The operation of the receiving apparatus A having the above configuration, in particular, a receiving method in the CDMA communication system by the receiving apparatus A will be described. The content described below is about the path search in the receiving operation, that is, the initial synchronization acquisition.

First, it is assumed that a reception signal is input to the reception device A. The received signal is sampled at oversampling four times the chip rate, and is a received signal that has been subjected to AD conversion processing.

Then, the speed conversion section 10 performs downsampling and converts the received signal into a double-oversampling received signal. The received signal of this 2 × over sampling is sent to the matched filter 20, and the multi-filter 20 detects the peak position, and detects the timing signal for each path, That is, a pass timing signal is output. The path timing signal is sent to the control unit 100, and the control unit 100 sends the path timing signal to the evening timing adjustment unit 60 in the finger 30. The step of detecting the peak position in the matrix filter 20 corresponds to the path timing detecting step in the claims.

Here, strictly speaking, the data of the relative time indicating the peak position is sent from the matched filter 20 to the control unit 100 as a pass evening timing signal, and the control unit 100 outputs the relative time. The path timing signal shown is converted to an absolute time and then sent to the evening adjustment unit 60. Note that the signal sent to the timing adjustment unit 60 is still a signal indicating the timing of the peak position.

When the correlation value data is sent from the matched filter 20 to the control unit 100, the control unit 100 calculates the absolute time indicating the peak position based on the correlation value data. The calculated absolute time is output to the evening adjustment unit 60 as a path timing signal.

The evening adjustment section 60 outputs a HOLD signal based on the pass evening signal. That is, in the clock cycle of the four times oversampling frequency (see FIG. 6 (a)), the HOLD signal is set to Low at the timing of time T with respect to the time indicated by the path timing signal (see FIG. 6) . Thereafter, the HOLD signal becomes LOW for each chip unless otherwise described later.

Here, the timing when the HOLD signal first becomes Low is the timing indicated by the time indicated by the path timing signal, that is, the time indicated by the time indicating the peak position. That is, the H〇LD signal is set to Low at a timing one cycle after the absolute time. This “one cycle” period can be set arbitrarily. For example, one frame (= 150 symbols) , N symbols (n is an integer of 1 or more), or n types (n is an integer of 1 or more). That is, for example, if one cycle is one frame, the HOLD signal becomes Low after a period of one frame from the absolute time. The HO LD signal may be set to L 0 w at the timing closest to the time indicated by the path timing signal.

Note that the timing when the H0LD signal first becomes L0w is the same as the start timing of the DLL 40. In other words, the start timing is also set one cycle after the absolute time, and the H 0 LD signal becomes Low at the same time as the start. In this way, at the first stage of the initial synchronization acquisition, the HOLD signal is set to Low based on the absolute time. In other words, the time indicated by the path timing signal from the matched filter 20 indicates the time (or time) at the peak position, whereas Ta in FIG. The timing when the signal becomes Low becomes Tb after a predetermined time (ie, the above-described one cycle) from the Ta. Here, it can be said that T in FIG. 6 strictly indicates this Tb.

The received signal of 4 times oversampling is also sent to DLL 40 at the same time. In this DLL 40, the difference value is calculated by the multipliers 42a and 42b, the detectors 44a and 44b, and the subtractor 48. Is done. That is, the correlation output between the received signal and the E-code is output from the detector 44a to the subtractor 48, while the correlation output between the received signal and the L-c0 de is calculated from the detector 44b and the subtractor 48. And the subtractor 48 performs a subtraction process to calculate a difference value. That is, the subtractor 48 performs a process of subtracting the output of the detector 44b from the output of the detector 44a. This difference value indicates a value indicating the difference between the demodulation time and the received signal, and is basically calculated for each symbol. The calculated difference value is The signal is sent to the evening adjustment unit 60 via the event controller 50. The step of calculating the difference value as described above corresponds to a difference value calculating step in the claims. In the multiplication processing in multipliers 42a and 42b, the first generator 72 of the spreading code generator 70 is connected to the multiplier 42a, and the third generator 76 is connected to the multiplier 4 2b, the spreading code is output. At the stage of initial acquisition, that is, at the stage of time T shown in FIG. 6, as described above, the time T indicated by the timing signal from the Since the HOLD signal is set to Low from the timing adjustment section 60 based on the timing based on Ta (see FIG. 5), the spread code is output according to the L0w timing. Will be.

The timing adjustment unit 60 compares the value of the difference value sent from the DLL 40 with a predetermined threshold value, and determines whether or not the value exceeds the threshold value. Since the difference value may be positive or negative, strictly speaking, the magnitude of the difference value, that is, the absolute value of the difference value is compared with the threshold value. For example, if the difference value is X and the threshold value is S (S is a positive value), it is determined whether IXI> S. That is, the evening timing adjustment unit 60 determines whether or not the magnitude of the difference value exceeds a predetermined threshold value, that is, whether or not the magnitude of the difference value is greater than the predetermined threshold value. The determination determines whether to correct the phase of the H 0 L signal. When the difference value exceeds the threshold value, the timing adjustment section 60 outputs a HOLD signal so as to correct the Low timing. In other words, when the difference value is positive, that is, when the operation clock has a delayed phase with respect to the received signal, the timing of setting the HOLD signal to Low is advanced by one clock (see FIG. 6 (d)). On the other hand, if the phase difference value is negative, that is, if the operating clock is ahead of the received signal and is in phase, the timing when the HOLD signal is set to Low is delayed by one clock. (See Fig. 6 (c)). Thus, the step of correcting the low timing in the HOLD signal corresponds to the correction step in the claims.

For example, as shown in Fig. 8 (a), when the value indicated by the symbol in Fig. 8 (a) is sampled by double over sampling with respect to the waveform of the correlation value, " The timing T1 shown in the “detection peak position” is the evening of the peak position detected by the matched filter 20. Thus, when demodulation is performed with the timing T1 as the demodulation timing, as shown in FIG. 8 (b), the timing T2 becomes the advanced arm position, and the timing T3 becomes the delayed arm position.

In the example shown in FIG. 8, since the operation clock is delayed with respect to the received signal, the above difference value is positive. The timing to set Low is advanced by one clock. As a result, the demodulation timing becomes the timing T4 as shown in FIG. 8 (c), and the timing closer to the peak position can be set as the demodulation timing. The example in Fig. 8 corresponds to Fig. 6 (d).

On the other hand, as shown in Fig. 9 (a), when the value indicated by the symbol in Fig. 9 (a) is sampled by double oversampling with respect to the waveform of the correlation value, the "detection" The timing T11 shown in the “peak position” is the timing of the peak position detected by the matched filter 20. Therefore, when the timing T11 is demodulated as the demodulation timing, as shown in FIG. 9 (b), the evening T12 becomes the advanced arm position, and the timing T13 becomes the delayed arm position. .

In the example of FIG. 9, since the operation clock is in a leading phase with respect to the received signal, the difference value becomes negative and exceeds the threshold value. In this case, the timing at which the H 0 LD signal is set to Low is delayed by one clock. As a result, the demodulation timing becomes the timing T14 as shown in FIG. 9 (c), and the timing closer to the peak position can be set as the demodulation timing. The example in FIG. 9 corresponds to FIG. 6 (c).

As shown in FIG. 6, the timing for actually correcting the L 0 w timing is n symbols (n is the time from the time T based on the time of the path timing detected by the maximum fill time 20). (Integer greater than or equal to 2) In other words, as shown in Fig. 6, the timing of Low timing correction is n symbols (n is an integer of 2 or more) from the timing of time T, that is, the timing when the HOLD signal is initially set to Low. Later timing. That is, a difference value obtained by averaging the difference value calculated for each symbol by n symbols is compared with a threshold value to determine whether to shift the phase of the Low timing. That is, it is determined whether or not to correct the phase of the HOLD signal at a timing n symbols after the time T.

However, the difference value for one symbol is calculated one symbol after the time (see Fig. 6), so it is possible to correct the low timing at this point.

It should be noted that the threshold value used in the timing adjustment section 60 should be such that shifting the timing of the Low of the H 0 LD signal results in a timing closer to the peak position. Will be set. In addition, the substantially mountain-shaped line in FIGS. 8 and 9 is an enlarged view of the peak position of the correlation value of the received signal.

As described above, the phase correction method of the timing signal in the CDMA communication system is performed. Since the H 0 LD signal is output from the timing adjustment section 60 with the Low timing corrected, the spreading code is multiplied by the spreading code generator 70 based on the corrected Low timing. These are output to the multiplier 42a, the multiplier 82, and the multiplier 42b, respectively.

Then, in the DLL 40, multiplication of the received signal by the input spread code and the like are performed in the same manner as described above.

In the despreading unit 80, a multiplier 82 multiplies the received signal by a spreading code from the second generator 74, and the despread signal is processed through a process in a detector 84. Output from detector 84.

Here, when the Low timing of the H 0 LD signal is corrected, the demodulation timing based on the corrected timing (the timing T 4 in the example of FIG. 6 (d) and FIG. 8). In the examples of FIGS. 6 (c) and 9, the despreading process is performed in the evening T14). In other words, if the Low timing of the HOLD signal is shifted by the correction, the spreading code is output to the despreading unit 80 at the Low timing, and the multiplication in the multiplier 82 is performed at that timing. Processing is performed. In other words, the corrected Low timing is the corrected demodulation timing.

The despread signal output from the despreading unit 80 is sent to a RAKE combining unit 90, and in the RAKE combining unit 90, the despread signal, that is, the received signal that has been despread A process for combining is performed. The RAKE-combined received signal is output to the outside via the control unit 100. Of course, when the phase of the H 0 LD signal is corrected, the HO LD signal has a predetermined period, that is, a period of the chip frequency, until the next correction is performed. Low.

The correction after the correction of the low timing in the HO LD signal is performed, for example, by using the same clock phase as described above for each of a plurality of symbols. May be corrected. That is, an opportunity to correct the phase may be provided for each of a plurality of symbols, and it may be determined whether or not to correct the phase for each of the plurality of symbols. Also, a phase correction opportunity may be provided for each symbol.

In the above description, the operation in the initial synchronization acquisition has been described as an example.However, the opportunity for correcting the phase of the HOLD signal as described above is not limited to the initial synchronization acquisition stage, and may be provided after that. become.

As described above, according to the receiving apparatus A of the present embodiment, rough pass evening is detected by using the multiplied filter operated with a low oversampling number, and synchronization acquisition with a high oversampling number is performed.保持 For holding, the DLL originally provided for the demodulation finger is used, so the circuit size of the matched filter can be reduced, and the circuit size of the receiving device as a whole can be reduced. . Further, according to the receiving apparatus A of the present embodiment, the processing performed by the second circuit unit in the CDMA receiver disclosed in JP-A-2000-82973 can be omitted, and the processing load can be reduced. Can help. Further, according to the receiving apparatus A of the present embodiment, as a result, the peak position can be detected with the accuracy of the sampling frequency of the received signal, that is, the accuracy of 4 times over sampling, so that the SZN ratio can be improved. Demodulation processing can be performed.

In the above description, as shown in FIGS. 6 (c;) and (d), n symbols (n is 2 or more) from the time T with reference to the pasting detected at the matrix fill 20. In the following timing, the low timing of the H 0 LD signal is described as being corrected. However, the present invention is not limited to this. The low timing is corrected at a certain timing in a certain symbol. You may. That is, for example, up to n-1 symbols (n is an integer of 3 or more)! ) The average value of the difference value of LL40 is compared with a predetermined threshold value to judge. When the low timing is advanced or delayed, the correction is performed in the middle of the n-th symbol. Therefore, when the Low timing is corrected, despreading is performed from the (n + 1) th symbol at the demodulation timing based on the corrected Low timing. In the above description, the correction of the Low timing of the HOLD signal is described as being advanced or delayed by one clock, but is not limited thereto, and may be advanced or delayed by more than one clock. You may do it.

Also, in the above description, the first generator 72, the second generator 74, and the third generator 76 in the spreading code generator 70 are spread with a delay of a half chip period. It has been described that the code is output, that is, the time between the output timing of the first generator 72 and the output timing of the third generator 76 is one chip. The time between the output timing of 2 and the output timing of the third generator 76 is set to a time t of 2 chips or less, and the output timing of the second generator 74 is determined by the output of the first generator 72. The timing may be delayed by half the time t / 2 from the timing. This time t corresponds to the delay time in the claims.

Also, in the above description, the matched filter 20 is described as performing a two-fold oversampling operation, and the fingers 30 and the like are performed as a four-fold oversampling. However, the present invention is not limited to this. In the case of double-over-one sampling operation, finger 30 etc. are 8 times over-sampled, matched filter 20 is 2 times over-one sampling operation, and finger 30 etc. is 16 times over-one sampling operation. If the matched filter is operated at a frequency that is 1 / n (n is an integer of 2 or more) of the sampling frequency of the received signal, such as in the case of sampling, other modes can be considered.

In the above description, the magnitude of the difference value is compared with a predetermined threshold, When the magnitude of the difference value exceeds the threshold value, the phase of the HOLD signal is corrected, but the threshold value when the difference value is positive and the threshold value when the difference value is negative are described. May be provided, and the difference value itself may be compared with the threshold value. In other words, if the threshold value for a positive difference value is S, the threshold value for a negative difference value is —S, and if the differential value is positive, the difference value exceeds S. If so, make corrections. In other words, when the difference value is X, correction is performed when s <x. On the other hand, when the difference value is negative, the correction is performed when the difference value is smaller than 1S. In other words, when the difference value is a negative value X, correction is performed in the case of X-S. In this case, the method is also the same as the method of comparing the magnitude of the difference value with a predetermined threshold value and correcting the difference value when the difference value exceeds the threshold value. It can be said that there is. Industrial applicability

As described above, according to the receiving apparatus of the present invention, at the time of CDMA reception processing, the matched filter is operated at a frequency of 1 / n (ri is an integer) of the sampling frequency of the received signal. The circuit size of the matched filter can be reduced. In addition, since the demodulation timing roughly grasped by the matched filter is corrected based on the signal from the DLL, the DLL provided in the CDMA receiver is used originally, so the circuit scale and processing load in the receiver are used. Can be prevented from becoming large.

Claims

The scope of the claims

1. A receiving device in the CDMA communication system,

A multi-fill filter operating at a frequency that is 1 / n (n is an integer) of the sampling frequency of the received signal, wherein a multi-filter filter detects path timing;

A finger unit for performing despreading on the received signal,

A DLL that operates at the sampling frequency of the received signal and calculates a difference value that is a value indicating a deviation between the demodulation timing defined by the path timing detected by the matched filter and the received signal; and a matched filter. A timing adjustment unit that outputs a timing signal having a predetermined cycle based on the path timing detected by the DLL, and that adjusts the phase of the evening timing signal based on the difference value calculated by the DLL. Department and

A despreading unit that performs despreading at a demodulation timing specified by a timing signal from the evening adjustment unit;

A receiving device comprising:

2. The timing adjustment section corrects the phase of the timing signal in a predetermined case according to a comparison result between the difference value calculated by the DLL and a predetermined threshold value. The receiving device according to item 1.

3. If the magnitude of the difference value calculated by the DLL exceeds a predetermined threshold value and the difference value indicates that the demodulation timing is behind the received signal, The timing adjustment section advances the phase of the timing signal,

On the other hand, the magnitude of the difference value calculated by the DLL is a predetermined threshold. If the difference exceeds the value and the difference value indicates that the demodulation timing is advanced with respect to the received signal, the timing adjustment unit delays the phase of the timing signal. The receiving device according to claim 1 or 2, wherein

4. When the difference value calculated by the DLL is a positive value, the timing adjustment unit advances the phase of the evening timing signal when the difference value exceeds a predetermined threshold value. Not

On the other hand, when the difference value calculated by the DLL is a negative value, when the difference value is smaller than a second threshold value in which the predetermined threshold value is a negative value, The receiving device according to claim 1 or 2, wherein the timing adjustment unit delays the phase of the timing signal.

5. The timing adjustment unit according to claim 1, wherein, in correcting the phase of the timing signal, the phase is advanced or delayed by one or more clocks in the sampling frequency of the received signal. Or the receiving device according to paragraph 2 or 3 or 4.

6. The timing adjustment unit outputs the timing signal first when a predetermined period has passed from the path timing detected by the matched fill, and thereafter, based on the difference value calculated by the DLL, 6. The receiving apparatus according to claim 1, wherein the phase of the timing signal is corrected.

7. The DLL includes a first generator that outputs a spread code based on the timing signal output from the timing adjustment unit, and an output of the first generator. A third generator that outputs a spreading code delayed by a delay period that is a period of two chips or less from the timing, and the despreading unit is configured to output the spreading code from the output timing of the first generator. And a second generator that outputs a spread code delayed by a half of the delay period. 2. The method according to claim 1, further comprising: Item 7. The receiving device according to item 6 or 6.

8. The receiving apparatus further down-samples the received signal to a frequency that is 1 / n (n is an integer) of the sampling frequency of the received signal, and outputs the down-sampled received signal to the matched filter. 8. The receiving device according to claim 1, further comprising a conversion unit that outputs the signal.

9. The receiving method in the CDMA communication method,

A path timing detection step of detecting a path timing by a matched filter operating at a frequency 1 / n (n is an integer) of the sampling frequency of the received signal;

A difference value calculating step of calculating, by a DLL operating at the sampling frequency of the received signal, a difference value which is a value indicating a deviation between the demodulated timing specified by the path timing detected in the above-described path timing detecting step and the received signal. When,

A timing signal output step of outputting a timing signal having a predetermined period based on the path timing detected in the path timing detection step; and the timing based on the difference value calculated in the difference value calculation step. A correction step for correcting the phase of the timing signal output in the signal output step;

A receiving method, comprising:

10. In the correcting step, the phase of the timing signal is corrected in a predetermined case according to a result of comparison between the difference value calculated in the difference value calculating step and a predetermined threshold value. 10. The receiving method according to claim 9.

11. The magnitude of the difference value calculated in the difference value calculation step exceeds a predetermined threshold value, and the difference value indicates that the demodulation timing is delayed with respect to the received signal. If there is, in the above-mentioned correction process, advance the evening

On the other hand, it is determined that the magnitude of the difference value calculated in the above difference value calculation step exceeds a predetermined threshold value, and that the difference value indicates that the demodulation timing is advanced with respect to the received signal. 11. The receiving method according to claim 9, wherein the timing signal is delayed in the correction step in the case where it is indicated.

12. When the difference value calculated in the difference value calculation step is a positive value, if the difference value exceeds a predetermined threshold value, the timing is calculated in the correction step. Advance the phase of the signal,

On the other hand, when the difference value calculated in the difference value calculation step is a negative value, when the difference value is smaller than a second threshold value in which the predetermined threshold value is a negative value, 10. The receiving method according to claim 9 or 10, wherein a phase of said timing signal is delayed in said correcting step.

13.When correcting the phase of the timing signal in the correction step, 13. The receiving method according to claim 9, wherein the phase is advanced or delayed by one or more clocks at the sampling frequency of the received signal. .

14. When a predetermined period has elapsed from the path timing detected in the path timing detection step, the timing signal is output first in the timing signal output step, and thereafter, in the difference value calculation step. The phase of the timing signal is corrected in the correction step based on the calculated difference value, wherein the phase of the timing signal is corrected. The receiving method according to paragraph 13.