KR100731260B1 - Tracker for Mobile Broadcasting Receiver - Google Patents

Abstract

The present invention relates to a tracker in a mobile broadcast receiver for a fully digital form, wherein the tracker in a mobile broadcast receiver according to the present invention is an example of a tracker in a mobile broadcast receiver for synchronizing a digitized received signal. A first digital resampler for pre-processing the signal; A digital resampler for compensating the digital signal, including a second digital resampler for post-signaling the output signal of the first digital resampler and the output signal of the NCO; A DLL for estimating timing error using the correlation characteristic of the PN code from the compensated digital signal; A loop filter for receiving and accumulating the estimated timing error signal; And an NCO generating an interpolation position information value corresponding to the cumulatively corrected timing error signal.

Therefore, according to the present invention, by eliminating the selector used in the conventional tracker system and adopting the digital resampler, not only much more accurate pager offset correction but also correction of the frequency offset is possible.

Tracker, Digital Resampler, Offset, Masking, Chip Off

Description

Tracker for Mobile Broadcasting Receiver

1 is a view for explaining a tracker (tracker) of a mobile broadcast receiver employing a conventional DLL.

2 is a view for explaining a first embodiment of a tracker in the mobile broadcast receiver according to the present invention.

3 is a diagram for explaining an operation of a general digital resampler.

FIG. 4 is a diagram for explaining a digital resampler to which a narrow filter structure is applied.

FIG. 5 is a diagram for explaining the principle of operation of a digital resampler when a negative fractional delay is applied. FIG.

6 is a view for explaining a digital resampler according to the present invention.

7 is a view for explaining the DLL of FIG.

FIG. 8 is a diagram for describing the data sorter of FIG. 7. FIG.

9 is a diagram for explaining a case where a positive timing frequency offset exists.

FIG. 10 is a diagram for explaining PN sequence synchronization and Integrate & Dump when there is a masking output. FIG.

11 is a diagram for explaining an operation when there is a negative timing frequency offset.

12 is a diagram for explaining PN sequence synchronization and integral & dump when there is a chip off output.

* Explanation of symbols for main parts of the drawings

100: digital resampler 110: digital resampler part A

120: digital resampler part B 130: DLL

140: loop filter 150: NCO

200: data sorter 210: PN despreader

220: Integration & Dump Unit 230: Multiplier

240: subtractor

420: Polynomial Filter Output Selector

430: Negative Fractional Delay Conversion

The present invention relates to a tracker in a digital multimedia broadcasting receiver and to a tracker in a mobile broadcast receiver having a new structure having a digital resampler.

Digital multimedia broadcasting can be classified into terrestrial digital multimedia broadcasting and satellite digital multimedia broadcasting. Terrestrial digital multimedia broadcasting provides audio and video services on the move based on orthogonal frequency division modulation (OFDM), and satellite digital multimedia broadcasting is based on code division modulation (CDM) to provide satellite and complementary ground gap fillers. To enable audio and video services on the go.

In a satellite digital multimedia broadcasting receiver, a received signal input to an antenna is converted into a baseband through a tuner, and an automatic gain controller has a constant magnitude of the signal input to A / D (analog / digital). In order to maintain the power, the power of the received signal is measured and multiplied by the calculated gain value, and the ADC samples the signal having a relatively constant magnitude by the AGC and converts the analog signal into a digital signal. Let it be. In order to demodulate a signal in the CDM transmission scheme, the acquisition of a pseudo-noise sequence used for signal spreading should be prioritized. This process consists of two stages: signal acquisition and tracking. .

     The division unit of the pseudo noise sequence is called a chip, and the acquisition is a process of securing signal synchronization within ± 1/2 chips at a receiver, and is performed by a searcher. Signal tracking is a fine tuning of the signal found and is performed in the tracker. In this way, the synchronized signal is despread by multiplying the pseudonoise sequence generated by the receiver, and the symbol of the desired CDM channel is extracted by multiplying the WALSH code used to distinguish the CDM channels.

The process is performed in all the multiple paths found by the searcher, each of which is called a finger.

1 is a view for explaining a tracker (tracker) of a mobile broadcast receiver employing a conventional DLL.

In FIG. 1, the conventional tracker is composed of an analog part 10, an ADC 11 and a VCXO 13, and the digital part 20 includes a selector 21, a DLL 23, an SRG 25, and a despreader ( 27), the loop filter 29, and the DAC 31 are configured.

First, a clock of a frequency higher than an integer multiple of a chip rate generated by a voltage controlled crystal oscillator (VCXO) 13 is input, and the ADC 11 oversamples an input analog signal.

Oversampled data generated by the VCXO 13 and oversampled by the ADC 11 is input to the selector 21 to be drawn. For example, if the input signal is oversampled 8 times, the selector chooses one for every eight input signals. In this case, the selector 21 operates based on a timing error signal generated by the DLL (Delayed Locked Loop, hereinafter referred to as a 'DLL') 23 and passed through the loop filter 29.

The selector 21 outputs not only the chip rate data in position but also 1/2 chip faster data and 1/2 chip slow data while deciding. At this time, the chip data output at the correct position is called main path data, and the data output at the 1/2 chip fast position is called early path data, and the data output at the 1/2 chip slow position. Is defined in the present invention as late path data.

In addition, the SRG 25 outputs a signal generated from the SRG 25 to the DLL 23 and the despreader 27 by a code generator.

Early path data and late path data output from the selector 21 are input to the DLL 23 to generate a timing error signal, and further, the selector ( Main path data output from 21 is input to the despreader 27 to output a despreading signal.

In addition, early path data and late path data output from the selector 21 and input to the DLL 23 generate a timing error signal, and the timing error signal is a Loop Filter ( 29) and a signal converted into an analog signal from a digital-analog converter (DAC) 31 is outputted, and a timing frequency offset component is inputted to the VCXO 12 to provide an analog-to-digital converter (ADC). The clock speed of (11) is adjusted and frequency correction is performed in the ADC (11).

The timing phase offset component output from the loop filter 29 is input to the selector 21 to perform phase compensation to select data corresponding to the most appropriate phase. That is, the conventional tracker is different in frequency compensation and phaser compensation.

As the closed loop is formed in the above manner, tracking is performed in the tracker.

However, the tracker in the conventional digital multimedia broadcasting receiver described above has the following problems.

First, the conventional tracker is not a complete digital system due to the presence of the analog VCXO, so it is necessary to digitally-analog convert the timing frequency offset signal passed through the loop filter.

Second, power consumption is increased because oversampling must be performed by a high integer multiple to operate the selector in the tracker.

Third, because of the existence of analog VCXO that cannot guarantee the same performance in every component, it was difficult to maintain a constant reception performance in mass production of the receiver.

The present invention is to solve the above problems, to provide a complete digital tracker. In addition, the present invention is to provide a tracker to reduce the power consumption of the receiving chip by applying a digital resampler to maintain the operating speed of the ADC at twice the chip rate (chip rate).

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In order to achieve the above object, an example of a tracker in a mobile broadcast receiver for synchronizing a digitized received signal configured according to the present invention is a first digital resampler for pre-signaling the digital signal. ; A digital resampler for compensating the digital signal, including a second digital resampler that post-processes an output signal of the first digital resampler and an output signal of a numerical contorlled oscillator (NCO); A delayed locked loop (DLL) for estimating a timing error using a correlation characteristic of a pseudo noise (PN) code from the compensated digital signal; A loop filter configured to receive and estimate the estimated timing error signal; And an NCO generating an interpolation position information value corresponding to the cumulatively corrected timing error signal.
In this case, the first digital resampler may include a polynomial filter configured to perform polynomial filtering on the input data; And a delay unit for delaying the filtered data.
The second digital resampler may include a selector configured to select a signal output from the first digital resampler; And a negative partial delay converter configured to perform partial negative conversion of a signal input from the NCO.
The DLL may further include a data sorter for correcting and realigning an input chip data signal; A PN despreader that receives the rearranged signal and despreads the PN; An integration & dump unit for integrating and dumping the despread signal to generate symbol data; A multiplier for obtaining symbol power of an early path and a symbol power of a late path of the generated symbol data; And a subtractor that calculates a timing error using the obtained difference of symbol powers.
The data sorter may align the input chip data signal into a main pass, an early pass, and a late pass.
An example of a mobile broadcast receiver having a plurality of fingers configured to extract a CDM symbol of a specific channel through PN despreading and WALSH despreading after synchronizing a signal received through a corresponding path configured according to the present invention And a tracker including a digital resampler for resampling a digital signal at a sampling frequency corresponding to a timing error to compensate for the digital signal, wherein the digital resampler is a shared digital resampler unit and each finger shared by each finger. It is characterized by separating into separate digital resampler unit each configured.
In this case, the digital resampler may have a narrow filter structure.
The shared digital resampler unit may sample the input digital signal and output the same sampling data to the individual digital resampler unit of each finger.
In addition, the individual digital resampler unit may receive different partial delay data for each finger.

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Therefore, according to the present invention, by eliminating the selector used in the conventional tracker system and adopting the digital resampler, not only a much finer pager offset correction but also a frequency offset correction is possible, and even though the digital resampler is used, All fingers share a specific part of the resampler, which greatly reduces the size of the tracker.The system uses a frequency-converted gap filler by separating and converging the carrier frequency offset and the timing frequency offset. Because it is possible to receive at all and is completely digital, the reception rate does not occur due to the performance of analog parts, which ensures a constant reception performance in mass production, and uses the sampling frequency twice as high as the chip plate. Power cow Most of being able to be occupied by an ADC reducing the sampling rate (sampling rate) to reduce significantly the power unknown mobile receiver, is finally implemented in a digital single-chip is easily upset.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can be specifically realized for the above purpose.

Referring to FIG. 2, a first embodiment of a tracker in a mobile broadcast receiver according to the present invention will be described.

The structure proposed in the present invention is a digital resampler 100 consisting of a digital resampler part A (110) and a digital resampler part B (120), a DLL ( 130, a loop filter 140, and an NCO 150.

First, the digital resampler 100 will be described. The digital resampler adopted in the present invention is a structure modified from a general digital resampler used when receiving digital quadrature phase shift keying (QPSK) or vestigial side band (VSB).

3 is a diagram for describing an operation of a general digital resampler.

As shown in FIG. 3, the digital resampler is a kind of filter that extracts data corresponding to a position of a transmission signal from an input signal sampled at a constant frequency.

3, x (1), x (2), ..., x (n) are digital data sampled by the reception sampling frequency. However, in order to extract the correct transmission data due to the offset and phase difference between the transmission sampling frequency and the reception sampling frequency, the desired data from the data between x (1), x (2), ..., x (n) We need to get y (1), y (2), ..., y (n).

As an example of obtaining the desired data, if x (3) is input as the received data, but the data transmitted at this timing is y (3), preferably 3 We need to get the / 4 delayed data. In this case, 3/4 is called a fractional delay and is denoted as u (3).

Therefore, the digital resampler 100 uses the digital signal processing of x (m), x (m-1), x (m-2) ... and u (m) previously inputted to obtain the actual transmission value and the most. This filter outputs an approximate value of y (m). At this time, there are various methods for obtaining y (1), y (2), ..., y (n), but in the present invention, a polynomial FIR interpolator using a Farrow filter structure is preferably used. .

4 is a diagram illustrating a digital resampler to which a fellow filter structure is applied.

Farrow filter structure varies slightly depending on the order of the polynomial of the digital resampler and the number of taps of the filter, and the common configuration is the polynomial filter unit 300 and fractional. It is divided into a fractional delay operation unit 310.

However, in order to apply such a digital resampler to a rake receiver, the digital resampler must be provided for each finger, thereby causing a size problem. Accordingly, the present invention proposes a structure in which all the fingers of the polynomial filter unit 300 share the digital resampler, and the fractional delay operation unit 310 has each finger.

Therefore, when configured as described above, for each finger, the input sample data (x (1), x (2), x (3), ..., x (n)) is common but the fractional delay u ( 1), only u (2), u (3), ..., u (n)) are different, so the output of the polynomial filter unit 300 is used in common, and only the fractional delay operation unit 310 is used for each finger. Because they are used differently, they contribute significantly to reducing the size and power consumption of digital systems.

FIG. 5 is a diagram for explaining the principle of operation of a digital resampler when a negative fractional delay is applied.

In the case of a CDM receiver, since a searcher part generally needs to operate in advance of all receiving systems, the digital sampling rate of the input signal must be configured as an integer multiple of the transmission signal.

Therefore, a difference from the conventional digital resampler is that not only a positive fractional delay exists, but also a negative fractional delay may exist depending on the sign of a sampling frequency offset. However, the conventional digital resampler can only compensate for the positive fractional delay, thus modifying the conventional digital resampler to operate on the negative fractional delay.

Referring to FIG. 5, the operation of the digital resampler in the case of a negative fractional delay as well as a positive fractional delay will be described. When the fractional delay to be applied to x (1) is negative, the output value y (1) is equal to the above. Equivalent to applying a positive fractional delay u '(1) to x (0), one sample prior to x (1). The relationship between u (1) and u '(1) is as follows.

u '(1) = 1 + u (n)

That is, it can be seen that the relative distance from y (1), which is a value to be restored at the x (1) position, is negative (meaning opposite to the positive direction). Therefore, looking at y (1) from the position of x (0) which is one input data of x (1), it can be seen that the relative distance is positive.

Using this principle, if u (1), which is the fractional delay from the current position x (1) to y (1), is positive, then apply x (1) and u (1) as it is, and u (1) If the negative number is x (0) instead of x (1), u (1) = 1 + u (n) of Equation 1 is used to obtain the interpolation value y (1).

6 is a view for explaining a digital resampler according to the present invention.

The digital resampler according to the present invention may include a digital resampler part A 400 and a digital resampler part B 410.

In addition, the polynomial filter output selector 420 of the digital resampler part B 410 may use x (1) according to whether the input fractional delay is positive or negative. Negative fractional delay conversion unit 430 determines whether the fractional delay u (1) is positive or negative, and if it is positive, exports u (1) and negative Is a part that outputs 1 + u (1) which is u '(1).

The digital resampler part A 400 is a polynomial filter part which only needs one in the rake receiver, and the digital resampler part B 410 is a part which must be entered for each finger. Here, the fingers of the polynomial filter, which occupies most of the size of the digital resampler, are shared by all fingers, which significantly reduces the overall system volume.

In relation to this, when the input fractional delay is negative, the negative fractional delay converter 430 converts the positive fractional delay into the positive fractional delay by applying Equation 1, and then the polynomial filter output selector 420. In u, u '(n) is applied to the past output of the sample, not the output of the current polynomial filter, to finally implement a negative fractional delay.

In FIG. 2, the signal resampled by the digital resampler 100 is input to the DLL 130 to output a timing error signal, and the timing error signal output from the DLL 130 is input to the loop filter 140 and filtered. The NCO 150 receiving the filtered timing error signal generates an interpolation position information value corresponding thereto and outputs the interpolated position information value to the digital resampler part B 120.

FIG. 7 is a diagram for describing the DLL of FIG. 2.

The DLL 130 includes a data aligner 200, a PN despreader 210, 210-1, and 210-2, an integration & dump unit 220, a multiplier 230, and an adder. 240 is configured to include.

The DLL 130 input signal passes through the digital resampler 100 and has chip data of 2x chip rate (32.768Mhz) at which a chip off or masking situation occurs. to be.

The data aligner 200 performs a process of down sampling the 2x chip rate (32.768Mhz) chip data to 1x chip rate (16.384Mhz) between a main path, an early path, and a late path. The alignment will be broken, which will correct and rearrange it.

This rearranged main path, early path, and late path at 1x chip rate is despread by a PN code whose phase is adjusted according to a chip off or masking signal adapted to the 1x chip rate.

In this case, the SRG 260 changes the phase of the PN code generated by receiving the chip off signal and the masking signal of 1x chip rate from the data aligner 200.

The PN despreaders 210, 210-1, and 210-2 despread the PN code generated from the SRG 260 and the output chip data of the data sorter 200 through an XOR operation.

The Integration & Dump unit 220 integrates a chip corresponding to a coding gain (64 in case of satellite digital multimedia broadcasting) of the chip data from which the PN code is stripped, and dumps the chip data into symbol data. Change it. Therefore, in the above case, an early symbol and a late symbol for generating a timing error are output.

The multiplier 230 outputs the in-phase early symbol data inputted from the integration & dump unit 220 and (Quadrature Early Symbol Data = I ^ 2 + Q ^ 2). The Power formula is used to find the power of the Early Symbol, and the power of the Late Symbol is calculated in the same way.

The timing error is obtained by using the difference between the early path power and the late path power thus obtained.

FIG. 8 is a diagram for describing the data sorter of FIG. 7.

Chip 2x at the top passes through the digital resampler 100 of FIG. 2 after the input analog signal is sampled at 32.768Mhz, which is twice the code rate of the satellite digital multimedia broadcasting reception system (16.384Mhz). Indicates a signal.

Here, the numeric data (1,2,3,4 ..) consisting of integers is the data corresponding to the main path location, and the data with decimal points (1.5, 2.5, 3.5, ..) are used for the early path and not the main path. Indicates that the data corresponds to the late path.

The signal passing through the digital resampler 100 causes a chip to fall out (Chip Off situation) or the chip is repeated once more (Masking situation) according to the magnitude of the timing frequency offset between the transmission and reception signals. .

In FIG. 8, it can be seen that 2.5 is repeated twice in chip2x. In this case, masking occurs at this position. The digital resampler transmits a masking or chip off status indication signal (masking flag, chip off flag) to the masked signal or the signal location where the chip off occurs in synchronization with Chip 2x which is an output data signal.

In addition, the masking flag and the chip off flag are downsampled together when down sampling at a 1x chip rate. The status display signal at this time is referred to as masking flag 1x and chip off flag 1x. This signal is input to the PN code generator for PN despreading to adjust the phase of the PN code and also to adjust the integral section in the Integrate & Dump unit 220 for making a symbol.

In this case, if the conventional down sampling method is applied, the alignment of the main path, the early path, and the late path is misaligned. Referring to FIG. 8, it can be seen that main 1x, which is a main path, has 2.5 or 3.5 instead of an integer, and main path data 2, 3, and 4 exist in Early 1x, which is an early path. It can be seen.

Therefore, there is a need for a method of changing the position of the main path by using the relationship between the chip off signal and the masking signal. Implementing this is the data sorter 200. Hereinafter, the operation of the data sorter 200 will be described.

Initially, the main path data is extracted along the main 1x, and when a signal indicating a masking flag 1x situation is encountered, the location where the main path data is extracted is changed to an early 1x. This tells us that the primary path remains constant.

Therefore, the data sorter 200 aligns the alignment between the main path and the early and late in the same principle.

In the tracker of the present invention, the DLL 130 is the most important control part. This is because the present invention has to be considered in the full digital domain up to the timing frequency offset as compared to the conventional DLL, which only had to consider timing phase offset.

When the timing frequency offset is positive (transmission timing frequency <receive timing frequency), the number of passing through the digital resampler 100 is smaller than the number of data input to the actual digital resampler 100. On the contrary, when the timing frequency offset is negative (transmit timing frequency> receive timing frequency), the digital resampler 100 outputs more than the digital resampler 100 input.

FIG. 9 is a diagram for describing a case in which a positive timing frequency offset exists.

In this case, it can be seen that the transmitted timing period, which is the interval between y (n), which is the signal that restored the transmission signal, is wider than the received sampling period, which is the interval between the received signals x (n). have. Therefore, it can be seen that the transmission timing frequency <receiving timing frequency.

In this case, it can be seen that the fractional delay u (n) gradually increases over time and a point exceeding 1 will occur (u (4) in FIG. 9). Since there is no transmission signal to be transmitted, the previous output signal y (3) is repeatedly output to y (4). Such an output is defined as a masking output in the present invention.

In this context, other digital receiving systems use a masking clock to solve this case, but in a CDM system a masking clock is used because the masking position is different for each finger. There is a problem that the clock timing of the clock is shifted.

Therefore, in the present invention, the previous output data is output once more during the masking situation, and the actual transmission timing is restored to be designed in the symbol state (Symbol Domain) after Integrate & Dump is performed in the Integrate & Dump unit 220. have.

10 is a diagram for explaining PN sequence synchronization and integral & dump when there is a masking output.

In the present invention, when five chips form one symbol, in the present embodiment, when a masking output exists between the five chips, the chip data is not a transmission chip data but a timing. Since it is dummy data to fit, it ignores the data and takes 6 chip data into Integrate & Dump to make one symbol. In this case, the duration of the generated symbol data is equal to the time of six receiving chips. Therefore, the symbol duration becomes wider, and as a result, timing with the transmission symbol is restored.

In this case, however, it should be noted that in the case of the CDM receiver, the PN sequence at the transmission and the PN sequence at the reception must be exactly synchronized. Therefore, if a masking output occurs during the digital resampler output, the PN sequence must be repeated in synchronization with it.

Referring to FIG. 10, the input signals are y (1), y (2), y (3), y (4), y (5), y (6), y (7), y (8) , y (9) .. The PN sequence that is synchronized with this when it comes in is p (1), p (2), p (3), p (4), p (5), p (6), p (7), p (8), p (9) .. When masking output occurs between input signals and y (3) is repeated, the PN sequence p (3) must be repeated accordingly. Is showing.

11 is a diagram for explaining an operation when there is a negative timing frequency offset.

The negative timing frequency offset case is the opposite of the positive timing frequency offset mentioned above. On the contrary, since the received sampling frequency is slower than the transmission timing frequency, the fractional delay exceeds -1 as time passes, so it is necessary to keep referring to the past polylynomial filter output. A problem occurs.

Referring to FIG. 11, it can be seen that as time passes, the magnitude of the negative fractional delay gradually increases, but eventually exceeds -1 in the case of u (4). In this case, since y (4) cannot occur in x (4) which u (4) refers together, it can be seen that x (3), which is a past output, must be referred to. This happens over and over and over, and you end up with an infinite number of buffers.

In order to solve the above problems, the present invention uses the concept of chip off. That is, for fractional delays exceeding -1, chip data is discarded and the symbol data is obtained by passing through the integration & dump unit 220.

In the case of FIG. 11, y (4) output by referring to u (4) exceeding -1 is obtained, and u '(4) and x (4) are used for the next chip data, y (5). It is obtained by. In this case, the relationship between u (4) and u '(4) is as follows.

u '(4) = mod [u (4) + Tt, 1]

In Equation 2, Tt is a ratio of a timing duration of a transmitter and a sampling duration of a receiver.

FIG. 12 is a diagram for explaining PN sequence synchronization and integral & dump when there is a chip off output.

Here, in the case of Integration & Dump, since the PN sequence and Sync must move in the same way as the positive timing frequency offset, chip off occurs between y (2) and y (4) as shown in FIG. If not, the corresponding PN sequence, p (3), is also lost and the number of chips performing Integrate & Dump is four instead of five. Accordingly, it can be seen that the symbol period matches the symbol period of the transmitter.

In addition, in a satellite digital multimedia broadcasting system, pilot channel information not only includes pilot information but also information related to forward error correction (FEC), so that pilot signal information duty is actually present in the pilot channel. Duty rate is only 50%. In addition, during initial acquisition, if the carrier frequency offset is not corrected, a problem occurs that the S-curve of the coherent DLL collapses.

Therefore, in the present invention, timing errors are extracted in a non-coherent manner in order to secure robustness in pilot channel characteristics and carrier offset of satellite digital multimedia broadcasting.

In addition, in the present invention, Integrate & Dump and Integration & Dump are used to have the same meaning.

The present invention is not limited to the above-described embodiments, and can be modified by those skilled in the art as can be seen from the appended claims, and such modifications are within the scope of the present invention.

The effects of the tracker in the digital multimedia broadcasting receiver according to the present invention described above are as follows.

First, by eliminating the selector used in the conventional tracker system and adopting a digital resampler, not only more precise phaser offset correction but also frequency offset correction are possible.

Second, despite the use of the digital resampler, all the fingers share a specific part of the digital resampler, which leads to a significant reduction in the size of the tracker.

Third, the carrier frequency offset and the timing frequency offset can be separately converged to be received even in a system using a frequency transform type gap filler.

Fourth, because it is composed of all-digital, the reception rate does not decrease due to the performance of analog parts, so it is possible to guarantee a constant reception performance in mass production.

Fifth, the sampling frequency, which is twice as high as the chip rate, reduces the ADC sampling rate, which accounts for most of the power consumption, thereby dramatically reducing the power consumption of the mobile receiver.

Sixth, it is digitally implemented to facilitate single chipping.

Claims (10)

A tracker in a mobile broadcast receiver for synchronizing a digitized received signal, A first digital resampler for pre-processing the digital signal; A digital resampler for compensating the digital signal, including a second digital resampler for post-signaling the output signal of the first digital resampler and the output signal of the NCO; A DLL for estimating timing error using the correlation characteristic of the PN code from the compensated digital signal; A loop filter for receiving and accumulating the estimated timing error signal; And And an NCO for generating interpolation position information values corresponding to the cumulative corrected timing error signal. The method of claim 1, wherein the first digital resampler, A polynomial filter unit for polynomial filtering the input data; And And a delay unit for delaying the filtered data. The method of claim 1, wherein the second digital resampler, A selector for selecting a signal output from the first digital resampler; And And a negative partial delay converter for negative partial delay conversion of the signal input from the NCO. The method of claim 1, wherein the DLL, A data sorter for correcting and realigning an input chip data signal; A PN despreader that receives the rearranged signal and despreads the PN; An integration & dump unit for integrating and dumping the despread signal to generate symbol data; A multiplier for obtaining a symbol power of an early path and a symbol power of a late path of the generated symbol data; And And a subtractor for calculating a timing error using the obtained difference of symbol powers. The method of claim 4, wherein And the data aligner aligns the input chip data signal into a main pass, an early pass and a late pass. In a mobile broadcast receiver having a plurality of fingers configured to extract the CDM symbols of a specific channel through PN despreading and WALSH despreading after synchronizing the signals received through the path in the tracker, And a tracker including a digital resampler to resample the digital signal to a sampling frequency corresponding to a timing error to compensate for the digital signal. And the digital resampler is divided into a shared digital resampler unit shared by each finger and a separate digital resampler unit configured for each finger. The method of claim 6, And the digital resampler has a fellow filter structure. The method of claim 6, The shared digital resampler unit samples the input digital signal and outputs the same sampling data to the individual digital resampler unit of each finger. The method of claim 6, And the individual digital resampler unit receives different partial delay data for each finger. delete

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