KR100662403B1 - Having Parallel Structure CDM receiver - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mobile broadcast receiver. In order to demodulate a signal received through a multi-path, a digital resampler extracts data corresponding to a position of a transmission signal from the input signal. A searcher for receiving the output signal of the signal and acquiring synchronization of the signal; It provides a CDM receiver having a parallel structure characterized in that it comprises a tracker for receiving the output signal of the digital resampler at each finger activated by the searcher to track the synchronization of the signal (finger). . Therefore, the parallel structure can decompose adjacent multipath received signals around 10 ns, thereby increasing the SNR of the output signal to increase the reception rate.

CDM Receiver, Searcher, Tracker

Description

CDM receiver having a parallel structure {Having Parallel Structure CDM receiver}

1 is a conceptual block diagram of a CDM receiver incorporating the present invention.

2 is a block diagram showing the structure of a new CDM receiver using a parallel structure of a searcher and a tracker according to the present invention.

3 is a view for explaining a digital resampler applied to the present invention.

4 is a block diagram illustrating an internal configuration of a digital resampler applied to the present invention.

5 is a block diagram illustrating the internal configuration of a searcher NCO according to the present invention.

6 is a block diagram illustrating the internal configuration of a DLL to which the present invention is applied.

7 is a block diagram illustrating an internal configuration of a finger NCO according to the present invention.

* Explanation of symbols for main parts of the drawings

4: searcher 5-1 ~ 5-n: tracker

25: matching filter 26: Farrow filter

27: fractional delay calculation unit 28: DLL

29: finger proportional filter 30: timing error adder

31: common integral filter 32: finger NCO

33: searcher NCO 34: searcher

The present invention relates to a mobile broadcast receiver, and more particularly, to a structure in which a searcher and a tracker are structured in parallel to reduce mismatch between the searcher and the tracker, thereby increasing the efficiency of the receiver.

DMB (Digital Multimedia Broadcasting) can be divided into terrestrial DMB and satellite DMB.

The terrestrial DMB provides audio and video services while moving based on Orthogonal Frequency Division Multiplexing (OFDM), and the satellite DMB is a satellite based on Code Division Multiplexing (CDM). In order to solve the shadow area that does not receive a signal from the satellite and to complement the ground gap filler to enable audio and video services on the move.

The received signal input to the antenna of the satellite DMB receiver is converted into baseband through a tuner, and the automatic gain controller (AGC) multiplies the gain value calculated by measuring the power of the received signal. The amplitude of the signal is kept constant and output to A / C, and the A / D converts an analog signal into a digital signal by sampling a signal having a relatively constant magnitude by the AGC.

In order to demodulate the signal in the CDM transmission scheme, the acquisition of a pseudo-noise sequence used for spreading the signal should be prioritized. This process involves two steps: acquisition and tracking of the signal. Is done.

     The division unit of the pseudo noise (PN) sequence is called a chip, and the acquisition is performed by a searcher in a process of securing signal synchronization within ± 1/2 chips at a receiver.

Signal tracking is performed in a tracker by finely synchronizing the captured signals. In this way, the synchronized signal is despread by multiplying the pseudonoise sequence generated by the receiver, and the symbol of the desired CDM channel is extracted by multiplying the WALSH code used to distinguish the CDM channels.

The capturing and tracking processes are performed in all multi-paths searched by the searcher, and each is called a finger.

However, in the structure of the conventional CDM receiver, the searcher is located immediately after the matched filter, and the tracker performs a tracking after passing through the matched filter and the resampler.

In addition, even if the searcher delivers the location information by capturing the signal, the tracker does not receive the fractional delay, which is the detailed location information, from the searcher, so the tracker starts from a position where there is a slight error at the exact location captured by the searcher. Since tracking starts, there is a problem that the efficiency of the tracker may be reduced, such that convergence in the wrong direction may occur for the adjacent multipath channel of about 10 ns.

The present invention is to solve the above problems, an object of the present invention is to provide a new CDM receiver having a parallel structure in order to reduce the mismatch coming from the structure of the conventional searcher and tracker.

Another object of the present invention is to provide an apparatus capable of increasing the efficiency of a tracker by exchanging and receiving minute position error information generated by a difference between the clock frequency of a transmitter and a receiver between the searcher and the tracker.

In order to achieve the above object, the present invention provides a digital resampler for extracting data corresponding to the position of a transmission signal from the input signal to demodulate a signal received through a multi-path. A searcher 34 which receives an output signal of the signal and acquires synchronization of the signal; It provides a CDM receiver having a parallel structure characterized in that it comprises a tracker for receiving the output signal of the digital resampler at each finger activated by the searcher to track the synchronization of the signal (tracking) do.

At this time, the searcher 34 and the tracker preferably share the fellow filter 26 of the digital resampler.

In addition, the searcher 34 may include the searcher 4 and the fractional delay calculator 27 of the digital resampler.

Another object of the present invention is a searcher NCO 33 for converting a loop filtered timing error generated from a tracker into a fractional delay value; Provided is a CDM receiver having a parallel structure, comprising a finger NCO 32 for receiving a fractional delay of a signal acquired at the searcher from the searcher NCO and used for tracking.

At this time, the searcher NCO 33 preferably takes an output of a common integrator filter among the loop filters as an input.

In addition, the searcher NCO 33 preferably outputs from the searcher to the fractional delay calculator 27 of the digital resampler.

The finger NCO 32 preferably outputs the output of the searcher NCO and the output of the loop filter to the fractional delay calculation unit 27 of the tracker.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

In addition, the terms used in the present invention was selected as a general term widely used as possible now, but in certain cases, the term is arbitrarily selected by the applicant, in which case the meaning is described in detail in the corresponding description of the invention, It is to be clear that the present invention is to be understood as the meaning of terms rather than names.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can be specifically realized for the above purpose.

In a mobile communication network in which cell planning is performed using a gap filler or a repeater, signals are transmitted to a receiver through various paths. In this case, the phase (phase) is different between each path signal.

However, in the case of frequency, there is no big difference, which is caused by an oscillator driving a system of a terminal and a gap filler. The oscillator used in the receiver has a large error due to the cost and the simplification of the design structure, while the gap filler uses a very precise oscillator, so the frequency between the multipath received signals transmitted from two or more gap fillers and received by the CDM receiver is high. The difference is very small.

1 is a conceptual block diagram of a CDM receiver incorporating the present invention.

In the reception process, a received signal transmitted through a multi-path and input through an antenna is converted from a tuner 1 to a base band, and the converted signal is converted into an A / D 3. In order to do this, the A / D (3) is converted into a digital signal through an automatic gain control unit (2) which measures the power of the received signal and multiplies the calculated gain value. .

At this time, in order to demodulate a signal in the CDM transmission scheme, the acquisition of a pseudo-noise sequence used for signal spreading should be prioritized. This process is performed in two steps, signal acquisition and tracking. The acquisition is performed in the searcher 4, and the tracking is performed in the trackers 5-1 to 5-n.

In this way, the synchronized signal is despread by multiplying the pseudonoise sequences generated at the receiving apparatus through the despreaders 6-1 to 6-n, and the desired CDM by multiplying the WALSH codes used to distinguish the CDM channels. Extract the symbols of the channel.

This process is performed in all the multiple paths found by the searcher 4, each called a finger.

In this case, the frequency offset estimator 7 estimates the frequency offset for each finger, synthesizes it, and then feeds back to the tuner 1 to correct the frequency offset.

The extracted symbol is synthesized by the rake synthesizer 8, in which rake synthesis is performed on all CDM channels to be demodulated, and the synthesized signal is decoded by an AV decoding stage through a forward error correction encoding unit 9. Is displayed.

Now, a preferred embodiment of a new CDM receiver having a parallel structure according to the present invention will be described.

The present invention relates to the structure of the searcher (4) and the trackers (5-1 to 5-n) in the process of capturing and tracking the signal, which is converted into a digital signal via the A / D (3) as described above. The signal is input to a matched filter 25. The matched filter 25 is a filter that enables the most efficient reception in a white Gaussian channel environment, and is a pulse shaping filter of a transmitter. It uses the same filter as the Shaping Filter and removes noise in the range where there is no transmission data.

The signal from which the noise is removed through the matching filter 25 is now captured by the searcher 34 and the tracker 5-1 to 5-n tracks the captured signal. The searcher unit 4 is located between the matching filter 25 and the digital resamplers 26 and 27, and the tracker is located at the rear end of the digital resampler, so that the searcher unit 34 and the tracker unit 5- are located. There was a problem that miss-match could occur in the process of capturing and tracking between 1 ~ 5-n).

Thus, in order to exclude the possibility of the mismatch, the present invention adopts a parallel structure to the searcher 34 and the tracker 5-1 to 5-n. Referring to the accompanying drawings, FIG. According to the present invention, a block diagram showing the structure of a new CDM receiver using the parallel structure of the searcher 34 and the trackers 5-1 to 5-n is shown.

Referring to FIG. 2, the receiver is divided into a searcher 34 and trackers 5-1 to 5-n. First, the searcher 34 includes a searcher 4 and a digital resampler. (26, 27), the searcher NCO (33), the tracker (5-1 to 5-n) is a finger NCO (32), digital resampler (26, 27), DLL (Delayed Locked Loop, (Hereinafter referred to as a 'DLL') 28, a despreader 6, a timing error combiner 30, and loop filters 29 and 31.

First, the searcher 34 is located between the conventional matched filter 25 and the digital resamplers 26 and 27 and mismatches with the tracker units 5-1 to 5-n located at the rear end of the digital resampler. In order to solve the problem of mismatch, the problem is solved by forming a parallel structure by positioning the rear end of the digital resamplers 26 and 27 as the trackers 5-1 to 5-n.

Hereinafter, the searcher 34 and the tracker 5-1 to 5-n will be described separately in connection with the present invention. A description will be given in the order of receiving process. First, the digital resamplers 26 and 27 common to the searcher 34 and the trackers 5-1 to 5-n will be described. It is a figure for demonstrating the resampler 26,27.

As shown in FIG. 3, the digital resamplers 26 and 27 are a type of filter that extracts data corresponding to a position of a transmission signal from an input signal sampled at a constant frequency.

3, x (1), x (2), ..., x (n) are digital data sampled by the reception sampling frequency. However, in order to extract the correct transmission data due to the offset and phase difference between the transmission sampling frequency and the reception sampling frequency, the desired data from the data between x (1), x (2), ..., x (n) We need to get y (1), y (2), ..., y (n).

As an example of obtaining the desired data, if x (3) is input as the received data, but the data transmitted at this timing is y (3), preferably 3 We need to get the / 4 delayed data. In this case, 3/4 is called a fractional delay and is denoted u (3).

Therefore, the digital resamplers 26 and 27 actually transmit by digital signal processing of previously inputted x (m), x (m-1), x (m-2) ... and u (m). A filter that outputs y (m), which is the closest value. At this time, there are various methods for obtaining y (1), y (2), ..., y (n), but in the present invention, a polynomial FIR is preferably applied with a narrow filter structure. interpolator).

The Farrow filter structure varies slightly depending on the order of the polynomial of the digital resampler configured by the designer and the number of taps of the filter. A common configuration is the polynomial filter unit and the frag. It is divided into a national delay operation unit.

However, in order to apply such a digital resampler to a rake receiver, the digital resampler must be included in each finger, which causes a problem of size. Accordingly, the present invention proposes a structure in which all the fingers share the digital resampler, and that only the fractional delay operation unit has a finger for each finger.

Therefore, when configured as described above, for each finger, the input sample data (x (1), x (2), x (3), ..., x (n)) is common but fractional. Only the Fractional Delay (u (1), u (2), u (3), ..., u (n)) is different, so the polynomial filter output is used in common and only the fractional delay calculator Each uses differently, which contributes to the reduction of digital system size and power consumption.

4 is a block diagram illustrating an internal configuration of a digital resampler applied to the present invention.

The digital resampler according to the present invention includes a digital resampler part A (400) and a digital resampler part B (410).

In addition, the polynomial filter output selector 420 of the digital resampler part B 410 determines whether to use x (1) or x (0) according to whether the input fractional delay is positive or negative. The negative fractional delay conversion unit 430 determines whether the fractional delay u (1) is positive or negative, and outputs u (1) if it is positive and u '(1) if it is negative. Outputs + u (1).

The digital resampler part A 400 is a polynomial filter unit which requires only one in a rake receiver, and the digital resampler part B 410 is a part which must be entered for each finger. Here, the fingers of the polynomial filter, which occupies most of the size of the digital resampler, are shared by all fingers, which significantly reduces the overall system volume.

In this regard, when the input fractional delay is negative, the negative fractional delay converter 430 converts the positive fractional delay into a positive fractional delay, and then the output of the current polynomial filter is changed by the polynomial filter output selector 420. Instead, u '(n) is applied to the past output of the sample to finally implement a negative fractional delay.

The searcher 34 includes the fractional delay calculator 27, the searcher NCO 33, and the searcher 4 of the digital resampler described above.

The searcher NCO 33 converts a loop-filtered timing error signal, which will be described later, into a fractional delay which is one of the inputs of the digital resampler.

Referring to the internal structure of the NCO 33 with reference to the accompanying drawings, Figure 5 is a block diagram of the internal configuration of the searcher NCO according to the present invention.

Referring to FIG. 5, the loop filtered timing error data is added to W, which is a value between a transmitter end system data clock and a receiver end system data clock. For example, if the transmit system data clock is 32.768 MHz and the receive system data clock is 35 MHz, the W value is 35 / 32.768 = 1.068.

This means that the data clock of the receiving end is faster than the data clock of the transmitting end.

Referring to FIG. 5, a timing error after a loop composed of the digital resamplers 26 and 27, the tracker, the timing error summing unit 30, the loop filters 29 and 31, and the searcher NCO 33 converges. Even if is zero, the fractional delay of the NCO output is not zero.

The clipper 520 causes the loop-filtered timing error signal added to the W to pass through the clipper. The clipper may cause a momentary malfunction of a DLL that generates a timing error or an instant instability of the tracker loop itself. Therefore, when a timing error that is abnormally larger than the normal predicted value is inputted, it plays a role of stabilizing input values larger than a certain range in order to prevent the loop itself from diverging due to instantaneous malfunction.

The modulo operation unit 540 is a block that performs a modulo 1 operation. For example, a block that performs a modulo 1 operation such as 1.5-> 0.5, 3.25-> 0.25, and 1 passes through the modulo 1 operation. The smaller output value is the fractional delay value.

The integer extracting unit 560 is a block for extracting only the integer part of the input data. For example, the integer extracting unit 560 performs an operation such as 2.4-> 2, 4.78-> 4.

The masking chipoff generator 570 recognizes normal operation when the input from the integer extracting unit 560 is 1 and generates a masking flag only when 2, without generating any output signal. If zero), an operation of generating a chipoff flag is performed.

The searcher's fractional delay calculator 27 receives the searcher's fractional delay from the searcher NCO 33 and calculates the output of the searcher 4 by outputting it to the searcher 4.

The searcher 4 receives the output of the fractional delay calculating section 27 and starts capturing the synchronization of the signal, and outputs the captured result for each finger. In this way, the operation in the searcher 34 ends.

The tracker includes the digital resampler 26 and 27, the DLL 28, the despreader 6, the timing error adder 30, the loop filter 29 and 31, and a finger. NCO 32.

The digital resampler 26, 27 in the tracker has the same function and structure as the digital resampler in the searcher 34 described above, and is composed of a fellow filter 26 and a fractional delay calculation unit 27. However, unlike the searcher, the fractional delay calculator is present for each finger and exists as many as the number of fingers. The fellow filter 26 has a structure in which the searcher 34 and the tracker share each other. do.

Referring to FIG. 2, the signal output from the fractional delay calculating unit 27 of the digital resampler is input to the DLL 28, which uses the PN correlation characteristic from the digital signal compensated by the digital resampler. The timing error signal is estimated.

Referring to the accompanying drawings, Figure 6 is a block diagram illustrating the internal configuration of a DLL applied to the present invention.

The DLL 28 includes a data aligner 600, a PN despreader 610, 610-1, 610-2, an integration & dump unit 620, a multiplier 630, and a subtractor. And (Adder) 640.

The DLL 28 input signal is 2x chip rate (32.768Mhz) chip data that has passed through a digital resampler and has a chip off or masking situation.

The data aligner 600 may include Main Path, Early, and Early Sampling during down sampling of 2x chip rate (32.768Mhz) to 1x chip rate (16.384Mhz). The alignment between the late paths is broken, and it plays a role of correcting and rearranging them.

The data in which the main path, early and late paths are rearranged at the 1x chip rate is despread by the PN code whose phase is adjusted according to the chip off signal or the masking signal changed to the 1x chip rate.

At this time, the SRG 660 changes the phase of the PN code generated by receiving the chip off signal and the masking signal of 1x chip rate from the data aligner 600.

In addition, the PN despreaders 610, 610-1, and 610-2 despread the PN code generated from the SRG 660 and the output chip data of the data sorter 600 through an XOR operation.

In addition, the integration & dump unit 620 integrates the chip corresponding to the coding gain (64 in the case of satellite DMB) of the chip data from which the PN code is stripped, dumps the chip data, and converts the chip data into symbol data. Therefore, in the above case, early symbols and late symbols for generating a timing error are output.

The multiplier (Square) 630 is the power of the Early Symbol by using the formula I ^ 2 + Q ^ 2 = Power on the Inphase Early Symbol Data and Quadrature Early Symbol Data output from the Integration & Dump unit 620. ). The power of the Late Symbol is calculated in the same way.

The timing error is obtained by using the difference between the Early Path Power and Late Path Power.

The signal output from the digital resampler is input to the DLL 28 with reference to FIG. .

The DLL 28 receives a PN code from the SRG 660 which is a PN code generator, receives a signal output from the digital resampler, and outputs a signal to the SRG 660, the despreader 610, and a loop filter. .

Accordingly, the timing error signal output from the DLL 28 is input to the loop filter to accumulate the correction. A PI loop filter is used as the loop filter.

However, the difference between the present invention and the tracker structure of the conventional CDM receiver is that the PI loop filter is divided into two parts.

Referring to FIG. 2, the timing error signal output from the DLL 28 is input into two parts, which are input to the finger proportional filter 29 and the common integral filter 31.

First, the finger proportional filter 29 is proportional to the timing error signal output from the DLL 28 and the common and the timing error signal output from the finger proportional filter 29. And an adder for adding the timing error signal filtered out by the integrating filter unit 31. In this case, the finger proportional filter unit 29 is configured for each finger.

The common integration filter unit 31 receives a timing error signal output from the DLL 28, and includes a timing error synthesizer 30 and a common integration filter 31.

The timing error synthesizer 30 synthesizes the timing error signal output from the DLL 28 of each finger and outputs the synthesized signal to the common integration filter 31. The timing error signal passing through the common integration filter 31 is input to the finger NCO in addition to the timing error signal passing through the proportional filter for each finger.

Looking at the structure of the finger NCO 32, Figure 7 is a block diagram of the internal configuration of the finger NCO according to the present invention.

In order to minimize mismatch between the searcher 34 and the tracker, the finger NCO 32 in FIG. 7 receives the fractional delay information of the searcher NCO 33 and uses the information as initial position information. Otherwise, the functional part of the finger NCO is the same as the searcher NCO 33 described above.

The finger NCO 32 converts the loop-filtered timing error signal into a fractional delay value corresponding thereto and inputs the fractional delay calculator 310 of each finger to output a signal whose timing is corrected.

Therefore, the finger NCO 32 sums up the fractional delay information captured by the searcher NCO 33 at the current searcher, the output of the finger proportional filter 29 and the output of the common integration filter 31 for each finger. The negative fractional delay calculation unit 27 outputs the negative fractional delay calculation unit 27 to perform tracking as described above.

This signal is input into the DLL to form a tracker loop.

In this way, the structure of the new CDM receiver having the parallel structure in the present invention has been described. As described above, the present invention adopts the parallel structure for the first reason. First, the match part and the tracker part are taken in parallel to achieve a mismatch. It can be minimized. This is because the conventional searcher is immediately after the synthesis filter, and the tracker passes through the matching filter and passes through the Farrow filter and the fractional delay function, so that the mismatch between the searcher and the tracker is likely to occur.

Second, the parallel structure as shown in FIG. 2 is added to the searcher section to separately add the NCO to transmit the fractional delay currently captured by the searcher to the finger NCO to be captured by communicating the searcher section and the tracker section. In the tracking of the received signal, the tracker may increase the efficiency of the tracker by tracking from the point where the searcher is captured, not the position of the input signal.

At this time, the searcher NCO 33 receives only the output of the common integration filter 31 among the loop filters in order to receive only the average value of the timing frequency component having a slight difference in all fingers.

The signal tracked through the above-described configuration block and process is entered into the rake synthesizer 8 and decoded and displayed through the forward error correction coding unit 9, and the output of the tracker is input to the frequency offset estimator 7 and is tuned. Feedback to (1) is used to compensate for the frequency offset.

Referring to the effect of the CDM receiver having a parallel structure according to the present invention described above are as follows.

First, according to the present invention, since the searcher portion is disposed at the rear end of the digital resampler to have a parallel structure, the mismatch in the relationship with the tracker can be reduced.

Second, according to the present invention, the information captured by the searcher is searched and transmitted to the finger NCO through the NCO, so that the communication between the searcher and the tracker is performed, thereby increasing the efficiency of the tracker.

Third, according to the present invention, since all parts of the tracker are fully digitally implemented, there is an effect of guaranteeing uniform quality because the performance difference is small for each receiver during mass production.

Fourth, according to the present invention, since the A / D sampling rate can be operated at 32.768 MHz, which is twice the operating frequency of the transmitting end, the A / D operation rate, which occupies most of the power consumption of the receiving chip, is reduced. It is effective to reduce power consumption.

Fifth, the present invention can decompose a very close multipath signal of about 1.5 chips (100 ns), thereby improving reception performance.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (7)

In order to demodulate a signal received via multi-path, A searcher configured to receive an output signal of a digital resampler for extracting data corresponding to a position of a transmission signal from the input signal and to acquire synchronization of the signal; And a tracker unit configured to receive an output signal of the digital resampler at each finger activated by the searcher unit and track the synchronization of the signal. The method of claim 1, And the searcher unit and the tracker unit share a fellow filter of the digital resampler. The method of claim 2, The searcher unit includes a searcher and a fractional delay calculator of the digital resampler. A searcher NCO for converting a loop filtered timing error generated from the tracker into a fractional delay value; And a finger NCO used for tracking by receiving a fractional delay of a signal currently captured by the searcher from the searcher NCO. The method of claim 4, wherein The searcher NCO is a CDM receiver having a parallel structure, characterized in that the output of the common integral filter (Common Integrate Filter) of the loop filter as an input. The method of claim 4, wherein The searcher NCO also outputs from the searcher to the fractional delay calculator of the digital resampler. The method of claim 4, wherein The finger NCO is a CDM receiver having a parallel structure, characterized in that the output of the searcher NCO and the output of the loop filter as an input to the fractional delay calculation unit of the tracker.

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