WO2001097169A1 - Method for treating chips which are mounted on a carrier tape - Google Patents

Method for treating chips which are mounted on a carrier tape Download PDF

Info

Publication number
WO2001097169A1
WO2001097169A1 PCT/NL2001/000447 NL0100447W WO0197169A1 WO 2001097169 A1 WO2001097169 A1 WO 2001097169A1 NL 0100447 W NL0100447 W NL 0100447W WO 0197169 A1 WO0197169 A1 WO 0197169A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
chips
tape
reel
station
Prior art date
Application number
PCT/NL2001/000447
Other languages
French (fr)
Inventor
Benjamin Slager
Original Assignee
Nedcard B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nedcard B.V. filed Critical Nedcard B.V.
Priority to AU74671/01A priority Critical patent/AU7467101A/en
Publication of WO2001097169A1 publication Critical patent/WO2001097169A1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips

Abstract

Method for treating chips, mounted on a carrier tape, the contact surfaces of said chips being free accessible, according to which method the tape is unwounded from a first reel (16), guided along one or more treating stations (20, 22, 24) and wound onto a second reel (18), whereby one of said treating stations (24) comprises contact pins which are pressed onto the contact surfaces of the chip which is present in said station (24) so that a connection is formed between the chip and a test generator (26) for subjecting the chip to a test program. After finishing the test program the pins are connected to a load circuit (32) for loading an operating system into the chip.

Description

Method for treating chips which are mounted on a carrier tape
The invention relates to a method for treating chips, mounted on a carrier tape, the contact surfaces of said chips being free accessible, according to which method the tape is unwounded from a first reel, guided along one or more treating stations and wound onto a second reel, whereby one of said treating stations comprises contact pins which are pressed onto the contact surfaces of the chip which is present in said station so that a connection is formed between the chip and a test generator for subjecting the chip to a test program. Such a method may be part of a process for manufacturing chip pay cards, telephone cards, credit cards, etcetera. The chips, delivered from a chip manufacturing process, are mounted on a carrier tape having conductors through which the contact pins of the chips can be brought into contact with one or more bus lines extending over the whole length of the tape. Thereafter the tape is guided through a galvanising station whereby predetermined voltages are provided to the bus conductors such that a gold layer (or a layer of another suitable electrically conducting material) is deposited on the surface of the chip such that therewith the externally accessible contact surfaces are formed. At the end of this part of the process the tape is wound onto a reel. Thereafter a further part of the above-mentioned process is performed, whereby in a first station the conducting connections between the bus conductors and the chips are disturbed whereafter the tape is transported further to a second station in which the chip is tested.
Thereafter the tape is in general delivered to a separate receiving instance which takes care of programming the chips, i.e. loading the operating system into the memory and loading specific memory places with data for personalising the chip. For that purpose the tape is again wound off and guided along at least one programming station, where by means of pressed on pins a contact is realised between the inner part of the chip and the program generator. The generator takes care of loading the operating system into the chip so that the chip is ready to be personalised thereafter by loading personal data such as code numbers, etcetera, related specifically to a predetermined person. Before or after individualising the chip can be taken off from the carrier and mounted onto a card or similar device. An object of the invention is now to simplify the whole process carried out by the card producer such that the card producer only has to individualise the chip.
In agreement with said object the method is carried out such that after the test program the pins are connected with a load circuit for loading an operating system into the chip.
According to a further embodied development the inventive method is carried out such that after loading the operating system the pins are connected to a data source for loading specific data into the chip so that the chip becomes personalised.
The invention will now be explained in more detail with reference to the attached drawings.
Figure 1 illustrates schematically the applied method according to the prior art. Figure 2 illustrates schematically a method according to the invention. Figure 3 illustrates schematically a further developed method according to the invention. In figure 1 schematically the method according to the state of the art is presented.
The system which is applied according to the state of the art will be discussed with reference to figure 1. The whole method is subdivided into four stages, indicated with the phases A, B, C, and D. During phase A a wafer 10, supplied by a company which makes such wafers, is subdivided into the separate chips, whereby one of the chips is indicated by 12 in figure 1 and these separate chips are attached thereafter to the surface of a tape which is references by 14 in the figure. This tape is thereafter wound into a coil and ready for the treatments which will take place in phase B.
In phase B the tape 14 is unwound from the reel 16, guided along a number of treating stations and finally wound onto the reel 18. During the transfer from reel 16 to reel 18 the tape with the thereon mounted chips 12 will pass a number of stations, schematically indicated by 20 and 22, where the contact surfaces which thereafter should be accessible are manufactured, where the connections between the contact surfaces and the chips are realised and where the chip furthermore, with the exception of the contact surfaces, is completely encapsulated in a protecting material. All these steps are known as such and do not need any further explanation. With reference to the invention it is important that in phase B the tape also passes a station 24 in which the chip is subjected to a test process. The station 24 comprises a number of pins or other contacting elements which can be brought into contact with the now ready made contact surfaces. Because of that the generator 26 is able to carry out a test program by means of which the respective chip which is momentarily present in the station 24, will be tested. Eventually erroneously functioning chips are marked by the station 24 and thereafter the tape with the now tested chips is wound onto the reel 18. It is remarked that in phase A the chips as example are mounted in rows of two.
However, that is not necessary. Also one single row or more rows can be applied.
The reel 18 with the now tested tubes will in most cases be transported to another company where the chips will be loaded with programs and data and will be mounted onto telephone cards, pay cards, identification cards, etcetera. This company carries out the steps C and D whereby in step C the tape 14 with the now tested chips 12 is wound from the reel 18 and guided along a station 30 and wounded thereafter onto the reel 34. The station 30 is of the same type as station 24 and comprises pins or other contacting elements by means of which contact can be made with each of the chips on the tape 14 to load an operating system present in the generator 32 into the respective chip. At the end of this step C the tape 14, which is in the meantime wound onto the reel 34, carries chips which are both tested and loaded with an operating system.
Finally the step D has to be performed whereby the chips are taken off from the tape and are mounted onto a card or other carrier indicated by 36 in figure 1. The card 36 is guided through a station 38 where the card is personalised or individualised by loading the card with data in the form of code numbers, address data, etcetera, whereby the card gets a completely personalised or individualised character. The ultimately ready card is indicated by 36 A in figure 1.
The invention now proposes to simplify this whole process, at least partly in the way as is illustrated in figure 2. The simplified system according to the invention knows only three phases, i.e. A, B, and D. Phase A relates to the subdivision of the wafer in chips and mounting the chips on a tape 14. This phase is completely identical to phase A in figure 1. In phase B the tape 14 is first of all guided from the reel 16 along a number of treatment stations 20 and 22 in a manner identical to the manner described with reference to figure 1 and is finally guided along the station 24 where- after the tape is wound up onto the reel 18. In the station 24 through the thereto destined contact elements contact is made with the chip and a test program is performed by the generator 26 to establish correct functioning of the chip. At the end of this test program 26 the chip is loaded with an operating system which is derived from the source 32. The result thereof is the chips which are present onto the reel 18 are both tested and loaded with an operating system. As a result thereof the phase C indicated in figure 1 can be skipped and the reel 18 can be transferred to the company which finally makes the cards, etcetera through phase D of the system. Phase D is completely identical to phase D in figure 1. The end result of phase D is just as in figure 1 a collection of cards or other carriers 36A onto which chips are mounted which chips are completely loaded with an operating system and do comprise the necessary data to personalise the respective card 36A.
According to a preferred embodiment also phase D can be simplified by shifting a number of treatments carried out during said part of the operation to phase B. That is illustrated in figure 3. Phase A in figure 3 is again identical to phase A in figures 1 and 2 and does not need any further explanation.
In phase B the tape 14 is unwound from reel 16 and transported along stations 20, 22, and 24. Again in station 24 first of all the chips are tested through a program which is stored in the test generator 26. Thereafter the operating system is loaded from the generator 32 and following that data is supplied from a data source 40 so that therewith the respective chip is personalised or individualised. The result thereof is that the tape 14 on the reel 18 now comprises chips which are completely operational. In phase D in figure 3 it is only necessary to unwind tape 14 from reel 18, whereby the separate chips 12 are separated from the tape and are mounted onto a card or other carrier. In the figure this card is indicated by 36A to indicate that this is the completely operational ready card.

Claims

1. Method for treating chips, mounted on a carrier tape, the contact surfaces of said chips being free accessible, according to which method the tape is unwounded from a first reel, guided along one or more treating stations and wound onto a second reel, whereby one of said treating stations comprises contact pins which are pressed onto the contact surfaces of the chip which is present in said station so that a connection is formed between the chip and a test generator for subjecting the chip to a test program, characterised in that in that after finishing the test program the pins are connected to a load circuit for loading an operating system into the chip.
2. Method according to claim 1, characterised in that after loading the operating system the pins are connected to a data source for loading specific data into the chip so that the chip becomes personalised.
3. Apparatus for performing the method according to claim 1 or 2, characterised in that the apparatus comprises a first memory for storing the test program and a second memory for storing the operating system, both memories being connected to the same treatment station.
4. Apparatus according to claim 3, characterised in that the apparatus comprises a third memory for storing said data source, said third memory being connecting to the same treatment station as indicated in claim 3.
PCT/NL2001/000447 2000-06-13 2001-06-13 Method for treating chips which are mounted on a carrier tape WO2001097169A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU74671/01A AU7467101A (en) 2000-06-13 2001-06-13 Method for treating chips which are mounted on a carrier tape

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL1015422 2000-06-13
NL1015422 2000-06-13

Publications (1)

Publication Number Publication Date
WO2001097169A1 true WO2001097169A1 (en) 2001-12-20

Family

ID=19771530

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/NL2001/000447 WO2001097169A1 (en) 2000-06-13 2001-06-13 Method for treating chips which are mounted on a carrier tape

Country Status (2)

Country Link
AU (1) AU7467101A (en)
WO (1) WO2001097169A1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5684742A (en) * 1995-09-20 1997-11-04 International Business Machines Corporation Device and method for the simplified generation of tools for the initialization and personalization of and communication with a chip card
EP1011071A2 (en) * 1998-12-17 2000-06-21 Giesecke & Devrient GmbH Method and device for manufacturing customized chip cards

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5684742A (en) * 1995-09-20 1997-11-04 International Business Machines Corporation Device and method for the simplified generation of tools for the initialization and personalization of and communication with a chip card
EP1011071A2 (en) * 1998-12-17 2000-06-21 Giesecke & Devrient GmbH Method and device for manufacturing customized chip cards

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
LENDER F: "HERSTELLUNG, PERSONALISIERUNG UND VERSAND VON CHIPKARTEN - EIN UEBERBLICK", IT + TI INFORMATIONSTECHNIK UND TECHNISCHE INFORMATIK,DE,OLDENBOURG VERLAG. MUNCHEN, vol. 39, no. 5, 1 October 1997 (1997-10-01), pages 7 - 13, XP000702135, ISSN: 0944-2774 *
RANKL: "HANDBUCH DER CHIPKARTEN", SECOND EDITION, CARL HANSER VERLAG, PAGE(S) 322-337, DE, MUENCHEN, 1996, ISBN: 3-446-18893-2, XP002158725 *

Also Published As

Publication number Publication date
AU7467101A (en) 2001-12-24

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