WO2001095502A1 - Decodeur d'erreurs sans circuit de retour a concatenation - Google Patents

Decodeur d'erreurs sans circuit de retour a concatenation Download PDF

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Publication number
WO2001095502A1
WO2001095502A1 PCT/US2001/017021 US0117021W WO0195502A1 WO 2001095502 A1 WO2001095502 A1 WO 2001095502A1 US 0117021 W US0117021 W US 0117021W WO 0195502 A1 WO0195502 A1 WO 0195502A1
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Prior art keywords
blocks
error correcting
frame
codes
code
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PCT/US2001/017021
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English (en)
Inventor
Nandakumar Ramanujam
Bo Pedersen
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Tycom (Us) Inc.
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Publication date
Priority claimed from US09/589,215 external-priority patent/US6622277B1/en
Application filed by Tycom (Us) Inc. filed Critical Tycom (Us) Inc.
Priority to AU2001263442A priority Critical patent/AU2001263442A1/en
Publication of WO2001095502A1 publication Critical patent/WO2001095502A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2909—Product codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2927—Decoding strategies
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2948—Iterative decoding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0065—Serial concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes

Definitions

  • the invention relates to communications networks in general. More particularly, the invention relates to a method and apparatus to perform forward error correction in a network such as a long-haul communications network.
  • Long-haul communication networks are designed to carry information over relatively long distances, typically in the range of 600-10,000 kilometers.
  • Examples of long-haul communications systems include “undersea” or “submarine” systems that carry signals from one continent to another (e.g., North America to Europe). These systems are typically optical systems given the advantages in terms of capacity and reliability.
  • FEC Forward Error Correction
  • a transmitter receives a data stream and encodes the data stream using an FEC encoder.
  • the FEC encoder generates a code for a block of data, which is appended to the block of data.
  • the transmitter sends the encoded block of data over the network.
  • a receiver receives the encoded block of data and runs it through an FEC decoder.
  • the FEC decoder recovers the code and uses it to detect and correct any errors within the received block of data.
  • the use of FEC in a system provides "margin improvements" to the system.
  • the margin improvements can be used to increase amplifier spacing or increase system capacity.
  • WDM Wavelength Division Multiplexing
  • the margin improvement can be used to increase the bit rate of each WDM channel, or decrease the spacing between WDM channels thereby allowing more channels for a given amplifier bandwidth. Consequently, improvements in FEC techniques directly translate into increased capacity for long-haul communication systems. Accordingly, it can be appreciated that a substantial need exists for an enhanced FEC method and apparatus that improves margin requirements and therefore system capacity.
  • One embodiment of the invention comprises a method and apparatus to perform error correction.
  • a stream of data is encoded using concatenated error correcting codes.
  • the encoded data is communicated over a long-haul transmission system.
  • the encoded data is decoded using the codes and three levels of decoding.
  • FIG. 1 illustrates a system suitable for practicing one embodiment of the invention.
  • FIG. 2 is a block diagram of a FEC encoder in accordance with one embodiment of the invention.
  • FIG. 3 is a block diagram of a FEC decoder in accordance with one embodiment of the invention.
  • FIG. 4 is a block flow diagram of the operations performed by an FEC codec in accordance with one embodiment of the invention.
  • FIG. 5 is a block flow diagram of an encoding process in accordance with one embodiment of the invention.
  • FIG. 6 is a block flow diagram of a decoding process in accordance with one embodiment of the invention.
  • FIG. 7 is an illustration of how code blocks are packed into a frame in the encoding step.
  • FIG. 8 is an illustration of the interleaving process in accordance with one embodiment of the invention.
  • FIG. 9 is a plot of coding gains from three level and four level decoding in accordance with one embodiment of the invention.
  • the embodiments of the invention include a method and apparatus to increase coding gains in a long-haul communications system using concatenated error-correcting codes ("concatenated codes” or "product codes") in conjunction with a three level decoder.
  • Concatenated codes refer to the use of two or more levels of FEC coding. The performance improvement from concatenated codes arises from the fact that any residual errors from one level of decoding will be corrected in the second or third levels of decoding.
  • the coding gains for the embodiments of the invention are realized using concatenated codes and two levels of encoding to improve system performance.
  • Concatenated codes are particularly suitable for long-haul communications systems since they increase error correction capabilities with a slight incremental increase in redundancy.
  • RS concatenated codes are well-suited for long-haul communications systems since they tend to work well in "bursty" environments. Long-haul communications systems, especially undersea or submarine systems, tend to have more bursty traffic than other systems.
  • the coding gains for the embodiments of the invention are also realized using three levels of decoding to further improve system performance.
  • the two levels of encoding are matched at the receiving end by two levels of decoding.
  • the received data is processed by a third level of decoding that helps remove residual errors.
  • the additional error correction is gained without introducing any further redundancy to the transmitted stream of data. This is accomplished by correcting errors through the first two levels of decoding.
  • the received data is then repacked into the original received frames and sent through a third level of decoding using the same error correcting codes used for the first level of decoding.
  • the result is a coding gain of approximately 0.45 dB without the need to add signal redundancy.
  • error-correction codes suitable for use as concatenated codes.
  • Some examples include the linear and cyclic Hamming codes, the cyclic Bose-Chaudhuri-Hocquenghem (BCH) codes, the convolutional (Niterbi) codes, the cyclic Golay and Fire codes, and some newer codes such as the Turbo convolutional and product codes (TCC, TPC).
  • BCH Bose-Chaudhuri-Hocquenghem
  • Niterbi convolutional codes
  • TPC Turbo convolutional and product codes
  • the codes that are frequently used for application in high bit-rate communication systems are a set of cyclic, non-binary, block codes known as Reed-Solomon (RS) codes.
  • RS Reed-Solomon
  • the interleaver provides an FEC coding improvement corresponding to the depth of interleaving ("interleave depth") as discussed below.
  • One embodiment of the invention utilizes RS error correcting codes.
  • RS code word consists of a "block" of n "symbols", k of which represent the data, with the remaining (n - k) symbols representing the redundancy or check symbols.
  • check symbols are appended to the data symbols during the encoding step, and are used to uniquely detect and correct bit errors at the decoder, within the error-correction capability of the code.
  • the check symbols are stripped from the block, and the corrected data symbols are obtained.
  • the data symbols themselves are left unmodified during the encoding step, and it is for this reason that the RS code is referred to as a "systematic" code.
  • the rate of the RS code is the ratio of data symbols (or equivalently, bits) to code-word symbols (or bits).
  • RS codes The non-binary nature of block RS codes is manifest in the fact that a code symbol is not exactly a bit but rather it consists of several bits.
  • the typical symbol size m is 8 bits, or a standard byte.
  • RS error correcting schemes also include the use of a shortened RS code.
  • a shortened RS code is one where some of the data symbols are left unused.
  • the disadvantage of shortened codes, relative to full-length codes, is that they are rate-inefficient. Some practical considerations, such as the maximum number of code-word symbols having to be n* ( ⁇ n) in some cases, however, may actually require this form.
  • Shortened codes are implemented in both software and hardware by transforming a (n - s)l(k - s) RS code to a nlk code by padding s dummy symbols (e.g. 0) before encoding. At the decoder, this operation is reversed. After decoding, the padded symbols are stripped from the block.
  • Various procedures for encoding RS code words are well-known in the art, and therefore will not be further described herein.
  • concatenated codes provides relatively powerful error correction with relatively little additional processing power.
  • the overhead of a 2-level concatenated RS code can be calculated as (r ⁇ .r 2 ) _1 - 1, where ri and r 2 are the rates of the inner and outer codes, respectively.
  • the concatenated RS code itself can be represented in compact form as where the subscripts 1 and 2 represent the inner and outer codes, respectively.
  • Conventional FEC coding schemes e.g., RS 255/239
  • One embodiment of the invention uses a concatenated RS code that provides an additional coding gain of approximately 2 dB while providing and extra 16% redundancy bits (a total of 23%).
  • the embodiment uses an FEC encoder/decoder using a concatenated RS coding scheme with interleaving between the stages. More particularly, the FEC encoder/decoder utilizes a concatenated RS code of 223/207-255/223.
  • At least two important discoveries were significant in implementing concatenated codes in long-haul communication systems. The first was the recognition that concatenated codes having an inner code that is stronger (i.e., lower code rate) than the outer code (i.e., higher code rate) is particularly useful in such systems. The second was the recognition that the class of codes utilized for the concatenated code significantly impacted system design.
  • the first combination comprised a bit-based BCH inner code and a byte-based BCH outer code (referred to herein as "BCH-RS concatenated code").
  • BCH-RS concatenated code a bit-based BCH inner code and a byte-based BCH outer code
  • bit-based BCH codes are good for more uniformly distributed errors while RS codes are good for "bursty" channels.
  • the second combination comprised a pair of RS codes (referred to herein as "RS-RS concatenated code”).
  • Interleaving is a technique that is normally used to spread bursty errors among several consecutive code words. In this case an interleaver is inserted between the two concatenated codecs so that the inner and the outer decoding processes are statistically de- correlated. In general practice, the greater the interleave depth the better coding performance is gained.
  • the BCH-RS concatenated code and the RS-RS concatenated code each offers advantages according to the needs and constraints of a particular system.
  • the BCH-RS concatenation is good for channels that are both uniform and bursty in nature.
  • the RS-RS concatenation is particulary good for bursty environments. Consequently, the RS-RS concatenation is well-suited to undersea communications systems since undersea channels are more bursty in nature.
  • Another important aspect of implementing an enhanced FEC system concerns digital frame alignment and synchronization in a very noisy environment. This is an important implementation issue because the enhanced FEC must operate at BER values as high as 5x10 " .
  • the framing and synchronization strategies used in conventional FEC systems are inadequate for conditions where BER is greater than l ⁇
  • any reference in the specification to "one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention.
  • the appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
  • FIG. 1 is a block diagram of a long-haul communications network 100 comprising a communications transmitter/receiver ("transceiver") 102 and a transceiver 108 connected via a network 106.
  • Transceivers 102 and 108 each include a FEC encoder/decoder (“FEC codec”) 104 and a FEC codec 110, respectively.
  • FEC codec FEC encoder/decoder
  • long-haul communications network 100 is a conventional long-haul optically amplified undersea communication system with the optical transceivers modified to operate with a novel FEC codec performing in accordance with a novel concatenated FEC coding scheme and three levels of decoding.
  • Network 100 in general, and network 106 in particular, are designed to transport optical signals over distances greater than 600 kilometers.
  • FIG. 2 is a block diagram of a FEC encoder in accordance with one embodiment of the invention.
  • FIG. 2 illustrates a FEC encoder 200 representative of the structure performing the concatenated encoding function of FEC codecs 104 and/or 110.
  • FEC encoder 200 comprises a first encoder 204, an interleaver 206 and a second encoder 208.
  • First encoder 204 is also referred to herein as an "outer encoder.”
  • Second encoder 208 is also referred to herein as an "inner encoder.”
  • the operation of FEC encoder 200 will be discussed in more detail below with reference to FIGS. 4-6 and accompanying examples.
  • FIG. 3 is a block diagram of a FEC decoder in accordance with one embodiment of the invention.
  • FIG. 3 illustrates a FEC decoder 300 representative of the structure performing the concatenated decoding function of FEC codecs 104 and/or 110.
  • FEC decoder 300 comprises a first decoder 304, a deinterleaver 306, a second decoder 308, an interleaver 310, a third decoder 312 and a deinterleaver 314.
  • First decoder 304 and third decoder 312 are also referred to herein as “inner decoders.”
  • Second decoder 308 is also referred to herein as an “outer decoder.”
  • the operation of FEC decoder 300 will also be discussed in more detail below with reference to FIGS. 4-6 and accompanying examples.
  • FEC encoder 200 For purposes of clarity, the encoding structure and functionality (i.e., FEC encoder 200) is discussed separately from the decoding structure and functionality (i.e., FEC decoder 300). It can be appreciated, however, that both the encoding and decoding structure and functionality can be combined into a single FEC codec (e.g., FEC codecs 104 and 110) and still fall within the scope of the invention.
  • FIGS. 4-6 presented herein include a particular sequence of steps, it can be appreciated that the sequence of steps merely provides an example of how the general functionality described herein can be implemented. Further, each sequence of steps does not have to be executed in the order presented unless otherwise indicated.
  • FIG. 4 is a block flow diagram of the operations performed by an FEC encoder in accordance with one embodiment of the invention.
  • FEC encoder 202 performs the FEC encoding.
  • An example of an encoding process suitable for use in one embodiment of the invention is described in "A".
  • FIG. 4 illustrates a FEC process 400.
  • a stream of data is encoded using concatenated error correcting codes at step 402.
  • the encoded data is communicated over a long-haul transmissions system at step 404.
  • the long-haul transmission system communicates the encoded data at least 600 kilometers.
  • the encoded data is decoded using the error correcting codes and three levels of decoding at step 406.
  • FIG. 4 is a block flow diagram of the operations performed by an FEC encoder in accordance with one embodiment of the invention.
  • FEC encoder 202 performs the FEC encoding.
  • An example of an encoding process suitable for use in one embodiment of the invention is described in "A”.
  • FIG. 5 is a block flow diagram of an encoding process in accordance with one embodiment of the invention.
  • FIG. 5 illustrates an encoding process 500 that is representative of step 402 described with reference to FIG. 4.
  • the stream of data is packed into a first frame of first blocks at step 502.
  • the first frame is also referred to herein as an "unencoded outer frame.”
  • a first error correcting code is generated for each of the first blocks at step 504.
  • the first error correcting codes are appended to the first blocks to create a second frame of second blocks at step 506.
  • the second frame is also referred to herein as an "encoded inner frame.”
  • the second frame of second blocks is packed into a third frame of third blocks at step 508.
  • the third frame is also referred to herein as an "unencoded inner frame.”
  • a second error correcting code is generated for each of the third blocks at step 510.
  • the second error correcting codes are appended to the third blocks to create a fourth frame of fourth blocks at step 512.
  • the fourth frame is also referred to herein as an "encoded outer frame.”
  • the first frame, second frame, third frame and fourth frame each have a predetermined length. In one embodiment of the invention, the length of the second frame matches the length of the third frame. In this manner, no padding is required for the third frame. This decreases the latency associated with such padding hardware and techniques. In alternative embodiments, however, the length of the second frame is less than the length of said third frame. In such a case, the third frame is padded with padding symbols until the length of the third frame matches the length of the second frame. In this case, the increase in FEC coding efficiency is sufficient to compensate for the latency incurred by padding.
  • the embodiments of the invention use interleaving during the encoding and decoding process. More particularly, the interleaving operation occurs during the packing of the second blocks from the second frame into the third blocks of the third frame, and vice-versa. It can be appreciated, however, that the interleaving process can occur as a separate step from the packing process and still fall within the scope of the invention.
  • the interleaving operation can be either bit interleaving or byte interleaving.
  • the error correcting codes can be any code from a group comprising the linear and cyclic Hamming codes, the cyclic BCH codes, the convolutional Viterbi codes, the cyclic Golay and Fire codes, and some newer codes such as TCC and TPC.
  • the concatenated error correcting code pair may be separately represented as a first and second error correcting code, with the first error correcting code represented as x/y, and the second error correcting code represented as z/x.
  • the first error correcting code is a reed-solomon code. More particularly, the first error correcting code is a /207 reed-solomon error correcting code.
  • the second error correcting code is also a reed-solomon code.
  • the second error correcting code is a 255/ reed-solomon error correcting code.
  • the x is equal to 223 symbols.
  • This two level FEC coding results in a net coding gain of approximately 1.8 decibels while performing at a bit error rate of 10 "10 , without taking into account the coding gain given by the third level of decoding which is approximately 0.45 dB (as described more fully below).
  • This embodiment adds a redundancy percentage to the communicated encoded data of approximately 23 percent (including the third level of decoding).
  • the first error correcting code is one of a group comprising a bit based BCH code and a byte based BCH code.
  • the second error correcting is also one of a group comprising a bit based BCH code and a byte based BCH code. Further, the first error correcting code is stronger than the second error correcting code.
  • FIG. 6 is a block flow diagram of a decoding process in accordance with one embodiment of the invention.
  • FIG. 6 illustrates a decoding process 600.
  • the decoding process 600 has three levels of decoding.
  • the second error correcting codes and third blocks are recovered from the fourth blocks at step 602.
  • the second error correcting codes are used to correct errors for the third blocks at step 604.
  • the second blocks are unpacked from the third blocks at step 606.
  • the unpacking process also includes a deinterleaving operation described below.
  • the first error correcting codes and the first blocks are recovered from the second blocks at step 608.
  • the first error correcting codes are used to correct errors for the first blocks at step 610.
  • the first error codes are appended to the corrected first blocks to create a fifth frame of fifth blocks at step 612.
  • the fifth frame of fifth blocks is packed into a sixth frame of sixth blocks at step 614.
  • the packing process also includes an interleaving operation described below.
  • the second error correcting codes are used to correct errors for the sixth blocks at step 616.
  • the fifth blocks are unpacked from the corrected sixth blocks at step 618.
  • the unpacking process also includes the deinterleaving operation described below.
  • the first error correcting codes are removed from the fifth blocks to leave the received corrected data at step 620.
  • FIG. 7 is an illustration of how code blocks are packed into a frame in the encoding step.
  • first blocks 702 at the first (outer) encoding level are packed into a first frame 704 (i.e., the unencoded outer frame).
  • Check symbols 706 for first blocks 702 are generated by a first encoder (e.g., first encoder 204) of a FEC encoder (e.g., FEC codec 104 or FEC encoder 200).
  • Check symbols 706 are appended to first blocks 702 to form second blocks 708.
  • Second blocks 708 are packed into a second frame 710 (i.e., the encoded outer frame).
  • the bits (or bytes) from second blocks 708 are interleaved, and they are packed into third blocks 714 of a third frame 712 (i.e., unencoded inner frame).
  • second frame 710 and third frame 712 have the same length in terms of bits (or bytes), although the block size will likely vary between the two frames.
  • third frame 712 is required to be an integral number of third blocks 714, the size of which is different from that of second blocks 708.
  • the number of second blocks 708 and third blocks 714 per frame in each of these frames, respectively has to be chosen appropriately.
  • third frame 712 is padded or "stuffed" with dummy symbols until they are of equal length.
  • the padding process represents an increase in latency in a hardware implementation, or increased processing time in software.
  • the lengths of the frames are therefore chosen to minimize the number (or reduce to zero) of stuffed symbols, while at the same time keeping the number of second blocks per second frame to a minimum.
  • check symbols 716 are generated for third blocks 714 by a second encoder (e.g., second encoder 208) of an FEC encoder (e.g., FEC codec 104 or FEC encoder 200).
  • Check symbols 716 are appended to third blocks 714 to form a set of fourth blocks 718 of a fourth frame 720 (i.e., the encoded inner frame).
  • the encoded data stream is communicated to a transceiver (e.g., transceiver 108) for decoding by a FEC decoder (e.g., FEC codec 110 or FEC decoder 300).
  • FIG. 8 is an illustration of the interleaving process in accordance with one embodiment of the invention.
  • interleaving between the two encoding steps discussed with reference to FIG. 7 amounts to re-distributing the errors in bit-groupings or bytes that are either 1-bit or 8-bits long.
  • FIG. 8 illustrates an example of byte interleaving after second frame 710 is encoded. The improvement in error correction is directly related to the depth of interleaving. Using the example illustrated in FIG.
  • full byte (or symbol) interleaving requires that each of the 223 symbols in each second block 708 (i.e., the outer frame) is re-distributed into 223 different third blocks 714 (i.e., the inner frame).
  • the 223 symbols would require an interleave depth of 223 levels or 223 third blocks 714.
  • the interleave depth is 1784 levels.
  • steps 606 and 618 refer to an unpacking process that includes a deinterleaving process.
  • the deinterleaving process essentially reverses the interleaving process described with reference to FIG. 8.
  • the concatenated RS codes involve two independent levels of RS encoding, with an interleaving step in between them.
  • the decoding process includes three independent levels of RS decoding, with a deinterleaving step in between levels one and two, and an interleaving step and deinterleaving step between levels two and three.
  • transceiver 102 receives a stream of data for transmission over network 106.
  • Transceiver 102 utilizes FEC codec 104 to provide forward error correction to the data stream prior to transmission over network 106.
  • the encoded data stream is then transmitted over network 106 to transceiver 108.
  • Transceiver 108 receives the encoded data stream and begins the decoding process using FEC codec 110.
  • FEC codec 110 performs three levels of decoding.
  • the first level of decoding is performed by decoder 304 (i.e., inner decoder) of decoder 300 (that is part of FEC codec 110).
  • Decoder 304 receives the fourth frame of fourth blocks (i.e., the encoded inner frame) and recovers the second error correcting codes (i.e., inner codes) and third blocks (i.e., of the third frame) from the fourth blocks.
  • Decoder 304 corrects errors for the third blocks using the second error correcting codes.
  • the level of error correction is determined by the strength of the particular second error correcting codes.
  • the second level of decoding is performed by decoder 308 (i.e., outer decoder) of decoder 300.
  • the corrected third blocks are received by deinterleaver 306.
  • Deinterleaver 306 reverses the interleaving process used to pack the second blocks of the second frame into the third blocks of the third frame during the encoding process.
  • the unpacking and deinterleaving process produces the second blocks of the second frame from the third blocks.
  • Decoder 308 receives the second blocks and recovers the first error correcting codes (i.e., outer codes) and the first blocks (i.e., original data) from the second blocks. Decoder 308 corrects errors for the first blocks according to the particular strength of the first error correcting code.
  • the third level of decoding is performed by decoder 312 (i.e., inner decoder) of decoder 300.
  • the third level of decoding utilizes the second error correcting codes (i.e., inner codes) to correct errors in the corrected first and third blocks. This builds upon the basic premise of concatenated codes. To the extent the inner decoder cannot correct all the errors in the received information, the deinterleaver and the outer decoder may correct any unresolved errors. There may be an instance, depending on the strength of the inner and outer codes, that a number of errors remain despite the first two levels of decoding.
  • the corrected data (which may still have some uncorrected errors) can be sent through the inner decoder again in an attempt to correct any remaining errors.
  • additional coding gain could be achieved by resending the received information through the outer decoder again, this is typically not effective for several reasons.
  • the inner decoder typically utilizes the strongest error correcting code due to the advantages gained in terms of efficiency versus redundancy. Consequently, the greatest amount of additional error correction would come from the inner decoder.
  • the outer decoder provides relatively little, if any, additional coding gains, as demonstrated in FIG. 9.
  • FIG. 9 is a plot of coding gains from three level and four level decoding in accordance with one embodiment of the invention.
  • the third level decoding i.e., sending the data through the inner decoder again
  • fourth level decoding i.e., sending the data through the outer decoder again
  • both result in the same additional FEC gain of approximately 0.45 dB. Therefore, by sending the data through a fourth level of decoding would merely add latency without any appreciable coding gain for the system.
  • the third blocks must be reconstructed prior to sending them through the inner decoder again (e.g., decoder 312).
  • the first error codes are appended to the corrected first blocks to create a fifth frame of fifth blocks.
  • the fifth frame of fifth blocks equates to the reconstructed second frame of second blocks.
  • the fifth frame of fifth blocks is packed into a sixth frame of sixth blocks.
  • the sixth frame of sixth blocks equates to the reconstructed third frame of third blocks. This is accomplished by sending the fifth frame of fifth blocks through interleaver 310.
  • Decoder 312 receives the sixth blocks, uses the second error correcting codes to correct errors for the sixth blocks, and sends the corrected sixth blocks to deinterleaver 314.
  • Deinterleaver 313 unpacks and deinterleaves the fifth blocks from the corrected sixth blocks.
  • the first error correcting codes are removed from the fifth blocks to leave the outgoing data.
  • decoder 300 Although an additional decoder and deinterleaver is shown as part of decoder 300, it can be appreciated that the functions of decoder 312 and deinterleaver 314 may be accomplished using decoder 304 and deinterleaver 306, respectively, using the appropriate routing circuitry, and still fall within the scope of the invention. In another example, it can be appreciated that the functionality described for the embodiments of the invention may be implemented in hardware, software, or a combination of hardware and software, using well-known signal processing techniques.
  • the processor can be any type of processor capable of providing the speed and functionality required by the embodiments of the invention.
  • the processor could be a processor from the Pentium® family of processors made by Intel Corporation, or the family of processors made by Motorola.
  • Machine-readable media include any media capable of storing instructions adapted to be executed by a processor. Some examples of such media include, but are not limited to, read-only memory (ROM), random-access memory (RAM), programmable ROM, erasable programmable ROM, electronically erasable programmable ROM, dynamic RAM, magnetic disk (e.g., floppy disk and hard drive), optical disk (e.g., CD-ROM), and any other device that can store digital information.
  • ROM read-only memory
  • RAM random-access memory
  • programmable ROM erasable programmable ROM
  • electronically erasable programmable ROM dynamic RAM
  • magnetic disk e.g., floppy disk and hard drive
  • optical disk e.g., CD-ROM
  • the instructions are stored on the medium in a compressed and/or encrypted format.
  • the phrase "adapted to be executed by a processor" is meant to encompass instructions stored in a compressed and/or encrypted format, as well as instructions that have to be compiled or installed by an installer before being executed by the processor.
  • the processor and machine-readable medium may be part of a larger system that may contain various combinations of machine readable storage devices through various I/O controllers, which are accessible by the processor and which are capable of storing a combination of computer program instructions and data.
  • the embodiments were described using a communication network.
  • a communication network can utilize an infinite number of network devices configured in an infinite number of ways.
  • the communication network described herein is merely used by way of example, and is not meant to limit the scope of the invention.

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Abstract

L'invention porte sur un procédé et un appareil de correction d'erreurs selon lesquels on code un flux de données à l'aide de codes de correction à concaténation, puis transmet le flux codé via un système de transmission long distance, puis le décode à l'aide des codes en trois niveaux de décodage.
PCT/US2001/017021 2000-06-07 2001-05-25 Decodeur d'erreurs sans circuit de retour a concatenation WO2001095502A1 (fr)

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EP3124616A1 (fr) 2015-07-29 2017-02-01 F.I.S.- Fabbrica Italiana Sintetici S.p.A. Processus enzymatique pour la préparation de testostérone et d'esters de celle-ci
EP3958485A4 (fr) * 2019-05-15 2022-03-23 Huawei Technologies Co., Ltd. Procédé et dispositif de transmission de données

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EP3958485A4 (fr) * 2019-05-15 2022-03-23 Huawei Technologies Co., Ltd. Procédé et dispositif de transmission de données

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