WO2001095110A3 - Watchdog arrangement - Google Patents

Watchdog arrangement Download PDF

Info

Publication number
WO2001095110A3
WO2001095110A3 PCT/US2001/016750 US0116750W WO0195110A3 WO 2001095110 A3 WO2001095110 A3 WO 2001095110A3 US 0116750 W US0116750 W US 0116750W WO 0195110 A3 WO0195110 A3 WO 0195110A3
Authority
WO
WIPO (PCT)
Prior art keywords
watchdog
circuit
nmi
refreshed
reliable
Prior art date
Application number
PCT/US2001/016750
Other languages
French (fr)
Other versions
WO2001095110A2 (en
Inventor
Joseph Wayne Forler
Mark Alan Nierzwick
William John Testin
Original Assignee
Thomson Licensing Sa
Joseph Wayne Forler
Mark Alan Nierzwick
William John Testin
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing Sa, Joseph Wayne Forler, Mark Alan Nierzwick, William John Testin filed Critical Thomson Licensing Sa
Priority to AU2001264882A priority Critical patent/AU2001264882A1/en
Priority to JP2002502596A priority patent/JP2003536135A/en
Priority to DE10196261T priority patent/DE10196261T1/en
Priority to MXPA02011874A priority patent/MXPA02011874A/en
Publication of WO2001095110A2 publication Critical patent/WO2001095110A2/en
Publication of WO2001095110A3 publication Critical patent/WO2001095110A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N17/00—Diagnosis, testing or measuring for television systems or their details
    • H04N17/04—Diagnosis, testing or measuring for television systems or their details for receivers
    • H04N17/045—Self-contained testing apparatus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Health & Medical Sciences (AREA)
  • Biomedical Technology (AREA)
  • General Health & Medical Sciences (AREA)
  • Debugging And Monitoring (AREA)

Abstract

A watchdog arrangement advantageously provides systems, such as television signal processing apparatus, with a reliable, cost effective means by which to maintain consistent, stable operation. According to at least one embodiment, a hardware watchdog circuit receives regular pulses from a software timer in an integrated circuit (IC) to refresh itself. In the event that the watchdog circuit is not refreshed, it provides a predetermined logic signal to a non-maskable interrupt (NMI) terminal of the IC to generate a reset similar to what is generated by an internal IC watchdog.
PCT/US2001/016750 2000-06-02 2001-05-24 Watchdog arrangement WO2001095110A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU2001264882A AU2001264882A1 (en) 2000-06-02 2001-05-24 Watchdog arrangement
JP2002502596A JP2003536135A (en) 2000-06-02 2001-05-24 Watchdog timer circuit and method
DE10196261T DE10196261T1 (en) 2000-06-02 2001-05-24 supervision order
MXPA02011874A MXPA02011874A (en) 2000-06-02 2001-05-24 Watchdog arrangement.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US20885300P 2000-06-02 2000-06-02
US60/208,853 2000-06-02

Publications (2)

Publication Number Publication Date
WO2001095110A2 WO2001095110A2 (en) 2001-12-13
WO2001095110A3 true WO2001095110A3 (en) 2003-03-27

Family

ID=22776297

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/016750 WO2001095110A2 (en) 2000-06-02 2001-05-24 Watchdog arrangement

Country Status (7)

Country Link
JP (1) JP2003536135A (en)
KR (1) KR20030007843A (en)
CN (1) CN1488098A (en)
AU (1) AU2001264882A1 (en)
DE (1) DE10196261T1 (en)
MX (1) MXPA02011874A (en)
WO (1) WO2001095110A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005009955A1 (en) * 2005-03-04 2006-09-07 Bayerische Motoren Werke Ag Method for monitoring the operation of a computer device e.g., in motor vehicle, involves monitoring device with sensor set up for detecting event of computer device
CN100471244C (en) * 2007-02-09 2009-03-18 四川长虹电器股份有限公司 Circuit working state real-time monitoring method
US7774648B2 (en) 2007-05-02 2010-08-10 Honeywell International Inc. Microprocessor supervision in a special purpose computer system
US8698756B2 (en) 2007-11-06 2014-04-15 Stmicroelectronics Asia Pacific Pte Ltd. Interrupt reduction method in touch screen controller
ITMI20112406A1 (en) * 2011-12-28 2013-06-29 Datalogic Mobile S R L CUSTOMER TERMINAL AND SELF-SHOPPING SYSTEM

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4594685A (en) * 1983-06-24 1986-06-10 General Signal Corporation Watchdog timer
US4689766A (en) * 1984-11-16 1987-08-25 Zenith Electronics Corporation System for resetting the operation of a signal processing device upon the failure of accessng a predetermined memory location within a predetermined time interval
US4879647A (en) * 1985-06-11 1989-11-07 Nec Corporation Watchdog timer circuit suited for use in microcomputer
US4912708A (en) * 1988-03-22 1990-03-27 Siemens Transmission Systems, Inc. Automatic microprocessor fault recovery system
DE4113959A1 (en) * 1991-04-29 1992-11-05 Kloeckner Humboldt Deutz Ag MONITORING DEVICE
WO1998007089A1 (en) * 1996-08-12 1998-02-19 Papst-Motoren Gmbh & Co. Kg Process and device for monitoring a microprocessor
US6012154A (en) * 1997-09-18 2000-01-04 Intel Corporation Method and apparatus for detecting and recovering from computer system malfunction

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4594685A (en) * 1983-06-24 1986-06-10 General Signal Corporation Watchdog timer
US4689766A (en) * 1984-11-16 1987-08-25 Zenith Electronics Corporation System for resetting the operation of a signal processing device upon the failure of accessng a predetermined memory location within a predetermined time interval
US4879647A (en) * 1985-06-11 1989-11-07 Nec Corporation Watchdog timer circuit suited for use in microcomputer
US4912708A (en) * 1988-03-22 1990-03-27 Siemens Transmission Systems, Inc. Automatic microprocessor fault recovery system
DE4113959A1 (en) * 1991-04-29 1992-11-05 Kloeckner Humboldt Deutz Ag MONITORING DEVICE
WO1998007089A1 (en) * 1996-08-12 1998-02-19 Papst-Motoren Gmbh & Co. Kg Process and device for monitoring a microprocessor
US6012154A (en) * 1997-09-18 2000-01-04 Intel Corporation Method and apparatus for detecting and recovering from computer system malfunction

Also Published As

Publication number Publication date
DE10196261T1 (en) 2003-06-12
MXPA02011874A (en) 2003-04-10
JP2003536135A (en) 2003-12-02
AU2001264882A1 (en) 2001-12-17
KR20030007843A (en) 2003-01-23
CN1488098A (en) 2004-04-07
WO2001095110A2 (en) 2001-12-13

Similar Documents

Publication Publication Date Title
US20160335149A1 (en) Peripheral Watchdog Timer
WO2001095110A3 (en) Watchdog arrangement
CN111045505A (en) Time delay reset device and method of system on chip
KR970020745A (en) Starter of crew protection
WO2005022387A3 (en) Circuit arrangement and method for supporting and monitoring a microcontroller
US9411755B2 (en) Software debouncing and noise filtering modules for interrupts
US5063355A (en) Timer circuit
GB2310514A (en) Watchdog circuit
KR20070012351A (en) Electronic circuit arrangement for detecting a failing clock
CN111192542B (en) Static electricity eliminating device and method for driving chip and display device
US20080059666A1 (en) Microcontroller and debugging method
WO2004034172A3 (en) Method for synchronizing events, particularly for processors of fault-tolerant systems
CN108073489B (en) Method for ensuring operation of calculator
CN101739021B (en) Equipment self-inspection control device
KR100628109B1 (en) Apparatus and Method of Watch-Dog of Camera module for Handhelds device using Hardware logic
US5349387A (en) Apparatus for detecting polarity of an input signal
JPH02187856A (en) Resetting method for multi-central arithmetic unit system
US11086622B2 (en) Method for managing an update of a microcode within a processing unit
JP3025318U (en) Reset signal generator
JP3016852B2 (en) Data processing device
KR100459225B1 (en) Processor Having Frame Structure
KR940008853B1 (en) Watch-dog timing circuit
JPH0973404A (en) Watchdog timer circuit
JPH02252034A (en) Watchdog timer setting system
SU382089A1 (en) DEVICE FOR INTERRUPTION OF PROGRAMS

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 10296898

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: PA/a/2002/011874

Country of ref document: MX

WWE Wipo information: entry into national phase

Ref document number: 018106285

Country of ref document: CN

Ref document number: 1020027016432

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 1020027016432

Country of ref document: KR

RET De translation (de og part 6b)

Ref document number: 10196261

Country of ref document: DE

Date of ref document: 20030612

Kind code of ref document: P

WWE Wipo information: entry into national phase

Ref document number: 10196261

Country of ref document: DE

122 Ep: pct application non-entry in european phase