WO2001093335A1

WO2001093335A1 - Component with a transistor and method for production thereof

Info

Publication number: WO2001093335A1
Application number: PCT/DE2001/002064
Authority: WO
Inventors: Claus Dahl; Reinhard Jurk; Michael Röhner; Alexander Gschwandtner; Werner Robl; Roland Thewes
Original assignee: Infineon Technologies Ag
Priority date: 2000-05-31
Filing date: 2001-05-31
Publication date: 2001-12-06
Also published as: DE10027914B4; DE10027914A1

Abstract

The invention relates to a component with a transistor and method for production thereof. According to the invention, the cut-off voltage drift of PMOS transistors may be reduced, whereby a getter layer (14) with a thickness of at least 40 nm is provided in conductor tracks above the PMOS transistor.

Description

description

Component with a transistor and method for its production

The invention relates to a component with a transistor and a method for its production.

A component with a transistor is known from DE 198 03 665 AI. The transistor is a field effect transistor for analog circuit functions with at least one source region, at least one drain region, a channel region arranged between the source region and the drain region, a gate dielectric arranged above the channel region and a gate electrode arranged above the gate dielectric. The known transistor is characterized in that foreign atoms from the group of halogens are present in the gate dielectric.

By introducing free atoms from the group of halogens into the gate dielectric, the degradation by the "bias temperature stress effect" (BTS effect) is significantly reduced. This effect occurs when a negative gate-source voltage is applied to MOS field-effect transistors with p-channel. This is the case if the component with the integrated circuit is inactive when the supply voltage is present.

The degradation due to the BTS effect increases exponentially with the temperature and is particularly noticeable through a disadvantageous change in the threshold voltage. Because with analog or mixed analog-digital circuits some of the PMOS transistors are _often operated beitspunkt in one operation, which is very sensitive to changes in the threshold voltage of the transistor. This operating point is characterized by a gate voltage which is only slightly above the threshold voltage of the PMOS transistor. Accordingly, even small fluctuations in the threshold voltage of the MOS field-effect transistor lead to relatively large fluctuations in the current that flows through the transistor at the operating point. Since typical applications for analog circuit functions require a current that is as well-defined as possible through the respective transistor, such fluctuations in the threshold voltage of the transistor cannot generally be tolerated. In order to solve the problem of drift in analog circuits caused by the BTS effect, it has been proposed to incorporate foreign atoms from the group of halogens into the gate dielectric.

A disadvantage of the known component, however, is that the introduction of the atoms from the group of halogens into the gate dielectric requires additional process steps.

Based on this prior art, the object of the invention is to create a component with a transistor in which the degradation of the threshold voltage due to the BTS effect is reduced by simple process engineering measures.

This object is achieved by a component in which a layer associated with the transistor is produced from a material which is suitable for gettering substances which are harmful to the functioning of the transistor.

This object is further achieved by a method in which a layer associated with the transistor is formed, by which substances harmful to the functioning of the transistor are obtained.

In this context, a “layer associated with the transistor” is understood to mean the region of a layer that is closest to the respective transistor of the transistors arranged on the same level. For example, the part of a conductor track that falls under this definition the respective transistor is closer than an adjacent transistor.

"Gettering" means taking up and storing substances from the environment. This presupposes that the material has a higher ability to record and store than the neighboring material.

Since a layer associated with the respective transistor has the ability to getter substances that are harmful to the function of the transistor, such substances are kept away from the transistor during manufacture and operation. It is assumed that the concentration of hydrogen in the region of the transistor is particularly important for the BTS effect. It has now been shown that the degradation of the transistor parameters can be reduced by the BTS effect if areas are provided in the vicinity of the transistor which are made of a hydrogen-absorbing material.

In a preferred exemplary embodiment, the transistor is a field-effect transistor with a p-channel and the associated layer is part of a conductor track. In particular, the channel region of the transistor is made of n-doped silicon and the gate dielectric is made of SiÜ2. Titanium with a layer thickness of at least 40 nm is used for the associated layer.

It is sufficient to provide a layer of titanium of sufficient thickness in conductor tracks above the transistor in order to significantly lower the hydrogen content in the region of the transistor. It is therefore not necessary to provide titanium in the area above the transistor in order to significantly reduce the degradation due to the BTS effect. In another embodiment, a diffusion barrier made of TiN is arranged between the associated layer on the titanium and a conductor track core made of AlCu.

The diffusion barrier prevents the associated layer from alloying with the conductor core during manufacture. The diffusion barrier therefore ensures a sufficient thickness of the associated layer even after completion of the manufacturing process.

Further expedient refinements of the invention are the subject of the dependent claims.

An exemplary embodiment of the invention is explained in detail below with reference to the accompanying drawing. Show it:

1 shows a cross section through a PMOS transistor with an overlying conductor track;

FIG. 2 shows a transmission characteristic of the PMOS

Transistor of Figure 1;

FIGS. 3 to 5 representations of the grid along the interface of a channel region and a gate dielectric;

Figure 6 shows a cross section through an advantageous embodiment of a conductor track;

Figure 7 is a diagram showing the development of the BTS

Effect shows; and

FIGS. 8 and 9 are diagrams showing the dependence of the gate voltage drift on the thickness of a getter layer made of titanium. FIG. 1 shows a PMOS transistor 1 (p-channel MOS field-effect transistor) which has a well 3 formed in a substrate 2. In the present case, the substrate 2 is p-doped, while the well 3 is n-doped. The tub 3 is delimited by insulating layers 4 along the top of the substrate 2. The insulating layers 4 are for example made of Si0 ₂ (LOCOS method). The PMOS transistor 1 further comprises a source region 5 and a drain region 6 with a channel region 7 in between. The channel region 7 is covered by a gate dielectric 8 made of silicon oxide. Above the gate dielectric 8 there is a gate electrode 10 delimited laterally by spacers 9. Contacts 11 are connected to the source region 5, the drain region 6 and the gate electrode 10, of which only the contact 11 connected to the source region 5 is shown in FIG. The contacts 11 lead through an interlayer dielectric 12 to conductor tracks 13 which are provided with a getter layer 14 towards the interlayer dielectric 12. The conductor track 13 itself is made of AlCu. The getter layer 14 is made of titanium.

FIG. 2 shows transmission characteristics of the PMOS transistor 1 from FIG. 1. A solid line represents the original transmission characteristic 15 of the PMOS transistor 1. A shifted transmission characteristic 16 that results after a certain time is indicated in FIG. 2 by a dashed line. The shifting of the transmission characteristic 15 is based, among other things, on the degradation of the transistor parameters due to the BTS effect ("bias temperature stress effect"). A negative gate-source voltage is a prerequisite for this effect. Such an operating point of the PMOS transistor occurs particularly when the component with the integrated circuit is in the so-called power-down mode. In this case, the source region 5 and the drain region 6 are each at ground potential, while a negative gate voltage is present at the gate electrode 10. Over time, they form along the Interface between the channel region 7 and the gate dielectric 8 from surface charges that shift the transmission characteristic 15. This leads to a threshold voltage drift ΔVra.

The physical causes of the BTS effect are not fully understood. A number of models have been developed to explain the BTS effect. (C.E. Bhat et al. "Mechanism of negative-bias-temperature instability", I.

Appl. Phys. 79 (3), pp. 1712-1720 (1991); N. Bhat et al. , "Blas temperature instability in hydrogenated thin-film transistors", IEEE Transactions on Electron Devices (1997) vol. 44, no. 7, p.1102-1108). One of these models will be illustrated below with reference to FIGS. 3 to 5. FIG. 3 shows a section of the grid along the interface between the channel region 7 and the gate dielectric 8. Silicon atoms 17 are indicated by black circles. Large white circles represent oxygen atoms 18. Due to the different lattice constants of the silicon in the channel region 7 and the SiO ₂ in the gate dielectric 8, unsaturated bonds, so-called dangling bonds, are formed along the interface, to which hydrogen atoms 19 are attached, which are shown in FIG. 3 are represented by small white circles.

The Si-H bonds are broken under the influence of the negative gate-source voltage. As shown in FIG. 4, this results in charge-neutral interface states 20, surface charges 21 and an OH group bonded to a silicon atom 17 along the interface, as well as a free electron (not shown in FIG. 4).

As shown in FIG. 5, the OH group diffuses into the interior of the gate dielectric 8. This results in stable interface states 20. The surface charges 21 lead finally to the shift in the original transmission characteristic 15.

It has been found that the shift in the original transmission characteristic 15 turns out to be significantly smaller if a layer absorbing and storing hydrogen is present in the region above the PMOS transistor 1. Titanium, for example, is suitable as the material for such a getter layer 14.

FIG. 6 shows a cross section through the conductor track 13. In addition to the actual getter layer 14 made of titanium, which is at least 40 nm thick, the conductor track 13 comprises a diffusion barrier 22 made of 50 nm thick TiN. A thin intermediate layer 23 made of Ti can be applied to this diffusion barrier 22 in order to improve the electromigration properties. This is completely converted into TiAl ₃ by later process steps. The diffusion barrier 22 must have at least the thickness above which it is ensured that there is no diffusion between the conductor tracks 24 made of AlCu and the getter layer 14. This density is 25 nm. Depending on the process control, the thickness of the intermediate layer 23 can vary. The conductor core 24 consists of 400 nm thick AlCu and represents the actual current-carrying layer of the conductor 13. This is followed by an anti-reflection layer 25, which is required for structuring the conductor 13.

FIG. 7 shows the dependence of the threshold voltage drift ΔVra as a function of time. The measurement points entered with diamonds refer to a PMOS transistor whose getter layer has a thickness of 20 nm and is made of titanium. The measurement points shown with triangles in the diagram in FIG. 7 relate to PMOS transistors 1 with the cross section through the conductor path 13 shown in FIG. 6. The measurements were carried out in such a way that the PMOS transistors each have a time shown in the diagram Gate-source voltage of -6.5 volts at a temperature of 125 ° Celsius. FIG. 7 clearly shows that the PMOS transistors 1 with a getter layer made of 40 nm titanium and a diffusion barrier 22 made of 50 nm titanium have a threshold voltage drift ΔVra which is lower by a factor of 5.

The relationship between the threshold voltage drift ΔVm and the thickness of the getter layer 14 is shown in FIG. 8 for a PMOS transistor, the getter layer 14 of which is in direct contact with the conductor core 24. In each case, the threshold voltage drift AVm is entered in the diagram in FIG. 8, which results when the PMOS transistors are exposed to a gate-source voltage of -6.5 V and a temperature of 125 ° C. for 1000 seconds. It can be seen from FIG. 8 that the threshold voltage drift ΔVra decreases as the getter layer 14 increases in thickness. The decrease, however, slows down if the layer thickness of the getter layer 14 is above 80 nm, in particular 110 nm.

FIG. 9 finally shows a diagram which shows the dependence of the threshold voltage drift ΔVm as a function of the thickness of the getter layer 14 of the conductor track 13 shown in FIG. 6. Here too, the PMOS transistors 1 were exposed to a gate-source voltage of -6.5 volts at a temperature of 125 ° C. for 1000 seconds. The comparison with the diagram in FIG. 8 shows that the threshold voltage drift AVT is approximately 2 to 5 times smaller. The diffusion barrier 22 contributes to this, which prevents the getter layer 14 from reacting with the conductor track core 24 and being thinned out during manufacture. The getter layer 14 is advantageously at least 25 mm, preferably at least 40 mm thick.

FIGS. 8 and 9 make it clear that either in a typical CMOS process the getter layer 14 must have a thickness of at least 50 nm or that the diffusion barrier 22 between the getter layer 14 and the conductor core 24 must be added to ensure a sufficient thickness of the getter layer 14.

It should be noted that the measures described here can be combined with the known implantation of foreign atoms from the group of halogens into the gate dielectric. This further reduces the threshold voltage drift ΔVrw.

To manufacture the PMOS transistor 1, the actual PMOS transistor 1 is first formed in the substrate 2. Under certain circumstances, foreign atoms from the group of halogens can be implanted in the gate dielectric 8. A base layer, not shown in FIG. 1, made of 40 nm thick titanium and sufficiently thick TiN is then sputtered on. The contacts 11 are then filled with tungsten by means of CVD. The excess tungsten is ground back by chemical mechanical polishing, the base layer being removed. The getter layer 14 made of 40 nm thick titanium and the diffusion barrier 22 made of sufficiently thick TiN are then sputtered on. Here, getter layer 14 teases the excess hydrogen to reduce the BTS effect. The intermediate layer 23 is then sputtered onto the diffusion barrier 22 in order to improve the electromigration properties and a 400 nm thick AICu layer as the conductor track core 24. The process is completed by sputtering on the anti-reflection layer 25.

If further metal levels are provided, vias are formed accordingly between the conductor tracks 13 and the subsequent conductor tracks, not shown in FIG. 1. The downstream conductor tracks are also advantageously provided with 40 nm getter layers made of titanium, which are separated from the conductor core by diffusion barriers made of TiN. LIST OF REFERENCE NUMBERS

1 PMOS transistor

2 substrate

3 tub

4 insulating layer

5 source area

6 drain area

7 channel area

8 gate dielectric

9 spacers

10 gate electrode

11 Via

12 interlayer dielectric

13 conductor tracks

14 getter layer

15 original transmission characteristic

16 shifted transmission characteristic

17 silicon atoms

18 oxygen atoms

19 hydrogen atoms

20 interface state

21 interfacial charge

22 diffusion barrier

23 intermediate layer

24 conductor track core

25 anti-reflective layer

Claims

claims

1. Integrated component with a transistor

(1), so that a layer (14) associated with the transistor (1) is made of a material that is suitable for gettering substances that are harmful to the function of the transistor (1).

2. Component according to claim 1, characterized in that the transistor (1) has a source region (5), a drain region (6), a channel region (7) arranged between the source region (5) and drain region (6), a on the channel region (7 ) adjacent gate dielectric (8) and a gate electrode (10) adjacent to the gate dielectric (8).

3. Component according to claim 1 or 2, characterized in that the channel region (7) made of silicon and the gate dielectric (8) is made of Si0 ₂ .

4. The component as claimed in one of claims 1 to 3, so that the associated layer is a layer (14) of a conductor track (13).

5. Component according to one of claims 1 to 4, d a d u r c h g e k e n n z e i c h n e t that the associated layer (14) is made of titanium.

6. The component according to claim 5, characterized in that the associated layer (14) has a thickness of at least 25 nm.

7. The component according to one of claims 1 to 6, so that the conductor track (13) contains a conductor track core (24) made of an alloy based on at least one of the elements from the group of Al and Cu.

8. The component according to any one of claims 1 to 7, that a diffusion barrier (22) adjoins the associated layer (14).

9. The component according to claim 7 and 8, so that a diffusion barrier (22) made of TiN is arranged between the conductor track core (24) and the layer associated with the transistor (1).

10. A method for producing an integrated component with a transistor (1), so that a layer (14) associated with the transistor (1) is formed, through which substances harmful to the function of the transistor (1) can be obtained.

11. The method according to claim 10, since you rchgek characterized in that the transistor (1) is designed as a field effect transistor, with a source region (5), a drain region (6), one between the source region (5) and drain region (6). arranged channel area (7) with a gate dielectric (8) adjacent to the channel area (7) and a gate electrode (10) adjoining the gate dielectric (8).

12. The method according to claim 10 or 11, characterized in that the channel region (7) made of silicon and the gate dielectric (8) made of Si0 ₂ , Si ₃ N4, SiO _x N _y with 0 <x <2 and 3y = 4-2x or other metal oxides.

13. The method according to any one of claims 10 to 12, so that the associated layer is formed by a layer of a conductor track (13) arranged downstream of the transistor (1).

14. The method according to any one of claims 10 to 13, that the layer (14) associated with the transistor (1) is made of titanium.

15. The method according to claim 14, d a d u r c h g e k e n n z e i c hn e t that the associated layer (14) with a thickness of at least

40 nm is produced.

16. The method according to any one of claims 10 to 15, so that the conductor track (13) has a conductor track core (24) which is made of an alloy based on at least one element from the group AI and Cu.

17. The method according to any one of claims 10 to 16, so that a diffusion barrier (22) adjoining the associated layer (14) is formed.

18. The method according to claim 16 and 17, so that the diffusion barrier (22) is made of TiN and is arranged between the associated (14) layer and the conductor track core (24).