WO2001090828A2 - Systeme de transmission de signaux sur ligne d'alimentation en courant alternatif - Google Patents

Systeme de transmission de signaux sur ligne d'alimentation en courant alternatif Download PDF

Info

Publication number
WO2001090828A2
WO2001090828A2 PCT/CA2001/000671 CA0100671W WO0190828A2 WO 2001090828 A2 WO2001090828 A2 WO 2001090828A2 CA 0100671 W CA0100671 W CA 0100671W WO 0190828 A2 WO0190828 A2 WO 0190828A2
Authority
WO
WIPO (PCT)
Prior art keywords
signal
control signal
power
voltage dropping
control
Prior art date
Application number
PCT/CA2001/000671
Other languages
English (en)
Other versions
WO2001090828A3 (fr
Inventor
Alexei Bogdan
Marc Oliver Hoffknecht
Original Assignee
Lumion Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lumion Corporation filed Critical Lumion Corporation
Priority to AU2001258119A priority Critical patent/AU2001258119A1/en
Publication of WO2001090828A2 publication Critical patent/WO2001090828A2/fr
Publication of WO2001090828A3 publication Critical patent/WO2001090828A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/54—Systems for transmission via power distribution lines
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/21—Pc I-O input output
    • G05B2219/21125—Digital value of analog signals depends on range between signal and threshold
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/25—Pc structure of the system
    • G05B2219/25132—Superposition data signals on power lines for actuators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2203/00—Indexing scheme relating to line transmission systems
    • H04B2203/54—Aspects of powerline communications not already covered by H04B3/54 and its subgroups
    • H04B2203/5404—Methods of transmitting or receiving signals via power distribution lines
    • H04B2203/5412—Methods of transmitting or receiving signals via power distribution lines by modofying wave form of the power source
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2203/00—Indexing scheme relating to line transmission systems
    • H04B2203/54—Aspects of powerline communications not already covered by H04B3/54 and its subgroups
    • H04B2203/5404—Methods of transmitting or receiving signals via power distribution lines
    • H04B2203/542—Methods of transmitting or receiving signals via power distribution lines using zero crossing information

Definitions

  • This invention relates to signalling systems used to control devices powered by alternating current power supplies. More particularly, this invention relates to a signalling system which may be used to transmit a digital signal to a receiver which controls the power supply to a device connected to an AC power line.
  • HVAC heating, ventilation and air conditioning systems
  • security and other needs.
  • a large office tower may have dozens of tenants, each with different requirements with respect to the times at which different services are to be switched into different configurations.
  • a particular tenant may require that, during office hours, all lights be on, the HVAC system be set for full ventilation and air conditioning to 22° C and security system be disarmed.
  • the same tenant may require that during evening periods, only hallway lighting be on, the HVAC system be set for 25% ventilation and the air conditioning to 26° C and that the security system be armed to allow any employee to enter with a pass card.
  • the tenant may require that only minimal lighting required for safety be on, the HVAC system be off and the security system permit only specified persons to enter with a pass card.
  • the tenant may require that a manual override must be available to change any of these settings at any time.
  • Prior art signalling systems which transmit data over AC power lines using a high frequency control signal are also known. These systems transmit their high frequency control signal by adding it to the AC power signal with the result that the high frequency control signal propagates towards both the load and supply sides of the circuit (relative to the transmitter). High power filters are required to remove the high frequency control signal from the supply side of the circuit, or alternatively, only a single high frequency data signal may be transmitted in all circuits that are coupled together. [08] Accordingly, there is a need for a signalling system which can transmit a control signal across an AC power transmission line to a receiver coupled to a load without the use of signal or control wires.
  • the present invention provides a signalling system for controlling loads on an AC power line.
  • a transmitter receives an AC power signal and modifies it by adding a control signal.
  • the modified power signal is received by one or more receivers connected on the power line.
  • Each of the receivers decodes the control signal from the modified power signal and provides a digital bit stream corresponding to the control signal to a signal processing block, which in turn controls the operation of a device or system connected to it.
  • the control signal affects positive and negative half waves of the AC power signal equally to reduce the DC component added into the modified power signal as a result of the super-addition of the control signal.
  • the AC power signal is left unaffected to indicate a 'low' or logical '0' data bit.
  • the AC power signal is attenuated in a controlled manner to indicate a 'high' or logical data bit.
  • the control signal is essentially a square wave signal which attenuates the amplitude of the AC power signal. Each cycle of the modified power signal is used to encode one data bit.
  • an active wave shaping circuit is used in the transmitter, allowing a control signal of almost any shape to be generated.
  • This transmitter may be used to generate high frequency signals as part of the control signal. Such high frequency frequency signals may be easier to detect reliably and may be used to encode a high frequency data stream.
  • Another embodiment of a transmitter may be coupled in a one signal mode, in which it can be used to provide a precisely balanced control signal on an AC power line or a two signal mode in which it can provide two independent and generally balanced control signals to two independent devices on two AC power lines.
  • This embodiment includes a pair of control signal generation sub-stages, which may be coupled in series in the one signal mode.
  • the two control signal generation sub- stages are controlled by a single control signal control block in the one signal mode and may be controlled by a single control signal control block in the two signal mode.
  • the receiver determines whether a particular cycle of the modified power signal encodes a '0' or '1 ' bit by calculating the area of the positive half wave of the cycle.
  • the receiver includes an asymmetric filter which affects the positive and negative half waves of the modified power signal differentially.
  • This filtered signal is recitified, providing a rectified signal with a series of pulses corresponding to the positive half waves of the modified power signal.
  • the corresponding pulse of the rectified signal exhibits a time shift in its rising and falling portions. Due to the asymmetric filter, the rising edge of the pulse exhibits a lagging time shift but the falling edge exhibits a leading time shift.
  • the magnitude of the rectified signal is compared to a reference threshold to determine whether the time shift exists in the reference signal, and accordingly, if the cycle was encoded as a '1' bit. If not, then it is known to be have encoded a '0' bit.
  • the second embodiment is modified by comparing the falling edge of the rectified signal to a second voltage threshold, which is selected to be at a voltage that is not affected regardless of whether a '0' or '1' bit was transmitted.
  • the time at which the rising and falling edges cross the first threshold is compared to the time at which the falling edge crosses the second threshold, thereby identifying separately whether the rising edge has been time shifted and whether the falling edge has been time shifted. This allows two data bits to be transmitted per cycle of the modified power signal, be selecting an appropriate control signal.
  • Figure 1 is a block diagram of a circuit configured with a first embodiment of a signalling system according to the present invention
  • Figure 2 is a block diagram of a transmitter of the signalling system of Figure 1 ;
  • Figure 3 is a schematic diagram of a DC power supply circuit of the transmitter of Figure 2;
  • Figure 4 is a schematic diagram of a control signal control block of the transmitter of Figure 2;
  • Figure 5a illustrates an AC power signal produced by an AC power source of the circuit of Figure 1 ;
  • Figure 5b illustrates a synchronization signal produced in the control signal control block of Figure 4.
  • Figure 6a illustrates an input signal produced by a first switch of the control signal control block of Figure 4
  • Figure 6b illustrates a data signal produced by the control signal control block of Figure 4 in response to the input signal of Figure 6a;
  • Figure 7a illustrates an input signal produced by a second switch of the control signal control block of Figure 4.
  • Figure 7b illustrates a data signal produced by the control signal control block of Figure 4 in response to the input signal of Figure 7a;
  • Figure 8a illustrates an input signal produced by a third switch of the control signal control block of Figure 4.
  • Figure 8b illustrates a data signal produced by the control signal control block of Figure 4 in response to the input signal of Figure 8a
  • Figure 9 is a schematic diagram of a control signal generation block of the transmitter of Figure 2;
  • Figure 10a illustrates the AC power signal of Figure 5
  • Figure 10b illustrates the data signal of Figure 6b
  • Figure 10c illustrates a control signal produced in the control signal generation block of Figure 9 in response to the data signal of Figure 10b
  • Figure 10d illustrates a modified power signal produced by the control signal generation block of Figure 9 in response to the data signal of Figure 10b;
  • Figure 11 is a schematic diagram of a second control signal generation block which may be used with the transmitter of Figure 2
  • Figure 12 is a schematic diagram of a second control signal control block and a third control signal generation block which may be used with the transmitter of Figure 2;
  • Figure 13a illustrates a pulse width modulated signal generated by the control signal control block of Figure 12
  • Figure 13b illustrates a control signal produced in the control signal generation block of Figure 12 in response to the pulse width modulated signal of Figure 13a;
  • Figure 13c illustrates a modified power signal produced by the control signal generation block of Figure 12 in response to the pulse width modulated signal of Figure 13a;
  • Figure 14 illustrates the modified power signal of Figure 13c in greater detail
  • Figure 15a illustrates the AC power signal of Figure 5
  • Figure 15b illustrates another control signal
  • Figure 15c illustrates a modified power signal which may be produced in response to the control signal of Figure 15b;
  • Figure 16 is a block diagram of a receiver of the signalling system of Figure 1 ;
  • Figure 17 is a schematic diagram of a control signal detection block of the receiver of Figure 16;
  • Figure 18a illustrates the modified power signal of Figure 10d
  • Figure 18b illustrates a filtered signal produced in the control signal detection block of Figure 17 in response to the modified power signal of Figure 18a;
  • Figure 18c illustrates a data stream produced by the control signal detection block of Figure 17 in response to the modified power signal of Figure 18a;
  • Figure 19 is a schematic diagram of a control signal conversion block of Figure 16;
  • Figure 20 is a block diagram of a second receiver which may be used with the transmitter of Figure 2;
  • Figure 21 is a schematic diagram of a control signal detection block of the receiver of Figure 20;
  • Figure 22a illustrates an AC power signal produced by the AC power source of Figure 1 ;
  • Figure 22b illustrates a data signal produced by the transmitter of Figure 2;
  • Figure 22c illustrates a control signal which may be used with the receiver of Figure 20;
  • Figure 22d illustrates a modified power signal which may be generated by the control signal generation block of Figure 12 if the control signal of Figure 22c is used;
  • Figure 22e illustrates a filtered signal generated in the receiver of Figure 20
  • Figure 22f illustrates a rectified signal generated in the receiver of Figure 20
  • Figure 23 illustrates the rectified signal of Figure 22f in greater detail
  • Figure 24 is a schematic diagram of a second control signal detection block which may be used with the receiver of Figure 20;
  • Figure 25a illustrates an AC power signal produced by the AC power source of Figure 1 ;
  • Figure 25b illustrates a data signal produced by a transmitter which may be used with the control signal detection block of Figure 24;
  • Figure 25c illustrates a control signal which may be used with the control signal detection block of Figure 24;
  • Figure 25d illustrates a modified power signal which may be used with the control signal detection block of Figure 24
  • Figure 25e illustrates a filtered signal generated in control signal detection block of Figure 24;
  • Figure 25f illustrates a rectified signal generated in the control signal detection block of Figure 24
  • Figure 26 illustrates the rectified signal of Figure 25f in greater detail
  • Figure 27 is a block diagram of a second circuit configured with a second signalling system according to the present invention.
  • Figure 28 is a block diagram of a transmitter of the signalling system of Figure 27
  • Figure 29 is a schematic diagram of a transmitter of the signalling system of Figure 27;
  • FIG. 30a illustrates an AC power signal produced by an AC power source of the circuit of Figure 29
  • Figure 30b illustrates a synchronization signal produced in a control signal control block of the transmitter of Figure 29;
  • Figure 30c illustrates an input signal received on a switch coupled to the control signal control block of the transmitter of Figure 29;
  • Figure 30d illustrates a data on signal produced by the control signal control block of the transmitter of Figure 29
  • Figure 30e illustrates a data off signal produced by the control signal control block of the transmitter of Figure 29;
  • Figure 30f illustrates a control signal produced by a control signal generation block of the transmitter of Figure 29;
  • Figure 30g illustrates a modified power signal produced by the transmitter of Figure 29
  • Figure 30h illustrates a maximum load current which may flow through the transmitter of Figure 29;
  • Figure 30i illustrates a power supply control signal produced in the transmitter of Figure 29
  • Figure 30j illustrates a status of the transmitter of Figure 29
  • Figure 31a illustrates an AC power signal
  • Figure 31b illustrates a control signal having a constant high frequency component
  • Figure 31c illustrates a modified power signal produced in response to the control signal of Figure 31b;
  • Figure 32a illustrates an AC power signal;
  • Figure 32b illustrates a control signal having a frequency modulated high frequency component
  • Figure 32c illustrates a modified power signal produced in response to the control signal of Figure 32b
  • Figure 33 is a schematic diagram of a third control signal control block and a fourth control signal generation block which may be used with the transmitter of Figure 2, coupled in a one-signal mode;
  • Figure 34a illustrates a pulse width modulated signal generated by the control signal control block of Figure 12
  • Figure 34b illustrates a control signal produced in the control signal generation block of Figure 12 in response to the pulse width modulated signal of Figure 13a;
  • Figure 35 shows the control signal control block and control signal generation block of Figure 33 coupled in a two signal mode.
  • Circuit 20 includes three load blocks 34, 36, 38.
  • Load block 34 includes receiver 40, a power supply 42 and a load 44.
  • Receiver 40 which is also part of signalling system 22, receives modified power signal 30 and controls power supply 42 by means of control lines 46, 48.
  • Power supply 42 provides power to the load 44.
  • Load block 34 is representative of a load which requires a regulated variable power supply to control its operations.
  • load 44 may be a gas discharge lamp such as a fluorescent tube.
  • Power supply 42 may be an electronic ballast which is responsive to a well-known "0 to 10V" signalling protocol to control the intensity of light output from the gas discharge lamp.
  • receiver 40 would be configured to translate control signal 32 into a 0 to 10 V protocol control signal for use by the ballast to control the intensity of the lamp.
  • Load block 36 includes a load 54 with an integrated receiver 52. Receiver 52 receives modified power signal 30 and controls the operation of load 54 in response to control signal 32. Load block 36 is representative of a load which may be configured to operate in different states at different times.
  • load 54 may be a HVAC system. Receiver 52 may turn various portions of the HVAC system on or off or change the temperature setting for heating or air conditioning in response to control signal 32.
  • Receiver 40 will receive the control signal 32 and modify the 0 to 10 V protocol signal to power supply 42 (an electronic ballast which is responsive to the 0 to 10 V protocol), which will turn load 44 (the gas discharge lamp) on or off or modify the intensity of lamp 44 accordingly.
  • transmitter 24 may be part of a complex computer system (not shown) configured to control many devices and systems on circuit 20 simultaneously. The computer system may control transmitter 24 to generate control signals required to control the various devices and systems.
  • Transmitter 24 has a DC power supply block 80, a control signal control block 82 and a control signal generation block 84.
  • DC power supply block 80 is coupled to terminal AC1 and AC2 and receives AC power signal 28 from AC power source 26.
  • DC power supply block 80 produces a regulated DC power supply VDD at terminal DC1 in known manner.
  • DC power supply block 80 may be any AC to DC power conversion circuit.
  • This exemplary DC power supply block 80 has a linear regulator IC1.
  • IC1 is a high voltage linear regulator power IC, model number VB408, manufactured by ST Microelectronics, although any such device may be used.
  • a data sheet for the VB408 linear regulator power IC is available from ST Microelectronics' Internet web site at www.st.com.
  • IC1 has a voltage input terminal Vin, a voltage output terminal Vout and an output voltage adjustment terminal ADJ.
  • Diode D1 and capacitor C1 are coupled in series between terminals AC2 and AC1 , which is coupled to ground.
  • Diode D1 rectifies power signal 28 and provides a positively rectified power signal Vrect at voltage input terminal Vin.
  • Capacitor C1 is chosen to ensure that Vrect is positive at all times.
  • the ADJ terminal is coupled between resistors R1 and R2, which operate as a voltage divider between output terminal Vout and ground.
  • Output terminal Vout is coupled to DC output voltage terminal DC1.
  • Capacitor C2 is used to reduce ringing in the regulated DC power supply VDD at terminal DC1.
  • regulated DC power supply VDD may be calculated as follows:
  • VDD VR1 (1+R2/R1) + IADJ * R2,
  • VR1 is the voltage drop across resistor R1 ;
  • Power supply VDD is used to power control signal control block 82.
  • control signal control block 82 ( Figure 2) requires a DC power supply of 5 volts. It has been found that the use of the following components in DC power supply block 80 provides a DC supply voltage VDD of 5 V at terminal DC1 :
  • Control signal control block 82 includes a microcontroller 90, resistor R3, zener diode D2, switches SW1 , SW2, SW3 and a signal control terminal 92.
  • Resistor R3 and zener diode D2 are connected between terminal AC1 and ground.
  • Node 94 which is at the cathode of zener diode D2 provides a zero- crossing synchronization signal 96 for microcontroller 90 at input terminal IN4.
  • Figure 5a shows AC power signal 28 at terminal AC1.
  • Figure 5b shows the synchronization signal 96.
  • Resistor R3 has a value of 100 k ⁇ and zener diode D2 has a breakdown voltage of 4.7 volts.
  • Synchronization signal 96 is approximately a square wave signal with a high level of 4.7 volts and a low level of 0 volts (neglecting the voltage drop across diode D2 during negative half waves of power signal 28).
  • Microcontroller 90 uses synchronization signal 96 to ensure that control signal 32 is synchronized with power signal 28. This is discussed in further detail below.
  • Microcontroller 90 also receives input signals from switches SW1 , SW2 and SW3 ( Figure 4) at input terminal IN1 , IN2 and IN3, respectively.
  • the present embodiment of signalling system 22 is designed to provide a 0 to 10 V protocol control signal for a gas discharge lamp (load 44 in Figure 1).
  • Switch SW1 provides an "on/off' input
  • switch SW2 provides a "dim up” input
  • switch SW3 provides a "dim down” input to control the operation of the lamp.
  • Switches SW1 , SW2 and SW3 are normally open switches connected between ground and an input terminal of microcontroller 90. When they are closed, they provide a momentary "low” input signal to microcontroller 90.
  • Microcontroller 90 may be any conventional microcontroller and may be provided with internal or external memory.
  • Microcontroller 90 receives power from terminal DC1 , at which DC power supply block 80 produces DC supply voltage VDD. [34] Microcontroller 90 has been programmed to provide a 3-bit code word on a data signal 98 at signal control terminal 92 in response to inputs received on switches SW1 , SW2 and SW3, as indicated in the following chart:
  • each code word on data signal 98 may have any number of bits, and may include error detection and error correction bits, as is well known in the art.
  • a person skilled in the art will be capable of designing a set of code words which is appropriate to the specific system in which another embodiment of a signalling system according to the present invention is used.
  • microcontroller 90 receives an input from any of switches SW1 ,
  • Microcontroller 90 receives a low input signal at terminal IN1. At the beginning of the next high pulse of synchronization signal 96, microcontroller 90 starts to send a code word consisting of bits 101 on data signal 98. Each bit commences at the start of consecutive high pulses of synchronization signal 96 with the result that data signal 98 has a frequency identical to power signal 28.
  • Figures 7a and 7b similarly show data signal 98 (Figure 7b) when an input signal is received at terminal IN2 from switch SW2 ( Figure 7a).
  • Figures 8a and 8b show data signal 98 ( Figure 8b) when an input signal is received at terminal IN2 from switch SW2 ( Figure 8a).
  • control signal generation block 84 will be explained with reference to Figures 10a - 10d, which share a common time scale, but which are out of scale with respect to the magnitude of the signals shown.
  • Figure 10a shows AC power signal 28 and is identical to Figure 5a.
  • Figure 10b shows data signal 98 after microcontroller 90 ( Figure 4) has received an input from switch SW1 ( Figure 4) and is the same as Figure 6b.
  • Figure 10c shows control signal 32, which is generated by control signal generation block 84 as described below.
  • Modified power signal 30, which is a summation of power signal 28 and control signal 32 is shown in Figure 10d.
  • diodes D3 - D6 are model number 10ETS08 diodes, manufactured by International Rectifier. Each of these diodes produces a voltage drop of approximately 0.7 volts. Accordingly, when SW4 is open, control signal 32 ( Figure 10c) is generated by diodes D3-D6.
  • control signal 32 has a magnitude of 1.4 volts and is 180° out of phase with power signal 28.
  • Control signal 32 is essentially a square wave. The rising and falling edges of control signal 32 will have the same magnitude as power signal 28 during the brief period (about 60 microseconds) at the beginning of each half wave of power signal 28 when power signal 28 has a magnitude of less than 1.4 volts.
  • switch SW4 When switch SW4 is open, the magnitude of modified power signal 30 is 0 volts while the magnitude of power signal 28 is less than 1.4 volts and is 1.4 volts less than the magnitude of power signal 28 at other times.
  • Modified power signal 30 exhibits only a small power loss compared to AC power signal 28, and then only during the transmission of a '1' bit. At most times, no data will be transmitted by transmitter 24 and modified power signal 30 will be identical to AC power signal 28 ( Figure 10a). The small difference between modified power signal 30 and AC power signal 28 will be transparent to almost all loads on circuit 20.
  • control signal 32 is equal to 0 volts when SW4 is closed and is balanced about 0 volts when SW4 is open, modified power signal 30 is also balanced about 0 volts at all times (assuming that power signal 28 is itself balanced about 0 volts). As a result, modified power signal 30 has no DC component and avoids the inefficiencies of prior art systems which generate a control signal that is not balanced about 0 volts.
  • Control signal generation block 84b has diodes D3 and D4, which operate in the same manner as in control signal generation block 84.
  • diodes D5 and D6 and switch SW4 of control signal generation block 84 have been replaced with a MOSFET type transistor Q1 and an inverter 93 in control signal generation block 84b.
  • the drain of transistor Q1 is coupled to terminal AC1 and the source of transistor Q1 is coupled to terminal AC3.
  • the gate of transistor Q1 is coupled to terminal 92 through inverter 93.
  • the operation of control signal generation block 84b is similar to the operation of control signal generation block 84.
  • transistor Q1 When data signal 98 (on terminal 92) is low, the gate input of transistor Q1 is high due to inverter 93. Transistor Q1 conducts and acts as a closed switch between terminal AC1 and AC3. When signal 98 is high, the gate input of transistor Q1 is low and transistor Q3 is off and acts as an open switch with respect to positive half wave of power signal 28. During negative half waves of power signal 28, the internal reverse diode of transistor Q1 produces a voltage drop. In the preferred embodiment of control signal generation block 84b, transistor Q1 is a model number IRLIZ44N transistor produced by International Rectifier. The internal reverse diode of this transistor produces a voltage drop of approximately 1 volt.
  • diodes D3 and D4 together produce a voltage drop of about 1.4 volts.
  • the imbalance introduced into the modified power signal 30 (which is the sum of AC power signal 28 and control signal 32) as a result of this imbalance is very small. Assuming that AC power signal 28 has a magnitude of 120 volts, then positive half wave of modified power signal 30 will have a magnitude of approximately 118.6 volts (120 volts - 1.4 volts dropped by diodes D3 and D4) and negative half waves of modified power signal 30 will have a magnitude of approximately 119 volts (120 volts - 1 volt dropped across the internal reverse diode of transistor Q1).
  • control signal generation block 84b The percentage difference between the magnitude of the two half waves is only about 0.34% (( 19-118.6)/119). Accordingly, the control signal 32 and modified power signal 30 produced by control signal generation block 84b are essentially the same as those produced by control signal generation block 84, as shown in Figures 10c and 10d. Control signal generation block 84b therefore provides the benefit of an essentially balanced modified power signal 30 at terminal AC3 and AC4. The small imbalance of 0.34% is negligible and provides a good compromise between the desire to reduce the DC component added to modified power signal 30 and the need to provide a transmitter at a commercially feasible cost. [45] Control signal generation blocks 84 and 84b produce an essentially square wave control signal 32, as described above.
  • Control signal control block 82b is identical to control signal block 82 except that microcontroller 90' is programmed to provide a pulse width modulated (PWM) signal 102 at output terminal 100 in addition to data signal 98.
  • PWM pulse width modulated
  • Data signal 98 generated by control signal control block 82b is identical to data signal 98 generated by control signal control block 82 and is shown in Figure 10b.
  • Figure 13a shows PWM signal 102.
  • PWM signal 102 has a magnitude of 0 volts when (i) data signal 98 is 0 (i.e.
  • PWM signal 102 is used to control the shape of a control signal 32' generated by control signal generation block 84c.
  • Resistor R4 and capacitor C3 are connected as a low pass filter which provides a smoothed signal 106 corresponding to PWM signal 102 at the non-inverting input of op-amp 104.
  • Amplifier 104 and resistors R5 and R6 are configured as an inverting amplifier with a "virtual" ground at its negative input.
  • the emitter of pnp power transistor Q3 is coupled to terminal AC1.
  • the base of transistor Q3 is coupled to the output of amplifier 104.
  • the collector of transistor Q3 is coupled to the base of transistor Q4.
  • the collector of transistor Q4 is coupled to terminal AC1 and the emitter of transistor Q4 is coupled to terminal AC3.
  • resistor R4 and capacitor C3 filter higher order frequency components from PWM signal 102 to produce smoothed signal 106 corresponding to PWM signal 102 at the inverting input of amplifier 104.
  • Amplifier 104 inverts and amplifies the difference between power signal 28 at terminal AC1 and the smoothed signal 106 and produces a corresponding amplified signal 108 at the base of transistor Q3.
  • Transistor Q3 converts this amplified signal 108 (which is essentially a voltage signal) into a current signal 110 at the base of transistor Q4, which operates in its active region to produce a voltage drop Vdrop across its collector and emitter.
  • Voltage drop Vdrop corresponds to smoothed signal 106.
  • Control signal 32' is defined by the summation of voltage drop Vdrop and the voltage dropped across the internal reverse diode of transistor Q2.
  • Control signal 32' is shown in Figure 13b.
  • Modified power signal 30' is the sum of control signal 32' and power signal 28 and is shown in Figure 13c.
  • Figure 14 shows one wavelength of modified power signal 30' during the transmission of a '1' bit, corresponding to time period t2 in Figure 13c.
  • Modified power signal 30' is shown in solid outline.
  • Power signal 30, during the same time period is shown in dotted outline.
  • the positive half wave of modified power signal 30' is shaped to be relatively smooth, in contrast to the negative half wave of power signal 30'.
  • PWM signal 102 is selected such that smoothed signal 106 has no sharp transitions and by selecting the amplification factors of amplifier 104 and transistor Q3 such voltage drop Vdrop also has no sharp transitions, including at its leading and trailing edges.
  • PWM signal 102 is selected such that the average voltage of the positive half wave of modified power signal 30' is approximately equal to the average during the negative half wave of modified power signal 30'. This ensures that there is no DC component in modified power signal 30', even though the shapes of the positive and negative half waves are different. This may be done by ensuring that the area A under the positive half wave of the voltage curve of modified power signal 30' is approximately equal to the area B under the negative half wave of the voltage curve of modified power signal 30'.
  • Microcontroller 90' ( Figure 12) is programmed to generate PWM signal 102 to provide this result.
  • Control signal generation block 84c provides an important advantage over control signal generation block 84 ( Figure 9) and 84b ( Figure 11).
  • Control signal generation block 84 relies on diodes D3-D6 to produce control signal 32.
  • Control signal generation block 84b relies on diodes D3 and D4 to produce control signal 32.
  • control signal control block 82b and control signal generation block 84c may be used to produce many differently shaped waveforms in the positive half cycle of modified power signal 30' by appropriately selecting PWM signal 102. As long as area A of the modified power signal 30' is approximately equal to area B of the modified power signal 30', the advantage that no DC component is introduced into modified power signal 30' which is ultimately used to power various loads, such as loads 44, 54 and 56 ( Figure 1) will be retained.
  • Control signal generating block 84c provides the advantage of reduced power losses and control over the shape of modified power signal 30' only during the positive half wave of AC power signal 28, since the internal reverse diode of transistor Q2 is still used to generate control signal 32' in the negative half wave.
  • both the positive and negative half cycles of modified power signal 30' may be shaped by adding a voltage dropping circuit between terminals AC3 and AC1 which operates when transistor Q3 is not conducting and power signal 28 is in its negative half cycle.
  • modified power signal 30' may be precisely shaped during both the positive and negative half waves, independently of the current flowing through the circuits, thereby providing the benefit of reduced power losses during the positive and negative half waves of AC power signal 28.
  • a control signal generation block with active voltage dropping circuits for both halves of the control signal may also be used to achieve other objectives, such as reducing the generation of EMI or harmonics in the signalling system.
  • Figure 15b shows two cycles of AC power signal 28.
  • control signal 32 has a zero magnitude.
  • control signal 32a is non-zero for part of each half wave of the cycle.
  • time periods t3 and t5 control signal 32a is a smoothed negative curve.
  • time period t4 control signal 32a has a zero magnitude.
  • Modified power signal 30a which is summation of AC power signal 28 and control signal 32a is shown in Figure 15c.
  • modified power signal 30a has a magnitude smaller than that of AC power signal 28 (shown in dotted outline in Figure 15c). However, during time period t4, modified power signal 30a has the same magnitude as AC power signal 28.
  • the use of control signal 32a reduces the voltage drop on AC power signal 28 during time period t4, when AC power signal 28 is maximized. This reduces the power consumption of the transmitter.
  • a control signal generation block with two active voltage dropping circuit has the disadvantage that the additional circuitry increases the cost and complexity of the transmitter. Additional power electronic components are required to generate control signal 32a during the negative half wave.
  • Control signal generation block 84d comprises two control signal generation sub-blocks 84e and 84f.
  • Control signal generation sub-block 84e is identical to control signal generation block 84c ( Figure 12).
  • the collector of transistor Q4 is coupled to a terminal 402 and the source of transistor Q2 is coupled to a terminal 404.
  • Control signal generation sub-block 84f is symmetrical to control signal generation sub-block 84e and the corresponding elements are indicated with similar reference numerals with a prime (') mark.
  • the collector of transistor Q4' is coupled to a terminal 406.
  • the drain of transistor Q2' is coupled to a terminal 406 and the source of transistor Q2' is coupled to a terminal 408.
  • a switch SW8 is coupled between the sources of transistors Q2 and Q2'.
  • Control signal control block 82c includes a microcontroller 90" which is similar to microcontroller 90'. In addition to PWM signal 102 and data signal 98 at terminals 100 and 92, respectively, control signal control block 82c also generates a second PWM signal 102' at a terminal 100' and a second data signal 98' at a terminal 92'. It may be preferably to isolate control signal generation sub-blocks 84e and 84f from each other, particularly where the two control signal generation sub-blocks 84e and 84f do not share a common reference point. Optical isolation blocks 414 and 416 are provided for this purpose. Optical isolation block 414 is coupled between terminal 100' and resistor R4'.
  • Optical isolation block 416 is coupled between terminal 96' and diode 93'.
  • Optical isolation blocks 84e and 84f allow PWM signal 102' and data signal 98' to be level shifted or otherwise adjusted.
  • a person skilled in the art will be capable of adjusting signal 102' and 98' for use in controlling the operation of control signal generation sub-block 84f.
  • Control signal control block 82c and control signal generation block 84d may be configured to operate in two modes: a one control signal mode and a two- control signal mode.
  • the one control signal mode is illustrated in Figure 33. In this mode, terminal 402 is coupled to terminal AC1 , terminal 406 is coupled to terminal AC3 and switch SW8 is closed.
  • Control signal control block 82c generates PWM signal 102 and data signal 98 in response to signals from switches SW1 , SW2 and SW3, as described above in relation to control signal control block 82b.
  • Data signal 98 is high when a '1' bit in a control word is to be transmitted.
  • PWM signal 102 controls the shape of the control signal 30' ( Figure 13b) during positive half waves of power signal 28 when a '1' bit is transmitted.
  • Control signal generation sub-block 84e operates in a manner analogous to control signal generation sub-block 84c.
  • Control signal generation sub-blocks 84e and 84f and coupled in series between terminals AC1 and AC3 and cooperate to provide a highly controllable control signal 32f (Figure 34b).
  • Control 32f is generated as follows. When no data is to be transmitted, or when a '0' bit is to be transmitted, data signal 98 and 98' are low and transistors Q2 and Q2' conduct both the positive and negative half waves of power signal 28 between terminals AC1 and AC3. Control signal 32f thus has a magnitude of 0 volts. When a '1' bit is to be transmitted, data signals 98 and 98' are high and PWM signals 102 and 102' are non-zero during the positive and negative half-waves of power signal 28.
  • Transistor Q4 has a voltage drop Vdrop (controlled by PWM signal 102) across it and the internal reverse diode of transistor Q2' creates an additional voltage drop between terminals AC1 and AC3.
  • Control signal 32f is equal to the sum of these voltage drops during positive half waves of power signal 28.
  • a modified power signal 30f (Figure 34c) equal to the sum of power signal 28 and control signal 32f is produced at terminal AC3, which is coupled to a load (for example, load 44 in Figure 1).
  • switch SW8 In the two signal mode, switch SW8 is opened so that control signal generation sub-blocks 84e and 84d operated independently of one another.
  • a set of switches SW9, SW10 and SW11 are coupled to input terminals IN5, IN6 and IN7 of microcontroller 90".
  • Switches SW9, SW10 and SW11 are analogous to switches SW1 , SW2 and SW3, but are operated independently. As is described below, switch sets SW1-SW3 and SW9-SW11 are used to independently control to different loads.
  • Microcontroller 90 generates data signal 98 and PWM control signal
  • Control signal generation sub-block 84e is coupled between terminals AC1 and AC3 and operates in the manner described in relation to control signal generation block 84c to produce a modified power signal (i.e. power signal 30') at terminal AC3.
  • Control signal generation sub-block 84f is coupled between between terminal AC1 (at node 406) and a terminal AC3', which is coupled to a second load (not shown) which may be similar to load 44 ( Figure 1). This second load will typically be independent of the load 44 coupled to terminal AC3.
  • Receiver 40 includes a DC power supply block 120, a control signal detection block 122 and a control signal conversion block 124.
  • DC power supply block 120 is coupled to terminals AC3 and AC4 on which it receives modified power signal 30.
  • DC power supply block 120 produces a regulated DC power supply Vcc at terminal DC2.
  • Power supply Vcc is used to power control signal detection block 122 or control signal conversion block 124.
  • Low voltage power supply block 120 may be the same as DC power supply block 80 or may be any other circuit that provides a regulated DC power supply from an AC power signal such as modified power signal 30.
  • Control signal detection block 122 is coupled to terminals AC3 and AC4 on which it receives modified power signal 30. Control signal detection block 122 detects control signal 32 and provides a data stream 128 corresponding to digital data signal 98 ( Figures 4, 6b, 7b and 8b) at terminal 126.
  • Control signal conversion block 124 receives data stream 128 and generates a 0 to 10 V protocol control signal at terminals 46 and 48 which may be used with known electronic ballasts (power supply 42 ( Figure 1) in the present example) to control the operation of a gas discharge lamp (load 44 in the present example).
  • the 0 to 10 V control signal has a positive component LAMP+ and a negative component LAMP-.
  • Control signal detection block 122 includes resistors R7 and R8, a capacitor C4, a diode D7, a microcontroller 134 which includes an analog to digital (A/D) converter and a microcontroller 136.
  • diode D7 The anode of diode D7 is coupled to terminal AC3 and the cathode of diode D7 is coupled to ground through resistors R7 and R8. Capacitor C4 is coupled across resistor R8. Diode D7 rectifies modified power signal 30 so that rectified signal 142 with only the positive half waves of modified power signal 30 appear at node 138. Resistors R7 and R8 form a voltage divider so that a portion of the rectified signal 142 appears at the node between resistors R7 and R8. As is well known, AC power distribution lines are highly susceptible to and often highly polluted with high frequency noise such as power spikes.
  • Resistor R7 and capacitor C4 form a low pass filter which filters such high frequency noise from the signal across resistor R8, providing a filtered signal 144 at node 140.
  • An input terminal IN1 of microcontroller 134 is coupled to node 140 and receives filtered signal 144.
  • Microcontroller 134 is programmed to calculate the area under the voltage curve for each positive half wave of filtered signal 144. Modified power signal 30 is shown in Figure 18a, which is identical to Figure 10d.
  • Figure 18b shows the corresponding filtered signal 144.
  • Microcontroller 134 is a model
  • Microcontroller 134 is programmed to calculate the area under the voltage curve for each positive half wave of filtered signal 144 (i.e. integrating the voltage curve). This is done by sampling the magnitude of filtered signal 144 periodically and summing each sample to provide an estimate of the area. At the end of each positive half wave of filtered signal 144, microcontroller 134 provides a data word indicating the area of the preceding positive half wave at node 146, which is coupled to an output terminal OUT1 of microcontroller 134.
  • microcontroller 134 provides a data stream 148 of raw area values ( Figure 18c) corresponding to the area under each successive positive half wave of filtered signal 144.
  • Filtered signal 144 must be sampled sufficient times during each positive half wave to provide an accurate estimate of area.
  • microcontroller 134 is programmed to sample filtered signal every 32 ⁇ s (approximately 300 samples per half wave) to provide an accurate measurement of the area of each half wave.
  • terminal OUT1 and node 146 may consist of a number of parallel lines or a serial line.
  • An input IN of microcontroller 136 is coupled to node 146 to receive data stream 148.
  • Microcontroller 136 is programmed to convert data stream 148 into data stream 128 corresponding to the data signal 98.
  • Data stream 128 is generated at terminal OUTof microcontroller 136, which is coupled to terminal 126.
  • Microcontroller 136 reads each successive raw area value from data stream 148 and determines whether (i) a code word originally generated by control signal control block 80 as part of data signal 90 ( Figure 4) is being received and (ii) if so, whether the raw area value corresponds to a "0" bit or a "1" bit.
  • the present exemplary embodiment of signalling system 22 uses three code words (101 , 110 and 111) to represent input received on switches SW1 , SW2 and SW3, respectively (see Figure 4).
  • the first bit of each of these code words is a start bit, which indicates to microcontroller 136 that transmission of a code word has started.
  • Microcontroller 136 is programmed to interpret the following two bits to determine which input was received by the transmitter 24 (i.e.
  • Pulses are high frequency noise, generally of short duration. A pulse which has sufficient magnitude or duration may affect the interpretation of a data bit encoded into the half wave.
  • Signalling system 22 addresses the problem of pulse disturbances in two ways. The first is the use of a low pass filter consisting of resistor R7 and capacitor C4 in signal detection block 122, as described above. The second is the use of an integrated value to represent each positive half wave of filtered signal 144 rather than using a peak value or other measure which would be susceptible to pulse disturbances. [87] To address the problems of voltage fluctuations (disturbances with a smaller amplitude than a pulse and with a frequency of about 2-3 Hz, in general) and voltage drifts (which have a frequency of about 0.1 Hz or less), signalling system 22 uses an interpolation algorithm to determine whether a particular raw area value corresponds to a "0" or "1" bit.
  • Microcontroller 136 is programmed to establish two threshold values TH0 and TH1.
  • Threshold value TH0 represents the minimum raw area value that will automatically be considered to be a 'low' or logical '0' bit.
  • Threshold value TH1 represents the maximum raw area value that will automatically be considered to be a 'high' or logical '1' bit. In general, the difference between threshold values TH0 and TH1 will be fixed.
  • microcontroller 136 modifies threshold values THO and TH1 to track fluctuations and drifts in modified power signal 30.
  • microcontroller 136 uses a soft decision viterbi algorithm to determine whether the raw area value corresponds to a '0' or '1'.
  • microcontroller 136 also changes threshold values THO and TH1 to be centred between the expected raw area values for subsequent '0' and '1' bits. This viterbi algorithm will be well known to persons skilled in the art and is not further explained here.
  • the communication protocol of signalling system 22 may be configured such that no more than a selected number of '1' bits may be transmitted consecutively. If more than the selected number of '1' bits are received by the receiver 40, then microcontroller assumes that its threshold values THO and TH1 are incorrect and adjusts them so that the raw area values previously deemed to be '1' bits will now be deemed to be '0' bits. This and other methods of detecting errors in data transmitted by transmitter 24 will be familiar to persons skilled in the art.
  • microcontroller 136 is model
  • microcontrollers 134 and 136 are separated into two processing units to provide sufficient computing power to complete each function without loss of data.
  • a single appropriately selected microcontroller may be configured to perform all of these functions, if it is desired.
  • Control signal conversion block 124 includes a microcontroller 202, a microcontroller 204, capacitors C5 and C6, resistors R9, R10, R11 , R12, R13 and zener diode D8.
  • An input terminal IN2 of microcontroller 202 is coupled to node 126 to receive bit stream 128.
  • Bit stream 128 contains each code word transmitted by control signal control 82 in response to input signals received on switches SW1 , SW2 and SW3 ( Figure 4).
  • Microcontroller 202 is programmed to maintain a "Brightness" variable for the gas discharge lamp (load 44 in Figure 1) coupled to receiver 40.
  • Microcontroller 202 receives bit stream 128, assembles the code words and then adjusts the Brightness variable in response to the code words.
  • the 0 to 10 V protocol used by power supply 42 ( Figure 1) has 30 steps which allow a gas discharge lamp to be set at any of 30 intensity levels.
  • Microcontroller 202 may be programmed to maintain the Brightness variable as an integer in the range of 0-30, where 0 represents a lamp that is off and 30 represents a lamp at full brightness. In addition, microcontroller 202 maintains a "Last Intensity" variable. When code word 101 , which corresponds to SW1 (on/off), is received microcontroller is programmed to: (i) if the Brightness variable is not 0, then (a) store the value of the
  • Microcontroller 204 is programmed to produce a pulse width modulated (PWM) brightness signal 212 corresponding to the value of the Brightness variable at node 210.
  • PWM pulse width modulated
  • microcontroller 202 is a P87LPC764 model microcontroller manufactured by Philips Semiconductor.
  • microcontroller 202 is the same unit as microcontroller 136 and the single unit is programmed to perform all functions described for both microprocessors 136 and 202.
  • Microcontroller 204 is a microcontroller manufactured by Microchip
  • Resistors R9 and R10 are coupled in series between node 210 and ground. Capacitor C5 is coupled across resistor R10. Together, resistors R9, R10 and capacitor C5 form a low pass filter which smooths PWM brightness signal 212 to form a smoothed brightness signal 216 at node 214. Comparator 206 receives smoothed brightness signal 216 at its positive input node. Comparator 206 produces signal LAMP+ at terminal 46 through resistor R12. Resistors R11 and R13 are coupled in series between output terminal 46 and ground to form a voltage divider which produces an image signal 222 at node 220. Image signal 222 is a portion of the signal LAMP+.
  • comparator 206 compares smoothed brightness signal 216 with image signal 222. If smoothed brightness signal 216 is greater than image signal 222, then signal LAMP+ is reduced through resistor R12. If smoothed brightness signal 216 is less than image signal 222, then signal LAMP+ is increased through terminal 46, which acts as a current source, in accordance with the 0 to 10 V standard protocol. Capacitor C6, which is coupled between output terminal 46 and ground, smooths these transitions of signal LAMP+ to ensure that the intensity of the gas discharge lamp coupled to terminals 46 and 48, which is coupled to ground, does not change too rapidly.
  • Microcontroller 204 is programmed to produce PWM brightness signal
  • Zener diode D8 which has a breakdown voltage of 15 V is coupled between output terminal LAMP+ and ground to ensure that the output signal 118 cannot exceed 15 volts in any case. Zener diode D8 is used to prevent damage to receiver 40 and components connected to terminals LAMP+ and LAMP-.
  • Control signal detection block 122 of receiver 40 uses an integration algorithm to detect and '0' bits in modified power signal 30. This algorithm is computation intensive and requires a fairly powerful microcontroller 134 with an integrated (or coupled) A/D converter.
  • Figure 20 shows an alternative receiver 40'. Receiver 40' is identical to receiver 40, except for control signal detection block 122'. Control signal detection block 122' is coupled to terminals AC3 and AC4 to receive modified power signal 30" ( Figure 22d) which includes control signal 32", which was added to modified power signal 30" by a transmitter such as transmitter 84c. Control signal detection block 122' produces a digital data stream 128' at a terminal 126', which corresponds to terminal 126 of receiver 40.
  • Control signal detection block 122' includes resistors R20, R21 , R22, R23, capacitors C14, C15, diode D14, DC voltage source Vref and a microcontroller 135.
  • Resistors R20 and R21 are coupled in series between terminals AC3 and AC4.
  • Capacitor C14 is coupled across resistor R21.
  • Resistors R20, R21 and capacitor C14 form a low pass filter 131.
  • Resistor R22 and capacitor C15 are coupled in series across capacitor C14 and form a second low pass filter 133.
  • Figure 22a shows AC power signal 28.
  • Figure 22b shows data signal 98 as it appears when an input signal is received on switch SW1 ( Figures 4, 6a and 6b).
  • Figure 22c shows a control signal 32", which is selected to provide a modified power signal 30" which may be detected by control signal detection block 122'.
  • Control signal 32" is also chosen to have a zero amplitude during the peak of AC power signal 28, to reduce power consumption, as described above in relation to control signal 32a ( Figure 15b).
  • Figure 22d shows the modified power signal 30" which results from the use of control signal 32".
  • Figure 22e shows filtered signal 144'.
  • a rectified signal 147 (Figure 22f) is produce by diode D14 at node 145.
  • rectified signal 147 Due to the asymmetry introduced into low pass filter 133, rectified signal 147 exhibits a longer positive half wave when a '0' bit is transmitted than when a '1' bit is transmitted.
  • Microcontroller 135 is coupled to node 145 to receive rectified signal 147 at a terminal IN1.
  • a terminal IN2 of microcontroller 135 is coupled to voltage source Vref.
  • An output node OUT2 of microcontroller 135 is coupled to terminal 126'.
  • Figure 23 shows rectified signal 147 and reference voltage Vref.
  • Time period t21 corresponds to a positive half wave of modified signal 30" during which a '1' bit was transmitted and time period t22 corresponds to a positive half wave of modified signal 30" when a '0' bit was transmitted.
  • rectified signal 147 exceeds voltage Vref for time period t23.
  • rectified signal 147 exceeds voltage Vref for time period t24.
  • microcontroller 135 is programmed to compare rectified signal 147 with reference voltage Vref and to measure the time period during each positive section of rectified signal 147 that rectified signal 147 exceeds the reference voltage Vref. When the measured time period is equal to or greater than a threshold Th (not shown), then a '0' is deemed to have been received. When the measured time period is less than or equal to a threshold TI (not shown), then a '1' bit is deemed to have been received. Thresholds Th and TI are chosen such that microcontroller is reliably able to detect '0' and '1' bit from modified power signal 30". Microcontroller generates data stream 128' in response to data bits detected.
  • Control signal detection block 122 may be used in place of control signal detection block 122' in receiver 40'.
  • Control signal detection block 122" allows 2 bits of data to be transmitted during each positive half wave of modified power signal 30" ( Figure 22d).
  • Control signal detection block 122" is identical to control signal detection block 122' with the following exceptions: (i) microprocessor receives two DC voltage reference signals VREF1 and VREF2 at terminals IN1 and IN2; and (ii) microprocessor 135' receives filtered signal 147 at terminal IN1 and produces a data stream 128" at terminal 126".
  • Figures 25a - 25f which have a common time scale but do not have a common magnitude scale.
  • Figure 25a shows AC power signal 28a.
  • Figure 25b shows a data signal 98'.
  • Data signal 98' is similar to data signal 98 ( Figure 22b), except that data signal 98' includes two data bits in the period corresponding to the positive half wave of each cycle of AC power signal 28.
  • the four periods of data signal 98' shown represent '00', '01', '10' and '11' bit combinations. When a '00' bit combination is to be transmitted, signal 98' is low during the period corresponding to the negative half wave of AC power signal 28.
  • control signal 32' in response to data signal 98' and a PWM signal 102' (not shown) is shown in Figure 25c.
  • control signal 32' when a '11 ' bit combination is transmitted, control signal 32'" is identical to control signal 32" ( Figure 22c). However when a '10' or a '01' bit combination is transmitted, control signal 32'" includes a non-zero component only during the first portion or last portion, respectively, of the positive half wave of AC signal 28. When a '00' bit combination is transmitted, control signal 32'" has a magnitude of zero.
  • a person skilled in the art will be capable of programming microcontroller 90' of Figure 12 to produce data signal 98' and PWM signal 102'.
  • control signal 32' When a '01' or a '10' bit combination is to be transmitted, control signal 32'" has a magnitude of 1 volt during the first half of the negative half wave of AC power signal 28 and 0 volts during the second half of the negative half wave, in response to control signal 32'". This is done to reduce any DC component introduced into modified power signal 30'".
  • Figure 25d shows modified power signal 30'" produced on at terminal
  • a time shift s in the rising edge of rectified signal 147' will occur when a '10' or a '11' bit combination was transmitted.
  • a time shift u in the falling edge of rectified signal 147' will occur when a '01' or '11' bit combination was transmitted.
  • Microcontroller 135' compares rectified signal 147' to voltage reference signals VREF1 and VREF2.
  • Voltage reference signal VREF1 is selected to be at a magnitude that will be time shifted during the rising edge and during the falling edge of rectified signal 147' when a '11' bit combination is received.
  • microcontroller 135' During each pulse of rectified signal 147', microcontroller 135' records:
  • the time period TR will equal TR0. If the first bit of the received bit combination is a '1' (ie. a '10' or '11' bit combination was received), then time period TR will equal TR1. [116] If the second bit of a received bit combination is a '0' (i.e. if a '00' or '10' bit combination was received), then time period TF will equal TF0. If the second bit of a received bit combination is a '1' (i.e.
  • time period TF will equal TF1.
  • a signalling system configured with receiver 40' and with a control signal control block and a control signal generation block modified as described above may be used in this manner to transmit two data bits during each cycle of AC power signal 28. This increased data bandwidth may be used to increase the speed at which code words are transmitted or may be used to add additional error correction bits to code words without any loss in the effective data transmission rate.
  • the combination of receiver 40' and a properly configured transmitter form a generic communication system that is not limited to signalling systems such as signalling system 22.
  • a modified power signal is analogous to a data transmission signal in such a generic communication system.
  • the transmitter of such a system may add a signal waveform which may be received and filtered through an asymmetric filter to detect a time shift at one or two selected magnitudes, such as Vrefl and Vref2.
  • the output of such a filter may be analyzed by microprocessor with very little processing overhead to produce entirely digital output signal.
  • Circuit 20 is representative of North American power distribution circuits in which both a hot wire and a neutral wire are accessible in all switch boxes. This is not generally the case in Europe and other parts of the world. In a typical European power distribution circuit, only a hot wire is accessible in a switch box, although a neutral wire is generally accessible at a load. Accordingly, it is necessary to provide a transmitter which can function without access to the neutral wire.
  • Figure 27 shows a circuit 300 configured with a signalling system 302.
  • Signalling system 302 is similar to signalling system 22, except that signalling system 302 includes a transmitter 304 that is coupled to terminal AC1 , which is coupled to the hot line of circuit 300.
  • Transmitter 304 is not coupled to terminal AC2, which is coupled to the neutral line of circuit 300. Transmitter 304 receives power signal 28 from terminal AC1 , generates a control signal 306 and produces a modified power signal 308 at terminal AC3.
  • the remaining components of circuit 300 and signalling system 302 are identical to the corresponding components in circuit 20 and signalling system 22 and are identified with the same reference numerals as in Figure 1. [122]
  • signalling system 302 is configured to provide a 0 to 10 V protocol control signal for a gas discharge lamp (load 44 in Figure 27).
  • signalling system 302 may be configured to operate more than one device and may be configured to operate many different types of devices.
  • Transmitter 304 includes a DC power supply block 310, control signal control block 312 and control signal generation block 318.
  • DC power supply block 310 is coupled to terminals AC1 and AC3 to receive AC power signal 28.
  • DC power supply block 310 produces a DC power supply consisting of DC power signals +VDC and - VDC across nodes DC3 and DC4.
  • DC power supply block 310 also produces a DC power signal VAA at node DC5.
  • DC power signal VAA is a positive voltage signal used to power various components of transmitter 304.
  • Control signal control block 312 receives DC power supply +VDC / -
  • Control signal control block 312 is also coupled to terminal AC1.
  • Control signal control block 312 produces a pair of control signals 320 and 322 synchronized with AC power signal 28 at terminals 314 and 316.
  • Control signal generation block 318 is coupled to terminal AC1 to receive AC power signal 28, to terminals 314, 316 to receive control signal 320 and to node DC5 to receive DC power supply VAA.
  • Control signal generation block produces a modified AC power signal 308 at terminal AC3 in response to control signals 320 and 322.
  • Figure 29 is a schematic diagram of transmitter 304. The operation of transmitter 304 will be explained with reference to Figures 30a - 30j, which share a common time scale, but which are out of scale with respect to the magnitude of the signals shown.
  • Control signal control block 312 comprises resistors R17, R18, switches SW5, SW6, SW7 and a microcontroller 326.
  • Microcontroller 326 receives power from nodes DC3 and DC4, at which power supply block 310 produces DC power signal +VDC and -VDC, as is explained below.
  • the positive power input terminal VDD of microcontroller 326 is coupled to terminal DC3 and the negative power input terminal VSS is coupled to terminal DC4.
  • Microcontroller 326 is coupled to switches SW5, SW6 and SW7 at input terminals IN1 , IN2 and IN3, respectively.
  • signalling system 302 is configured to control a gas discharge lamp (load 44 in Figure 27).
  • Switches SW5, SW6 and SW7 correspond to switches SW1 , SW2 and SW3 of transmitter 24 ( Figure 4).
  • Switch SW5 provides an "on/off' input
  • switch SW6 provides a “dim up” input
  • switch SW7 provides a “dim down” input to control the operation of the lamp.
  • Switches SW5, SW6 and SW7 are normally open switches connected between terminal DC4 and an input terminal of microcontroller 326. When they are closed, they provide a momentary "low” signal to microcontroller 326, with a magnitude equal to -VDC, which is the same as the voltage applied to the negative power input terminal VSS of microcontroller 326.
  • Microcontroller 326 is similar to microcontroller 90 and may be any conventional microcontroller.
  • microcontroller 326 is a model 87LPC764 microcontroller manufactured by Philips Semiconductor.
  • Control signal generation block 318 includes diodes D15, D16, and D17 and a MOSFET type transistor Q5.
  • Diodes D15, D16 and D 7 operate in a manner analogous to diodes D3 and D4 of control signal generation block 84b.
  • Transistor Q5 operates in a manner analogous to transistor Q1 of control signal generation block 84b, described above.
  • Diodes D15, D16 and D17 are selected such that each of them has a voltage drop of about 0.6 volts and as a group they provide a total voltage drop of about 1.8 volts.
  • Transistor Q5 is connected between terminals AC1 and AC3. When transistor Q5 is conducting, modified power signal 308 at terminal AC3 will be identical to AC power signal 28 at terminal AC1. When transistor Q1 is not conducting, diodes D15, D16 and D17 will reduce the magnitude of modified power signal 308 by approximately 1.8 volts during positive half waves and the internal reverse diode of transistor Q5 will reduce the magnitude of modified power signal 308 by approximately 1 volt during negative half waves. Terminal AC3 is coupled to ground.
  • Node 328 is connected to terminal AC3 (and ground) through resistor
  • Node 330 is connected to terminal AC1 (and node 322) through resistor R18.
  • the 1.8 volt potential and the -1 volt potential which appears between node 322 and ground when transistor Q5 is not conducting provides a synchronization signal 340 at nodes 328 and 330.
  • Input terminals IN4 and IN5 of microcontroller 326 are coupled to nodes 328 and 330 to receive synchronization signal 340.
  • Synchronization signal 340 is the negative of control signal 306, which is described below.
  • Synchronization signal 340 ( Figure 30f) is used by microcontroller 326 to synchronize the output signals (described below) of microcontroller 326 with AC power signal 28.
  • Figure 30a shows AC power signal 28.
  • Figure 30b shows synchronization signal 340 over a corresponding time period.
  • Output nodes OUT1 and OUT2 of microcontroller 326 are coupled respectively to signal on control terminal 332 and signal off control terminal 334.
  • Microcontroller 326 has been programmed to provide a three bit code word on a data on signal 336 and a data off signal 338 at signal on control terminal 332 and signal off control terminal 334, respectively.
  • Data on signal 336 and data off signal 338 are mirror image signals such that when data on signal 336 is high, data off signal 338 is low.
  • a '1' bit is to be transmitted, data on signal 336 will be high and data off signal 338 will be low.
  • a '0' bit is to be transmitted, or no data is to be transmitted at all, data on signal 336 will be low and data off signal 338 will be high.
  • control signal generation block 318 includes Q6, Q7, Q8 and resistors R19, R24 and R25, in addition to diodes D15, D16, D17 and transistor Q5 which were discussed above.
  • the base of transistor Q6 is coupled to terminal 332 through resistor R24 to receive data on signal 336.
  • the base of transistor Q7 is coupled to terminal 334 through resistor R25 to receive data off signal 338.
  • the collector of transistor Q6 is coupled to the collector of pnp transistor Q8 and also to the gate of transistor Q5.
  • the collector of transistor Q7 is coupled to the base of transistor Q8 through resistor R19.
  • the emitter of transistor Q8 is coupled to terminal DC5 where it receives DC power signal VAA.
  • the emitters of transistors Q6 and Q7 are coupled to terminal DC4.
  • the negative power input terminal VSS of microcontroller 326 is coupled to terminal DC4, at which DC power supply block 310 produces a DC voltage signal -VDC.
  • data on signal 336 and data off signal 338 are referenced to voltage signal -VDC, rather than to ground.
  • control signal generation block 318 is as follows.
  • control signal 306 consisting of a stream of '0' and '1 ' bits, is superimposed onto AC power signal 28 to form modified power signal 308.
  • Control signal 306 and modified power signal 308 are shown in Figures 30f and 30g, during the period corresponding to Figures 30d and 30e.
  • resistor R14 and capacitor C7 are coupled in series between node 322 and ground.
  • the base of transistor Q9 is coupled between resistor R14 and capacitor C7.
  • the emitter of transistor Q9 is coupled to ground.
  • the collector of transistor Q9 is coupled to the base of pnp transistor Q10 and to the base of pnp transistor Q11 through resistor R15.
  • the collectors of transistors Q10 and Q11 are coupled to node 322.
  • the emitter of transistor Q10 is coupled to ground through transistor C8 and also to node DC3.
  • Terminal DC5 is coupled to capacitor C11 , which is coupled to terminal 334 to receive data off signal 338.
  • Charge pump voltage inverter 324 provides a voltage equal to -Vin at terminal Vout.
  • a voltage potential of 1.8 volts will exist between node 322 and ground during positive half waves of AC power signal 28 when a '1 ' bit is being transmitted on modified power signal 308.
  • the 1.8 voltage potential between node 322 and ground will charge capacitor C7 through resistor R14.
  • transistor Q9 When capacitor C7 is sufficiently charged, transistor Q9 will turn on, causing the voltage at the collector of transistor Q9 to fall. This will turn pnp transistors Q10 and Q11 on.
  • terminal DC3 When transistor Q10 enters its saturation region, terminal DC3, at the collector of transistor Q10 will have a voltage of 1.8 volts (equal to the potential between node 322 and ground). This voltage at terminal DC3 is voltage signal +VDC. Voltage signal +VDC will charge capacitor C8. [142] Simultaneously, terminal Vin of charge pump voltage inverter 324 will receive a 1.8 volt signal through the collector of transistor Q11. Charge pump voltage inverter 324 will produce a -1.8 volt signal at terminal DC4. This is voltage signal - VDC. Voltage signal -VDC will charge capacitor C12.
  • Capacitor C10, diodes D12, D13, capacitor C11 and R16 operate as a second charge pump.
  • One skilled in the art will be able to show that the voltage at the cathode of diode D13 is equal to
  • Diodes D12 and D13 are selected to have a voltage drop of 0.7 volts, giving a voltage of 2.2 volts (2 x 1.8 - 2 x 0.7). Since a '1 ' bit is being transmitted during this time, data off signal 338 will be low and will have a voltage equal to -VDC ( -1.8 volts), which is supplied to the negative power input terminal VSS of microcontroller 326.
  • the voltage across capacitor C11 and R16 is approximately 4 volts (2.2 + 1.8) and capacitor C11 will charge to 4 volts.
  • the charge across capacitor C11 is used only when transistor Q8 is on.
  • Voltage signal VAA at terminal DC5 will be equal to this voltage plus the voltage across capacitor C11 and will be approximately 5.8 volts (1.8 + 4).
  • the derivation of voltage VAA here is based on idealized operation of the components in DC power supply block 310 and ignores voltage drops through various components. For example, a small voltage will be dropped in transistor Q11 even when it is fully saturated, with the result that the voltage at terminal Vin of charge pump voltage inverter 324 will be slightly less than 1.8 volts. In addition, a small voltage will be dropped in resistor R16 while capacitor C11 is charging and when capacitor C11 is being used to provide voltage signal VAA.
  • DC power supply block 310 requires a measurable amount of current icharge from terminal AC1 to charge capacitors C8, C12 and C11 during positive half waves of AC power signal 28.
  • the magnitude of current icharge will depend primarily on the size of capacitors C8, C12 and C11 and other characteristics of DC power supply 310.
  • the magnitude of current icharge may be measured or calculated by known methods.
  • DC power supply block 310 may receive current icharge from terminal AC1 only when load current signal 346 has a magnitude larger than current icharge.
  • Capacitor C7 begins to charge when transistor Q5 turns off at the beginning of the transmission of a '1' bit.
  • the time between the beginning of the transmission of a '1' bit and between the turn on of transistor Q9 will be defined by the time constant of resistor R14 and capacitor C7. This time constant is selected to ensure that transistor Q9 does not switch on until after time t6.
  • Power supply control signal 344 is used to discharge capacitor C7, thereby switching transistor Q9 off prior to time t7. Normally, power supply control signal 344 is held low by microcontroller 326 and transistor Q12 is held off. When transistor Q9 is to be switched off, microcontroller 326 switches power supply control signal 344 to a high signal, causing transistor Q12 to switch on. Capacitor C7 discharges through capacitor Q12 and transistor Q9 switches off.
  • Figure 30i shows power supply control signal 344.
  • Figure 30j shows the on/off status of transistor Q9.
  • Control signal generation block 84c may be used to produce a control signal of almost any shape by programming microcontroller 90' to produce an appropriate PWM signal 102.
  • Figures 31a - 31c which are drawn with a common time scale but are out of scale with respect to the magnitude of the signals shown.
  • Figure 31a shows AC power signal 28.
  • Figure 31b shows a control signal 32b.
  • Figure 31c shows a modified power signal 30b corresponding to control signal 32b.
  • modified power signal 30b When modified power signal 30b is received by a receiver, the presence or absence of the high frequency component of control signal 32b may easily be detected by using a high pass filter, or more preferably, a band pass filter, which allows the high frequency component to be isolated and then detected. It has been found that such a receiver can detect the data encoded in modified power signal 30b with great accuracy. In particular, such a receiver is not susceptible to errors resulting from fluctuations and drifts in the voltage of modified power signal 30b. A person skilled in the art will be capable of designing a receiver capable of receiving modified power signal 30b and detecting control signal 32b. The use of high frequency control signal in a signalling system according to the present invention has another substantial benefit not found in prior art systems.
  • modified power signal 30b is produced by removing energy corresponding to the magnitude of control signal 32b from AC power signal 28, the resulting high frequency component of modified power signal 30b only propagates from the transmitter to the load, and is not propagated back to the power supply. As a result, AC power signal 28 is not affected by the frequency of control signal 30b and no filters are required to remove control 30b from AC power signal 28.
  • the AC power signal is modified by adding power corresponding to the desired high frequency signal to the AC power signal. This results in the high frequency signal propagating in both the load and supply directions from the transmitter.
  • Receivers 40 and 40' described earlier are not suitable to detect data transmitted in such a modified power signal 32c.
  • a person skilled in the art will be capable of making a receiver which can detect the frequency modulated signal.
  • such a receiver may sample modified power signal 30c at a frequency at least twice that of the high frequency used to modulate control signal 32c.
  • control signal 32b is configured such that the area A under the positive half wave of the voltage curve of modified power signal 30c is approximately equal to the area B under the negative half wave of the voltage curve of modified power signal 30c.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Selective Calling Equipment (AREA)
  • Remote Monitoring And Control Of Power-Distribution Networks (AREA)

Abstract

Dans cette invention, un émetteur émet un signal de commande qui, de préférence, ne contient pas de composante de courant continu (c'est-à-dire que son amplitude moyenne est 0). Ce signal de commande est synchronisé avec un signal de courant alternatif (CA) sur la ligne CA, et y est incorporé par sommation afin qu'un signal CA modifié soit produit. Un émetteur possédant un circuit de chute de charge actif conçu pour fournir un signal de commande à forme précise, et une forme d'onde possédant une faible amplitude pendant la partie la plus élevée du signal de courant CA permettent de diminuer la consommation de puissance du système de transmission de signaux. Un récepteur calcule la zone sous chaque demi-onde positive du signal de puissance modifié et la compare à une valeur seuil pour distinguer entre les bits «0» et «1». Dans un autre mode de réalisation, un filtre passe-bas asymétrique est incorporé dans le récepteur. Le signal filtré est atténué (à une amplitude choisie) lorsqu'un bit «1» (ou «0») est reçu. Ce récepteur détecte l'atténuation en mesurant la durée pendant laquelle le signal filtré dépasse l'amplitude choisie.
PCT/CA2001/000671 2000-05-09 2001-05-08 Systeme de transmission de signaux sur ligne d'alimentation en courant alternatif WO2001090828A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001258119A AU2001258119A1 (en) 2000-05-09 2001-05-08 Ac power line signalling system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US20306500P 2000-05-09 2000-05-09
US60/203,065 2000-05-09

Publications (2)

Publication Number Publication Date
WO2001090828A2 true WO2001090828A2 (fr) 2001-11-29
WO2001090828A3 WO2001090828A3 (fr) 2002-04-04

Family

ID=22752334

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2001/000671 WO2001090828A2 (fr) 2000-05-09 2001-05-08 Systeme de transmission de signaux sur ligne d'alimentation en courant alternatif

Country Status (2)

Country Link
AU (1) AU2001258119A1 (fr)
WO (1) WO2001090828A2 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007045946A1 (fr) * 2005-10-17 2007-04-26 Indesit Company S.P.A. Procédé, dispositifs et système pour transmettre des informations sur une ligne électrique d'alimentation
US7825822B2 (en) 2005-04-01 2010-11-02 Cepia, Llc System and method for extracting and conveying modulated AC signal information
WO2011064495A1 (fr) * 2009-11-24 2011-06-03 Hmi Innovation Dispositif d'eclairage a del incorporant une commande amelioree
DE102010046964A1 (de) * 2010-09-29 2012-03-29 Infineon Technologies Austria Ag Ladungspumpe
CN102681453A (zh) * 2012-05-18 2012-09-19 广东美的电器股份有限公司 电加热控制装置及其控制方法
EP2464027A4 (fr) * 2009-08-06 2016-07-13 Sumitomo Electric Industries Dispositif de communication sur ligne électrique, circuit d'alimentation électrique avec fonction de communication, appareil électrique et système de commande et de surveillance
WO2016114724A1 (fr) * 2015-01-16 2016-07-21 Jozef Sedlak Connexion pour la réalisation de la voie de communication dans la ligne d'alimentation 230v au moyen de modulation et démodulation de la valeur moyenne du demi-cycle de tension d'alimentation
US10667358B1 (en) 2018-03-13 2020-05-26 Keith Bernard Marx Load control using AC signalling with unique signatures

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4328482A (en) * 1977-11-17 1982-05-04 Consumer Electronic Products Corporation Remote AC power control with control pulses at the zero crossing of the AC wave
US4329678A (en) * 1980-03-24 1982-05-11 Hatfield Jerry M Method and apparatus for remotely controlling an electrical appliance
US4400688A (en) * 1976-01-16 1983-08-23 New England Power Service Company Method and apparatus for communication over electric power lines
EP0645870A1 (fr) * 1993-09-24 1995-03-29 Seb S.A. Procédé et circuit de transmission d'informations issues de capteurs sur un fil conducteur électrique

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043927A (ja) * 1983-08-22 1985-03-08 Matsushita Electric Ind Co Ltd 配電線信号注入装置の過渡現象サ−ジ電圧保護装置
JP2659165B2 (ja) * 1993-07-30 1997-09-30 大倉電気株式会社 需要家内低圧電力線による通信方式

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4400688A (en) * 1976-01-16 1983-08-23 New England Power Service Company Method and apparatus for communication over electric power lines
US4328482A (en) * 1977-11-17 1982-05-04 Consumer Electronic Products Corporation Remote AC power control with control pulses at the zero crossing of the AC wave
US4329678A (en) * 1980-03-24 1982-05-11 Hatfield Jerry M Method and apparatus for remotely controlling an electrical appliance
EP0645870A1 (fr) * 1993-09-24 1995-03-29 Seb S.A. Procédé et circuit de transmission d'informations issues de capteurs sur un fil conducteur électrique

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 009, no. 169 (E-328), 13 July 1985 (1985-07-13) & JP 60 043927 A (MATSUSHITA DENKI SANGYO KK), 8 March 1985 (1985-03-08) *
PATENT ABSTRACTS OF JAPAN vol. 1995, no. 05, 30 June 1995 (1995-06-30) & JP 07 046760 A (OHKURA ELECTRIC CO LTD;OTHERS: 01), 14 February 1995 (1995-02-14) *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7825822B2 (en) 2005-04-01 2010-11-02 Cepia, Llc System and method for extracting and conveying modulated AC signal information
WO2007045946A1 (fr) * 2005-10-17 2007-04-26 Indesit Company S.P.A. Procédé, dispositifs et système pour transmettre des informations sur une ligne électrique d'alimentation
EP2464027A4 (fr) * 2009-08-06 2016-07-13 Sumitomo Electric Industries Dispositif de communication sur ligne électrique, circuit d'alimentation électrique avec fonction de communication, appareil électrique et système de commande et de surveillance
WO2011064495A1 (fr) * 2009-11-24 2011-06-03 Hmi Innovation Dispositif d'eclairage a del incorporant une commande amelioree
DE102010046964A1 (de) * 2010-09-29 2012-03-29 Infineon Technologies Austria Ag Ladungspumpe
US8432215B2 (en) 2010-09-29 2013-04-30 Infineon Technologies Austria Ag Charge pump
CN102681453A (zh) * 2012-05-18 2012-09-19 广东美的电器股份有限公司 电加热控制装置及其控制方法
WO2016114724A1 (fr) * 2015-01-16 2016-07-21 Jozef Sedlak Connexion pour la réalisation de la voie de communication dans la ligne d'alimentation 230v au moyen de modulation et démodulation de la valeur moyenne du demi-cycle de tension d'alimentation
US10667358B1 (en) 2018-03-13 2020-05-26 Keith Bernard Marx Load control using AC signalling with unique signatures

Also Published As

Publication number Publication date
WO2001090828A3 (fr) 2002-04-04
AU2001258119A1 (en) 2001-12-03

Similar Documents

Publication Publication Date Title
AU2005214767B2 (en) Multiple-input electronic ballast with processor
US6392368B1 (en) Distributed lighting control system
US6842668B2 (en) Remotely accessible power controller for building lighting
US6218787B1 (en) Remote dimming control system for a fluorescent ballast utilizing existing building wiring
US7211968B2 (en) Lighting control systems and methods
US7009348B2 (en) Multiple channel ballast and networkable topology and system including power line carrier applications
CN105247963B (zh) 对负载控制设备的输入电容器充电
US20060284728A1 (en) Pulse width modulation data transfer over commercial and residential power lines method, transmitter and receiver apparatus
CA2512421C (fr) Ballast a deux niveaux lumineux
EP0786193A1 (fr) Circuit de ballast
EP1767067A1 (fr) Reglage de l'intensite lumineuse d'une lampe par derivation d'interruption de phase
WO2001090828A2 (fr) Systeme de transmission de signaux sur ligne d'alimentation en courant alternatif
CN105830535A (zh) 智能照明设备及其方法和系统
EP0046395A1 (fr) Dispositif atténuateur d'éclairage pour lampes électriques à décharge
US5128592A (en) High frequency ballast for gaseous discharge lamps
WO2003102890A2 (fr) Regulateur a multiples canaux, topologie pouvant etre mise en reseau et systeme comprenant des applications de courant porteur en ligne
JP4661763B2 (ja) 光伝送システム
KR102097553B1 (ko) 전력선 통신을 이용하는 전력 제어 방법
EP0801519B1 (fr) Un circuit nouveau pour améliorer le facteur de puissance et l'efficacité de la lampe
KR100446188B1 (ko) 제로크로스 직후의 낮은 전압부분에서의 위상제어를이용한 폐회로 전력선 데이터 통신
WO2009001267A2 (fr) Système de commande d'une pluralité de sources lumineuses
Lohaus et al. A comparison of receiver topologies for digital load-side transmission in general LED lighting
CN111491421A (zh) 基于plc-bus技术的花灯驱动系统
JPH09161972A (ja) 照明器具の点灯制御システム
ITME940004A1 (it) Economizzatore e limitatore di potenza per termoelettrodomestici, basato su sistema automatico modulare radiocontrollato

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 69(1) EPC

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase in:

Ref country code: JP