WO2001086715A3 - Verfahren zum verlöten einer ersten metallschicht, die eine dicke von weniger als 5 $g(m)m aufweist, mit einer zweiten metallschicht, löteinrichtung und halbleiterchip-montagevorrichtung - Google Patents

Verfahren zum verlöten einer ersten metallschicht, die eine dicke von weniger als 5 $g(m)m aufweist, mit einer zweiten metallschicht, löteinrichtung und halbleiterchip-montagevorrichtung Download PDF

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Publication number
WO2001086715A3
WO2001086715A3 PCT/DE2001/001651 DE0101651W WO0186715A3 WO 2001086715 A3 WO2001086715 A3 WO 2001086715A3 DE 0101651 W DE0101651 W DE 0101651W WO 0186715 A3 WO0186715 A3 WO 0186715A3
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WIPO (PCT)
Prior art keywords
metal layer
soldering
thickness
semiconductor chip
less
Prior art date
Application number
PCT/DE2001/001651
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English (en)
French (fr)
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WO2001086715A2 (de
Inventor
Detlef Houdeau
Holger Huebner
Vaidyanathan Kripesh
Original Assignee
Infineon Technologies Ag
Detlef Houdeau
Holger Huebner
Vaidyanathan Kripesh
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Application filed by Infineon Technologies Ag, Detlef Houdeau, Holger Huebner, Vaidyanathan Kripesh filed Critical Infineon Technologies Ag
Publication of WO2001086715A2 publication Critical patent/WO2001086715A2/de
Publication of WO2001086715A3 publication Critical patent/WO2001086715A3/de

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Abstract

Die Erste Metallschicht (107) wird mit der zweiten Metallschicht (102) unter Verwendung von Lotmaterial (104) verlötet, wobei nur ein Teil der ersten Metallschicht (107) in eine oder mehrere Intermetallische Phasen (122) mit dem verwendeten Lotmaterial umgewandelt wird.
PCT/DE2001/001651 2000-05-05 2001-05-03 Verfahren zum verlöten einer ersten metallschicht, die eine dicke von weniger als 5 $g(m)m aufweist, mit einer zweiten metallschicht, löteinrichtung und halbleiterchip-montagevorrichtung WO2001086715A2 (de)

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DE10021870 2000-05-05
DE10021870.9 2000-05-05

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WO2001086715A2 WO2001086715A2 (de) 2001-11-15
WO2001086715A3 true WO2001086715A3 (de) 2002-09-06

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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6740544B2 (en) 2002-05-14 2004-05-25 Freescale Semiconductor, Inc. Solder compositions for attaching a die to a substrate
EP2340554B1 (de) * 2008-09-18 2017-05-10 Imec Verfahren und systeme zum bonden von materialien
FR2964094B1 (fr) * 2010-08-31 2012-09-28 Commissariat Energie Atomique Assemblage d'objets par l'intermediaire d'un cordon de scellement comportant des composes intermetalliques
DE102014218426A1 (de) * 2014-09-15 2016-03-17 Siemens Aktiengesellschaft Baugruppe mit mindestens zwei Tragkörpern und einen Lotverbund
DE102015108668B4 (de) * 2015-06-02 2018-07-26 Rogers Germany Gmbh Verfahren zur Herstellung eines Verbundmaterials

Citations (4)

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Publication number Priority date Publication date Assignee Title
US5349500A (en) * 1992-08-19 1994-09-20 Sheldahl, Inc. Direct application of unpackaged integrated circuit to flexible printed circuit
DE19532250A1 (de) * 1995-09-01 1997-03-06 Daimler Benz Ag Anordnung und Verfahren zum Diffusionslöten eines mehrschichtigen Aufbaus
EP0918354A2 (de) * 1997-11-20 1999-05-26 Texas Instruments Incorporated Scheibenbereichsanordnung von Packungen in Chip-Grösse
EP0997942A2 (de) * 1998-10-30 2000-05-03 Shinko Electric Industries Co. Ltd. Chipgrosses Halbleitergehäuse und seine Herstellung

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5349500A (en) * 1992-08-19 1994-09-20 Sheldahl, Inc. Direct application of unpackaged integrated circuit to flexible printed circuit
DE19532250A1 (de) * 1995-09-01 1997-03-06 Daimler Benz Ag Anordnung und Verfahren zum Diffusionslöten eines mehrschichtigen Aufbaus
EP0918354A2 (de) * 1997-11-20 1999-05-26 Texas Instruments Incorporated Scheibenbereichsanordnung von Packungen in Chip-Grösse
EP0997942A2 (de) * 1998-10-30 2000-05-03 Shinko Electric Industries Co. Ltd. Chipgrosses Halbleitergehäuse und seine Herstellung

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