WO2001084330A2 - A method and system for multi-channel transfer of data and control information - Google Patents
A method and system for multi-channel transfer of data and control information Download PDFInfo
- Publication number
- WO2001084330A2 WO2001084330A2 PCT/US2001/014336 US0114336W WO0184330A2 WO 2001084330 A2 WO2001084330 A2 WO 2001084330A2 US 0114336 W US0114336 W US 0114336W WO 0184330 A2 WO0184330 A2 WO 0184330A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- cell
- bridge
- data
- queue
- bus
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/40—Network security protocols
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/14—Multichannel or multilink protocols
Definitions
- the present invention relates to bi-directional communication over a network
- DSPs Digital Signal Processors
- channels such as, for example, a single DSO or time division multiplexed (TDM) slot,
- the executive program (small kernel) and application.
- the executive programs reserve
- Channels may take one of the following forms: one channel carried on a physical
- wire or wireless medium between systems also referred to as a circuit
- time divisional
- TDM multiplexed
- sources are transmitted over a single cable by modulating each signal on a carrier at
- a current method to implement multiple services or multiple channels involves
- a bridge is connected to the bridge bus and to a system bus.
- a memory is connected to the bridge.
- Figure 1 is a system architecture of one embodiment for a multi-channel data
- Figure 2 is a block diagram of one embodiment for a processing chip of Figure 1;
- Figure 3 is a block diagram of another embodiment for a multi-channel data
- Figure 4 is a block diagram of one embodiment for a bridge of Figure 1;
- Figure 5 is a block diagram of one embodiment for a buffer memory of Figure 1;
- Figure 6 is a block diagram of one embodiment for a bus data cell
- Figure 7 is a block diagram of one embodiment for a bus control cell
- Figure 8 is a flow diagram of one embodiment for the transmission of cells over a
- Figure 9 is a flow diagram of one embodiment for the receiving of cells over the
- a number of processing chips are described.
- a bridge is connected to the bridge bus and to a system bus.
- a memory is connected to the bridge.
- the bridge is connected to the bridge.
- system bus interface connected to the system bus, a memory interface
- a cell initiated serial interface connected to the system bus interface
- the present invention also relates to apparatus for performing the operations
- This apparatus may be specially constructed for the required purposes, or it
- Such a computer program may be stored in the computer. Such a computer program may be stored in
- a computer readable storage medium such as, but is not limited to, any type of disk
- ROMs read only memory
- RAMs random access memories
- EPROMs EPROMs
- EEPROMs electrically erasable programmable read-only memory
- magnetic or optical cards or any type of media suitable for storing electronic instructions
- Figure 1 is a system architecture of one embodiment for a multi-channel, multi-service
- system 100 Referring to Figure 1, system element 102 is connected via system bus 104
- bridge 106 to a plurality of processing chips 108, 110, 112, 114.
- bridge 106 to a plurality of processing chips 108, 110, 112, 114.
- System element may be another bridge 106
- Bridge 106 is connected via bus 118 to the
- processing chips 108-114 are connected
- TDM time division multiplexing
- chips 108-114 may be connected to a digital signal 0 (DS0) interface or
- TDM interface 122 is connected to a
- TDM interface
- TDM is a base-band technology in which individual channels of data or voice are
- Each input channel receives an interleave time segment in order that all channels
- transfer system 100 supports telecommunication and-data communication applications.
- Multi-channel data transfer system 100 enables the dynamic
- the operating system automatically defines
- bridge 106 may interface up to six chips 108-113 to bus 104.
- bridge 106 is a 32-bit Peripheral Component Interconnect (PCI) 2.1
- bridge bus 118 is a cell-based serial
- FIG. 2 is a block diagram of one embodiment for a processing chip 108.
- processing chip 108 contains clusters 202 and main processor 204. Each cluster 202
- BFUs basic functional units
- Main processor 204 is configured to perform all control code and operations including receiving control messages from host 102 and allocating channels to various clusters
- Processing chip 108 also includes shared static random access memory (shared
- Shared SRAM 206 may be accessed directly by all the cluster processors
- An instruction store contained within BFUs 210 may also
- Shared SRAM 206 is used for storing operating system and
- Each cluster 202 contains cluster SRAM 212.
- Cluster SRAM 212 is responsible for
- Cluster SRAM 212 maintaining channel data running on each individual cluster 202.
- the operating system of system 100 uses the
- External dynamic random access memory (DRAM) 214 may be used for
- each processing chip 108 includes two line side ports 216
- bus ports 218 are used for packet side data and control
- host port 220 is used to communicate with the host 102 and is
- Figure 3 is a block diagram of another embodiment for a multi-channel data
- bridge 106 receives cells from system bus 104.
- the cells are transmitted (TX) from bridge 106 via bridge bus 118 to processing
- Cells may be either control/status cells or data cells.
- chip 108 subsystems operate using a write-oriented
- Both data and control are transferred in fixed length, atomic cells.
- Both data and control are transferred in fixed length, atomic cells.
- the cells are 48 bytes in length in which each cell has an eight-byte header and a forty-
- bridge bus 118 is a point-to-point serial bus with
- Bridge bus 118 is "always on" in that there
- chip 108 is no request-grant protocol, and data is continuously transferred. If chip 108 or the
- bridge 106 has no valid data to send, null cells are transferred on bridge bus 118.
- null cells are both generated and filtered (depending on the direction) by logic that
- chip 108 and bridge 106 and bridge 106 filters out null cells before transmitting data or
- bridge 106 supports up to six processing chips 108, or a
- Each chip 108 is capable of
- Bridge 106 is unaware of the contents of each cell and makes queuing decisions based upon the contents of the cell header. In one embodiment,
- bridge 106 treats all cells similarly, with data and control cells following the same data
- data and control cells may follow
- FIG. 4 is a block diagram of one embodiment for bridge 106. Referring to
- bridge 106 includes system bus interface 402, memory interface 420, cell
- System bus interface 402 includes
- System interface 404 and system-local interface 406.
- System interface 404 performs the
- System interface 404 contains the
- System-local interface 406 is connected to
- System-local interface 406 also has a separate bus for register access so that these
- Memory interface 420 includes buffer memory interface 422 and MUX 424.
- buffer memory interface 422 provides a 32-bit data path interface to a
- SDRAM synchronous dynamic random access memory
- buffer memory 116 may be any storage device such as, for example,
- buffer memory interface 422 moves
- Cell initiated serial interface 430 includes bridge bus interface 432.
- interface 432 receives and transmits cells from and to processing chips 108-113.
- bus interface 432 uses FIFO buffers 434 to adapt to bridge bus 118 clock speed. In one
- three clock domains are maintained within bridge 106. The first is the
- the third clock domain is the bridge bus 118 clock domain, which
- Bridge bus interface 432 also resides between bridge bus and system clocks.
- Control logic 440 includes descriptor manager 442, pointer manager 444, and
- Descriptor manager 442 manages the cell descriptors that are locations
- descriptors is maintained in buffer memory 116 and a smaller set of descriptors is
- Pointer manager 444 manages the head and tail pointers for all queues that are
- each queue is
- Sequencer 446 coordinates the interaction of system bus interface 402, memory
- Sequencer 446 allocates access to the memory to each of the requesters, and communicates with the
- Figure 5 is a block diagram of one embodiment for buffer memory 116. In one
- buffer memory 116 is a synchronous DRAM, organized as x32 memory
- buffer memory 116 is maintained by pointer manipulation and is
- each descriptor is a 32-bit pointer to a cell buffer in host
- Receive data descriptors 510 and receive control descriptors 512 each store 4K
- descriptors each descriptor is 4 bytes. The two separate pools of available descriptors
- transmit data buffer 502 receive data buffer 504, transmit
- control buffer 506, and receive control buffer 508 are segmented into fixed length
- each segment is programmable at system startup.
- Each processing chip 108-113 supports multiple channels, each of which is
- a programmable threshold value may cause back-pressure to be asserted to
- descriptors are maintained as a circular queue, with bridge 106 managing the head
- bridge 106 fetches a descriptor from
- buffer queue in host memory, which is also a circular buffer. As the host services the
- Buffer memory interface 422 operates synchronous to system bus 104 clock.
- Buffer memory interface 422 allows accesses by requestors in a time-slot fashion in
- requesters may be assigned one or more time-slots based upon the requester's
- Requestors may be assigned one or more timeslots based on their
- each timeslot has a duration of 20 clock cycles (or
- the cells arrive at their respective time slots and each waits for transfer
- the worst case latency for a control cell may be written as:
- cells for each processing chip 108 are
- the queue for each processing chip 108 are enqueued and dequeued for a fixed amount
- buffers for processing chip 108 are
- buffers for processing chip 109 are
- Bridge bus 118 runs
- bus 118 is less than the time taken to make a complete run through the 50 time-slots
- the cell needs to wait for its corresponding processing
- time-slot (which is the total number of time-slots minus 1)
- the worst case latency for a data cell may be
- the worst case latency for a control cell may be written as:
- FIG. 6 is a block diagram of one embodiment for bus data cell 600. Referring
- bus data cell 600 is 48-bytes long, with an 8-byte header 620 and a 40-byte
- Header 620 supports multiple processing chip 108-based subsystems,
- Each subsystem may have multiple processing chips
- chip number 610 which in turn may have multiple channels
- channel number 606. up to 256 channels per each
- FIG. 7 is a block diagram of one embodiment for bus control cell 700. Referring
- bus control cell 700 is 48-bytes long, with an 8-byte header 720 and a 40-byte
- Header 720 supports multiple processing chip 108-based subsystems,
- Each subsystem may have multiple processing chips
- GCN Global Channel Number
- Bridge 106 is supplied with separate control and data
- Each descriptor is a 32 pointer to a cell buffer in the memory of host 102.
- host 102 replenishes the bridge descriptors in groups of 8 for
- This group of 8 descriptors forms a descriptor update cell.
- Descriptor 0 is the first descriptor used, and descriptor 7 is the last descriptor.
- the first four descriptors in the cell are dummy pointers and are not placed in the descriptor
- Figure 8 is a flow diagram of one embodiment for transmission of cells over
- System interface 404 and is burst into FIFO stack 408.
- system bus interface 404 and is burst into FIFO stack 408.
- system bus interface 404 and is burst into FIFO stack 408.
- sequencer 446 determines the proper queue to place the
- Sequencer 446 determines which of the chips 108-113 is to be used and determines
- system-local interface 406 writes the cell into the proper
- System-local interface 406 writes the cell into the
- the cell is dequeued from buffer memory 116 and placed
- bridge bus interface 432 transmits the cell to the
- bridge bus interface 432 inserts a null cell and bursts the null
- Figure 9 is a flow diagram of one embodiment for receiving of cells over bridge
- Bridge bus interface 432 places the cell in the appropriate FIFO queue
- bridge bus interface 432 removes the null cell and no further
- sequencer 446 determines the proper receive queue 504
- buffer memory 116 within buffer memory 116.
- the descriptor is the address or buffer location within host
- Sequencer 446 instructs system-local interface 406 where
- the cell is to be sent on system bus 104.
- system-local interface 406 bursts the cell to system
- System interface 404 places the burst cell in FIFO buffer 408.
- the cell is received on system bus 104.
- System interface 404 bursts the descriptor and the
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Security & Cryptography (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Bus Control (AREA)
- Small-Scale Networks (AREA)
- Selective Calling Equipment (AREA)
- Communication Control (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AT01932961T ATE310276T1 (en) | 2000-05-03 | 2001-05-03 | BUS BRIDGE AND SYSTEM FOR MULTI-CHANNEL TRANSMISSION OF DATA AND CONTROL INFORMATION |
EP01932961A EP1279103B1 (en) | 2000-05-03 | 2001-05-03 | Bridge and system for multi-channel transfer of data and control information |
AU2001259440A AU2001259440A1 (en) | 2000-05-03 | 2001-05-03 | A method and system for multi-channel transfer of data and control information |
DE60115010T DE60115010T2 (en) | 2000-05-03 | 2001-05-03 | BUS BRIDGE AND SYSTEM FOR MULTI-CHANNEL TRANSMISSION OF DATA AND CONTROL INFORMATION |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/564,592 US7107383B1 (en) | 2000-05-03 | 2000-05-03 | Method and system for multi-channel transfer of data and control information |
US09/564,592 | 2000-05-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2001084330A2 true WO2001084330A2 (en) | 2001-11-08 |
WO2001084330A3 WO2001084330A3 (en) | 2002-06-13 |
Family
ID=24255107
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2001/014336 WO2001084330A2 (en) | 2000-05-03 | 2001-05-03 | A method and system for multi-channel transfer of data and control information |
Country Status (6)
Country | Link |
---|---|
US (2) | US7107383B1 (en) |
EP (1) | EP1279103B1 (en) |
AT (1) | ATE310276T1 (en) |
AU (1) | AU2001259440A1 (en) |
DE (1) | DE60115010T2 (en) |
WO (1) | WO2001084330A2 (en) |
Cited By (1)
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---|---|---|---|---|
US7334074B2 (en) | 2000-05-03 | 2008-02-19 | Broadcom Corporation | Method and system for multi-channel transfer of data and control |
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US6959372B1 (en) * | 2002-02-19 | 2005-10-25 | Cogent Chipware Inc. | Processor cluster architecture and associated parallel processing methods |
US7085866B1 (en) * | 2002-02-19 | 2006-08-01 | Hobson Richard F | Hierarchical bus structure and memory access protocol for multiprocessor systems |
US7096304B2 (en) * | 2003-12-31 | 2006-08-22 | Micron Technology, Inc. | Apparatus and method for managing voltage buses |
US7929368B2 (en) * | 2008-12-30 | 2011-04-19 | Micron Technology, Inc. | Variable memory refresh devices and methods |
US8615621B2 (en) * | 2009-12-24 | 2013-12-24 | St-Ericsson Sa | Memory management |
TW201308200A (en) * | 2011-08-12 | 2013-02-16 | Ite Tech Inc | Bridge, system and the method for prefetching and discarding data thereof |
US9838500B1 (en) * | 2014-03-11 | 2017-12-05 | Marvell Israel (M.I.S.L) Ltd. | Network device and method for packet processing |
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- 2001-05-03 EP EP01932961A patent/EP1279103B1/en not_active Expired - Lifetime
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- 2001-05-03 WO PCT/US2001/014336 patent/WO2001084330A2/en active IP Right Grant
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Also Published As
Publication number | Publication date |
---|---|
ATE310276T1 (en) | 2005-12-15 |
WO2001084330A3 (en) | 2002-06-13 |
DE60115010D1 (en) | 2005-12-22 |
EP1279103B1 (en) | 2005-11-16 |
US7334074B2 (en) | 2008-02-19 |
AU2001259440A1 (en) | 2001-11-12 |
US7107383B1 (en) | 2006-09-12 |
EP1279103A2 (en) | 2003-01-29 |
US20070016713A1 (en) | 2007-01-18 |
DE60115010T2 (en) | 2006-08-03 |
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JP3431308B2 (en) | ATM switching equipment |
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