DE60115010D1 - BUS BRIDGE AND SYSTEM FOR MULTI-CHANNEL TRANSMISSION OF DATA AND CONTROL INFORMATION - Google Patents

BUS BRIDGE AND SYSTEM FOR MULTI-CHANNEL TRANSMISSION OF DATA AND CONTROL INFORMATION

Info

Publication number
DE60115010D1
DE60115010D1 DE60115010T DE60115010T DE60115010D1 DE 60115010 D1 DE60115010 D1 DE 60115010D1 DE 60115010 T DE60115010 T DE 60115010T DE 60115010 T DE60115010 T DE 60115010T DE 60115010 D1 DE60115010 D1 DE 60115010D1
Authority
DE
Germany
Prior art keywords
data
control information
channel transmission
bus bridge
bridge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60115010T
Other languages
German (de)
Other versions
DE60115010T2 (en
Inventor
Sundar Rajan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Publication of DE60115010D1 publication Critical patent/DE60115010D1/en
Application granted granted Critical
Publication of DE60115010T2 publication Critical patent/DE60115010T2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/14—Multichannel or multilink protocols

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)
  • Selective Calling Equipment (AREA)
  • Communication Control (AREA)

Abstract

A system and method for transferring information in a multi-channel, point-to-point environment are described. In one embodiment, a number of processing chips are connected to a bridge bus. A bridge is connected to the bridge bus and to a system bus. In addition, a memory is connected to the bridge.
DE60115010T 2000-05-03 2001-05-03 BUS BRIDGE AND SYSTEM FOR MULTI-CHANNEL TRANSMISSION OF DATA AND CONTROL INFORMATION Expired - Lifetime DE60115010T2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/564,592 US7107383B1 (en) 2000-05-03 2000-05-03 Method and system for multi-channel transfer of data and control information
US564592 2000-05-03
PCT/US2001/014336 WO2001084330A2 (en) 2000-05-03 2001-05-03 A method and system for multi-channel transfer of data and control information

Publications (2)

Publication Number Publication Date
DE60115010D1 true DE60115010D1 (en) 2005-12-22
DE60115010T2 DE60115010T2 (en) 2006-08-03

Family

ID=24255107

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60115010T Expired - Lifetime DE60115010T2 (en) 2000-05-03 2001-05-03 BUS BRIDGE AND SYSTEM FOR MULTI-CHANNEL TRANSMISSION OF DATA AND CONTROL INFORMATION

Country Status (6)

Country Link
US (2) US7107383B1 (en)
EP (1) EP1279103B1 (en)
AT (1) ATE310276T1 (en)
AU (1) AU2001259440A1 (en)
DE (1) DE60115010T2 (en)
WO (1) WO2001084330A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7107383B1 (en) * 2000-05-03 2006-09-12 Broadcom Corporation Method and system for multi-channel transfer of data and control information
US6959372B1 (en) * 2002-02-19 2005-10-25 Cogent Chipware Inc. Processor cluster architecture and associated parallel processing methods
US7085866B1 (en) * 2002-02-19 2006-08-01 Hobson Richard F Hierarchical bus structure and memory access protocol for multiprocessor systems
US7096304B2 (en) * 2003-12-31 2006-08-22 Micron Technology, Inc. Apparatus and method for managing voltage buses
US7929368B2 (en) * 2008-12-30 2011-04-19 Micron Technology, Inc. Variable memory refresh devices and methods
US8615621B2 (en) * 2009-12-24 2013-12-24 St-Ericsson Sa Memory management
TW201308200A (en) * 2011-08-12 2013-02-16 Ite Tech Inc Bridge, system and the method for prefetching and discarding data thereof
US9838500B1 (en) * 2014-03-11 2017-12-05 Marvell Israel (M.I.S.L) Ltd. Network device and method for packet processing

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US5588125A (en) * 1993-10-20 1996-12-24 Ast Research, Inc. Method and apparatus for increasing bus bandwidth on a system bus by inhibiting interrupts while posted I/O write operations are pending
EP0654743A1 (en) 1993-11-19 1995-05-24 International Business Machines Corporation Computer system having a DSP local bus
US6334219B1 (en) * 1994-09-26 2001-12-25 Adc Telecommunications Inc. Channel selection for a hybrid fiber coax network
US5630094A (en) 1995-01-20 1997-05-13 Intel Corporation Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions
US5600646A (en) * 1995-01-27 1997-02-04 Videoserver, Inc. Video teleconferencing system with digital transcoding
US5696910A (en) * 1995-09-26 1997-12-09 Intel Corporation Method and apparatus for tracking transactions in a pipelined bus
US5778180A (en) 1995-11-06 1998-07-07 Sun Microsystems, Inc. Mechanism for reducing data copying overhead in protected memory operating systems
US6044225A (en) 1996-03-13 2000-03-28 Diamond Multimedia Systems, Inc. Multiple parallel digital data stream channel controller
US5911055A (en) * 1996-06-05 1999-06-08 Compaq Computer Corporation Using subordinate bus devices that are connected to a common bus
GB9613473D0 (en) 1996-06-27 1996-08-28 Mitel Corp ATM cell transmit priority allocator
US5983291A (en) * 1996-09-24 1999-11-09 Cirrus Logic, Inc. System for storing each of streams of data bits corresponding from a separator thereby allowing an input port accommodating plurality of data frame sub-functions concurrently
US5774683A (en) * 1996-10-21 1998-06-30 Advanced Micro Devices, Inc. Interconnect bus configured to implement multiple transfer protocols
US5805845A (en) * 1996-10-21 1998-09-08 Advanced Micro Devices, Inc. Method for loading memory with program and data information from PC memory across a bridging bus
US5832245A (en) * 1996-10-21 1998-11-03 Advanced Micro Devices, Inc. Method for isochronous flow control across an inter-chip bus
DE69721474T2 (en) * 1996-10-31 2004-04-08 Texas Instruments Inc., Dallas A configurable expansion bus control unit
US5761462A (en) * 1996-12-13 1998-06-02 International Business Machines Corporation Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a data-processing system
US5826048A (en) * 1997-01-31 1998-10-20 Vlsi Technology, Inc. PCI bus with reduced number of signals
US6425033B1 (en) * 1997-06-20 2002-07-23 National Instruments Corporation System and method for connecting peripheral buses through a serial bus
US6078976A (en) * 1997-06-24 2000-06-20 Matsushita Electric Industrial Co., Ltd. Bridge device that prevents decrease in the data transfer efficiency of buses
US6108736A (en) * 1997-09-22 2000-08-22 Intel Corporation System and method of flow control for a high speed bus
US6189063B1 (en) * 1997-09-30 2001-02-13 Texas Instruments Incorporated Method and apparatus for intelligent configuration register access on a PCI to PCI bridge
US5996034A (en) * 1997-10-14 1999-11-30 Advanced Micro Devices, Inc. Bus bridge verification system including device independent bus monitors
US5964859A (en) * 1997-10-30 1999-10-12 Advanced Micro Devices, Inc. Allocatable post and prefetch buffers for bus bridges
JPH11238030A (en) * 1998-02-20 1999-08-31 Mitsubishi Electric Corp Pci-pci bridge and its fast-in fast-out memory
US6112311A (en) * 1998-02-20 2000-08-29 International Business Machines Corporation Bridge failover system
US6081863A (en) * 1998-03-13 2000-06-27 International Business Machines Corporation Method and system for supporting multiple peripheral component interconnect PCI buses by a single PCI host bridge within a computer system
US6295568B1 (en) * 1998-04-06 2001-09-25 International Business Machines Corporation Method and system for supporting multiple local buses operating at different frequencies
US6360289B2 (en) * 1998-04-14 2002-03-19 Micron Technology, Inc. System for autonomous configuration of peer devices
GB2337403A (en) 1998-05-11 1999-11-17 Gen Datacomm Adv Res Data communication
US6247086B1 (en) * 1998-11-12 2001-06-12 Adaptec, Inc. PCI bridge for optimized command delivery
JP3206570B2 (en) * 1998-11-12 2001-09-10 日本電気株式会社 PCI function expansion control device and PCI function expansion control method
US6078980A (en) * 1998-12-29 2000-06-20 Intel Corporation Regulating a data transfer time
US6311247B1 (en) * 1999-01-15 2001-10-30 Hewlett Packard Company System for bridging a system bus with multiple PCI buses
US6286074B1 (en) * 1999-03-24 2001-09-04 International Business Machines Corporation Method and system for reading prefetched data across a bridge system
TW514788B (en) * 1999-04-23 2002-12-21 Via Tech Inc Method of delayed transaction in bus system and device using the method
US6457091B1 (en) * 1999-05-14 2002-09-24 Koninklijke Philips Electronics N.V. PCI bridge configuration having physically separate parts
US6477646B1 (en) * 1999-07-08 2002-11-05 Broadcom Corporation Security chip architecture and implementations for cryptography acceleration
US6668299B1 (en) * 1999-09-08 2003-12-23 Mellanox Technologies Ltd. Software interface between a parallel bus and a packet network
US6484222B1 (en) * 1999-12-06 2002-11-19 Compaq Information Technologies Group, L.P. System for incorporating multiple expansion slots in a variable speed peripheral bus
US6636929B1 (en) * 2000-04-06 2003-10-21 Hewlett-Packard Development Company, L.P. USB virtual devices
US7107383B1 (en) 2000-05-03 2006-09-12 Broadcom Corporation Method and system for multi-channel transfer of data and control information
US6466541B1 (en) * 2000-05-31 2002-10-15 Fujitsu Network Communications, Inc. Cell pacing on a network link employing a rate-based flow control protocol with underlying credit-based flow control mechanisms

Also Published As

Publication number Publication date
US7334074B2 (en) 2008-02-19
EP1279103A2 (en) 2003-01-29
WO2001084330A3 (en) 2002-06-13
AU2001259440A1 (en) 2001-11-12
US20070016713A1 (en) 2007-01-18
EP1279103B1 (en) 2005-11-16
US7107383B1 (en) 2006-09-12
ATE310276T1 (en) 2005-12-15
WO2001084330A2 (en) 2001-11-08
DE60115010T2 (en) 2006-08-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: BOSCH JEHLE PATENTANWALTSGESELLSCHAFT MBH, 80639 M