WO2001082059A3 - Procede et appareil d'amelioration des temps de changement de contexte dans un systeme informatique - Google Patents

Procede et appareil d'amelioration des temps de changement de contexte dans un systeme informatique Download PDF

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Publication number
WO2001082059A3
WO2001082059A3 PCT/US2001/013530 US0113530W WO0182059A3 WO 2001082059 A3 WO2001082059 A3 WO 2001082059A3 US 0113530 W US0113530 W US 0113530W WO 0182059 A3 WO0182059 A3 WO 0182059A3
Authority
WO
WIPO (PCT)
Prior art keywords
registers
abandoned
instruction
register
processor
Prior art date
Application number
PCT/US2001/013530
Other languages
English (en)
Other versions
WO2001082059A2 (fr
Inventor
Ashley Saulsbury
Daniel S Rice
David Emberson
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to AU2001257323A priority Critical patent/AU2001257323A1/en
Publication of WO2001082059A2 publication Critical patent/WO2001082059A2/fr
Publication of WO2001082059A3 publication Critical patent/WO2001082059A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)

Abstract

L'invention concerne un procédé et un appareil d'amélioration des temps de changement de contexte dans un système informatique. L'invention a trait à un mécanisme destiné à des registres contenant des données non requises à enlever d'un contexte de processus, ce qui permet ainsi de réduire le temps nécessaire pour réaliser un changement de contexte. On utilise des instructions de programme pour spécifier explicitement des registres qui doivent être abandonnés. Dans le cadre de l'installation d'un projet de bits modifiés par un processeur, ce dernier réinitialise les bits modifiés pour ces registres qui doivent être abandonnés. Un changement de contexte subséquent exclut des registres abandonnés. Selon un mode de réalisation, une instruction NOP (ou une autre instruction avec des bits de surplus pour des opérandes supplémentaires) présente au moins une opérande de spécification des registres à abandonner. Lors de l'exécution normale de l'instruction NOP, les registres spécifiés sont enlevés du contexte du processus (par exemple, par réinitialisation des bits modifiés associés). Dans un autre mode de réalisation, l'identification des registres destinés à l'abandon est codée au sein d'instructions existantes qui peuvent spécifier des registres comme des opérandes de source. Selon l'invention, un champ binaire de « registre d'abandon » est créé dans une instruction pour chaque opérande de source qui spécifie un registre de processeur. Si le bit du « registre d'abandon » est établi pour l'opérande de source donnée, le processeur élimine du contexte du processus le registre associé.
PCT/US2001/013530 2000-04-27 2001-04-26 Procede et appareil d'amelioration des temps de changement de contexte dans un systeme informatique WO2001082059A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001257323A AU2001257323A1 (en) 2000-04-27 2001-04-26 Method and apparatus to improve context switch times in a computing system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US56137800A 2000-04-27 2000-04-27
US09/561,378 2000-04-27

Publications (2)

Publication Number Publication Date
WO2001082059A2 WO2001082059A2 (fr) 2001-11-01
WO2001082059A3 true WO2001082059A3 (fr) 2002-04-11

Family

ID=24241692

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/013530 WO2001082059A2 (fr) 2000-04-27 2001-04-26 Procede et appareil d'amelioration des temps de changement de contexte dans un systeme informatique

Country Status (2)

Country Link
AU (1) AU2001257323A1 (fr)
WO (1) WO2001082059A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7962731B2 (en) 2005-10-20 2011-06-14 Qualcomm Incorporated Backing store buffer for the register save engine of a stacked register file
US7844804B2 (en) * 2005-11-10 2010-11-30 Qualcomm Incorporated Expansion of a stacked register file using shadow registers

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4740893A (en) * 1985-08-07 1988-04-26 International Business Machines Corp. Method for reducing the time for switching between programs
US5485624A (en) * 1991-06-19 1996-01-16 Hewlett-Packard Company Co-processor monitoring address generated by host processor to obtain DMA parameters in the unused portion of instructions
EP0955583A2 (fr) * 1998-05-06 1999-11-10 Sun Microsystems, Inc. Technique de commutation de contexte pour processeurs avec grand tampon de régistres

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4740893A (en) * 1985-08-07 1988-04-26 International Business Machines Corp. Method for reducing the time for switching between programs
US5485624A (en) * 1991-06-19 1996-01-16 Hewlett-Packard Company Co-processor monitoring address generated by host processor to obtain DMA parameters in the unused portion of instructions
EP0955583A2 (fr) * 1998-05-06 1999-11-10 Sun Microsystems, Inc. Technique de commutation de contexte pour processeurs avec grand tampon de régistres

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"TECHNIQUE FOR REDUCING THE NUMBER OF REGISTERS SAVED AT A CONTEXT SWAP", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 33, no. 3A, 1 August 1990 (1990-08-01), pages 234 - 235, XP000123918, ISSN: 0018-8689 *
SCHLAEPPI H P ET AL: "LIVE/DEAD TAGS ON COMPUTER REGISTERS", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 25, no. 3A, August 1982 (1982-08-01), pages 1304 - 1307, XP000885132, ISSN: 0018-8689 *

Also Published As

Publication number Publication date
WO2001082059A2 (fr) 2001-11-01
AU2001257323A1 (en) 2001-11-07

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