WO2001080493A2

WO2001080493A2 - Method and device for layer 3 address learning

Info

Publication number: WO2001080493A2
Application number: PCT/US2001/009373
Authority: WO
Inventors: Shr-Jie Tzeng
Original assignee: Advanced Micro Devices, Inc.
Priority date: 2000-04-13
Filing date: 2001-03-23
Publication date: 2001-10-25
Also published as: WO2001080493A3; EP1273139A2; CN1456004A; KR20020091203A; JP2004515088A

Abstract

A packet identifier module is configured for determining whether a received data packet originated from a router. If the packet identifier module identifies the received data packet as being from a network node other than the router, the switch module selectively stores the layer 2 address and the associated layer 3 address of the data packet as an associated layer 2-layer 3 address pair in an address table. The selective storing of the associated layer 2-layer 3 address is also referred to as learning the internet protocol (IP)-media access control association (MAC) of the data packet. By selectively learning the IP-MAC associations of selected data packets from the non-router ports, the likelihood of overflowing the address table is reduced. Furthermore, by using the learned IP-MAC associations, the network switch may switch layer 3 data packets bypassing the router and reducing latency.

Description

PROGRAMMABLE LAYER 3 ADDRESS SELF- LEARNING SCHEME IN A NETWORK SWITCH

HELD OF THE INVENTION

The present invention relates to learning network addresses of data packets in a non- blocking network switch configured for switching data packets among subnetworks and a router.

BACKGROUND ART

Local area networks use a network cable or other media to link stations on the network. Each local area network architecture uses a media access control (MAC) enabling network interface devices at each network node to access the network medium.

The Ethernet protocol IEEE 802.3 has evolved to specify a half-duplex media access mechanism and a full-duplex media access mechanism for transmission of data packets. The full- duplex media access mechanism provides a two-way, point-to-point communication link between two network elements, for example between a network node and a switched hub. Switched local area networks are encountering increasing demands for higher speed connectivity, more flexible switching performance, and the ability to accommodate more complex network architectures. For example, commonly-assigned U.S. Patent No. 5,953,335 discloses a network switch configured for switching layer 2 type Ethernet (IEEE 802.3) data packets between different network nodes; a received data packet may include a VLAN (virtual LAN) tagged frame according to IEEE 802. Iq protocol that specifies another subnetwork (via a router) or a prescribed group of stations. Since the switching occurs at the layer 2 level, a router is typically necessary to transfer the data packet between subnetworks.

Efforts to enhance the switching performance of a network switch to include layer 3 (e.g., Internet protocol) processing typically require CPU-based control of network address tables for learning of layer 3 addresses. For example, a router may perform layer 2-layer 3 associations based on a prescribed address resolution protocol. Typically, the router is the bottleneck for a LAN, as current layer 2 switches preferably are configured for operating in a non-blocking mode, where data packets can be output from the network switch at the same rate that the data packets are received. Hence, use of a switch having layer 2-layer 3 switching capability can off-load the router and reduce the latency. In addition, the conventional learning technique in layer 2 switches of learning the media access control ("MAC") address of every received data packet is not practical in layer 3 switching since layer 3 learning may quickly overwhelm the address tables within network switch.

SUMMARY OF THE INVENTION

There is a need for an arrangement that enables a network switch to provide automatic learning of network addresses for layer 2 and layer 3 switching for 100 Mbps and gigabit links without blocking of the data packets.

There is also a need for an arrangement to enable a non-blocking network switch to selectively learn the layer 2 address and the associated layer 3 address of incoming data packets at the wire rate, without overwhelming the network switch address tables. These and other needs are attained by the present invention, where a network switch for switching a data packet includes a plurality of ports for receiving and transmitting a plurality of data packets. An incoming data packet is evaluated by a packet identifier module to determine whether the received data packet is received from a router connected to the network switch. If the received data packet is from a network node other than the router, a switch module selectively stores a layer 2 source address and an associated layer 3 source address of the received data packet as an associated layer 2-layer 3 address pair in an address table. Accordingly, the likelihood of an overflow condition in the address table is reduced since the address tables contain fewer entries.

One aspect of the present invention provides a method of switching a data packet at a network switch port. The method includes receiving the data packet by one port of the network switch, and determining whether the one port received the data packet from a router. The method also includes selectively storing in an address table a layer 2 source address and the associated layer 3 source address from the data packet as an associated layer 2-layer 3 address pair based on the determination that the one port received the data packet from a network node other than the router. Accordingly, the address tables contain fewer entries, and thus reducing the likelihood of an overflow in the address tables.

Another aspect of the present invention provides a network switch for switching a data packet received at a network switch port. The network switch includes a plurality of ports for receiving and transmitting a plurality of data packets where one port of the plurality of ports is coupled to a router, a packet identifier module, and a switch module. The packet identifier module configured for determining whether a received data packet is from the router. The switch module is configured for selectively storing a layer 2 source address and an associated layer 3 source address from the received data packet as an associated layer 2-layer 3 address pair in an address table based on received data packet being received from a network node other than the router. As a result, the likelihood of an overflow in the address tables is reduced.

Additional advantages and novel features of the invention will be set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the present invention may be realized and attained by means of instrumentalities and combinations particularly pointed in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference is made to the attached drawings, wherein elements having the same reference numeral designations represent like element elements throughout and wherein:

Figure 1 is a block diagram of a packet switched network including multiple network switches for switching data packets between respective subnetworks according to an embodiment of the present invention.

Figure 2 is a block diagram illustrating a network switch of Fig. 1 according to an embodiment of the present invention.

Figure 3 is a flow diagram illustrating learning in the network switch of Fig. 1 according to an embodiment of the present invention.

Figure 4 is an alternative flow diagram illustrating learning in the network switch of Fig. 1 according to an embodiment of the present invention. Figure 5 is another alternative flow diagram illustrating learning in the network switch of

Fig. 1 according to an embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Figure 1 is a block diagram illustrating a packet switched network 10, such as an Ethernet (IEEE 802.3) network. The packet switched network includes integrated (i.e., single chip) multiport switches 12 that enable communication of data packets between network stations 14. Each network station 14, for example a client workstation, is typically configured for sending and receiving data packets at 10 Mbps or 100 Mbps according to IEEE 802.3 protocol. Each of the integrated multiport switches 12 are interconnected by gigabit Ethernet links 16, enabling transfer of data packets between subnetworks (or subents) 18a, 18b, and 18c. Hence, each subnetwork includes a switch 12, and an associated group of network stations 14.

Each switch 12 includes a switch port 20 that includes a media access control (MAC) module 22 and a port filter 24, also referred to as a packet identifier module. The MAC module 20 transmits and receives data packets to the associated network stations 14 across 10/100 Mbps physical layer (PHY) transceivers (not shown) according to IEEE 802.3u protocol. Each switch 12 also includes a switch module 25 configured for making frame forwarding decisions for received data packets. In particular, the switch module 25 is configured for layer 2 switching decisions based on source MAC address, destination MAC address, and VLAN information within the Ethernet (IEEE 802.3) header; the switch module 25 is also configured for selective layer 3 switching decisions based on evaluation of an IP data portion within the Ethernet packet.

As shown in Figure 1, each switch 12 has an associated host CPU 26 and a buffer memory 28, for example an SSRAM. The host CPU 26 controls the overall operations of the corresponding switch 12, including programming of the switch module 25. The buffer memory 28 is used by the corresponding switch 12 to store data frames while the switch module 25 is processing forwarding decisions for the received data packets.

Each switch 12 also contains a memory 30 which is configured for the limited storage of internet protocol (IP)-media access control (MAC) associations of data packets as an address table. As described above, the switch module 25 is configured for performing layer 2 switching decisions and selective layer 3 switching decisions. The availability of layer 3 switching decisions may be particularly effective if an end station 14 within subnetwork 18a wishes to send an e-mail message to selected network stations in subnetwork 18b, 18c. Since subnetworks 18b, 18c are on different subnets, the host in subnetwork 18a cannot know the layer 2 address for the host on subnetworkslδb and/or 18c. The switch module 25 of switch 12a would need to send the e-mail message to the router 19, which would introduce additional delay. Use of layer 3 switching decisions by the switch module 25 enables the switch module 25 to make intelligent decisions as far as how to handle a packet, including advanced forwarding decisions, and whether a packet should be considered a high-priority packet for latency-sensitive applications, such as video or voice. As routers are typically the bottleneck for a LAN, the switch module 25 can off-load the router and also improve the round trip delay. .

According to the disclosed embodiment, a network switch 12 is configured to learn the IP- MAC association of selected data packets. Each packet identifier module 24 of the network switch is configured for determining whether a received data packet is received from the router 19. If the packet identifier module 24 identifies the received data packet as being from a network node other than the router 19, a switch module 25 of the network switch 12 selectively stores the layer 2 source address and the associated layer 3 source address of the data packet as an associated layer 2-layer 3 address pair in an address table. The selective storing of the associated layer 2-layer 3 address is also referred to as learning an IP-MAC association of the data packet. By selectively learning the IP- MAC associations of selected data packets from the non-router ports, the likelihood of overflowing the address table is reduced. Furthermore, by using the learned IP-MAC associations, the network switch may perform layer 3 switching, enabling bypassing of the router between connected subnetworks, reducing latency. Fig.2 illustrates a more detailed block diagram of the port filter 24 shown in Fig. 1. The port filter 24 includes a receive first-in-first out buffer (FIFO) 51, a MAC queuing logic 52, a memory 53, a MAC dequeuing logic 54, a transmit FIFO 55, and a processor interface module 57.

The receive FIFO 51 is a buffer that is configured for temporary storage of an incoming data packet in response to receiving the incoming data packet from the receive portion of the port 20. The MAC queuing logic 52 provides for a variety of functions for the port filter 24. The

MAC queuing logic 52 provides for writing a received data packet to the SSRAM 28 over a data bus 59 to an external memory interface 26 from the receive FIFO 51. The MAC queuing logic 52 also provides for a plurality of status signals 58 to the switch module 25 in response to the MAC queuing logic processing the received data packet. The status signals 58 provide an indication to the switch module 25 that the received data packet was transferred to the external memory interface 26 without error, or the transfer of the received data packet is complete. The status signals 58 also include a subnetwork routing signal (RNETS_ENABLE) and a learn signal (L3IRC_LEARN).

When the MAC queuing logic 52 sets the RNETS_ENABLE signal, the switch module 25 is notified that the received data packet is part of the inter-subnetwork traffic between subnetworks directly connected to the network switch 12a.

When the MAC queuing logic 52 sets the L3IRC_LEARN, the switch module 25 is to learn an IP-MAC address association for the received data packet.

The memory 53 provides register space 53a for parameters for the MAC queuing logic 52 to implement the learn and subnetwork routing functions. The register space 53a provides at least a SUBNETJD and SUBNETjMASK registers for the MAC queuing logic. The CPU 26 programs the registers via the processor interface (pi_mod) 57. The SUBNET_ID register provides for storage of the IP address that the individual port belongs. Each port on the switch 12a has one SUBNETJD register. The SUBNET_MASK provides for storage of the 32-bit IP address mask of the individual port. Each port on the switch 12a has one SUBNET_MASK mask register. The MAC dequeuing logic 54 provides for retrieving the received data packet from SSRAM

28 and forwarding the data packet to the appropriate port in response to the processing by the switch module 25.

The transmit FIFO 55 provides for a buffer for an outgoing data packet prior to transmission by the port 20. An incoming data packet is received at the port 20 and is buffered in the receive FIFO 51. The MAC queuing logic 52 forwards the data packet to the external memory interface 56 for storage in the SSRAM 28 over the data bus 59.

The MAC queuing logic 52 searches for layer 3 information, e.g., IP data packet, in the received data packet by examining the header and frame data of the data packet. Using the layer 3 information, the MAC queuing logic 52 may determine whether the received data packet is part of the inter-subnetwork traffic by comparing the destination IP addresses in the IP header with the values stored in the registers of the memory 53.

Specifically, if the received data packet is received from a non-router port, the IP destination address is masked against SUBNETJVIASK of all the other ports. The result of the mask operation is then compared against the SUBNET_ID registers of all other ports. If the result of the compare operation is successful, the MAC queuing logic 52 sets the RNETS_ENABLE signal to the switch module 25.

The MAC queuing logic 52 may also be configured to determine whether or not the switch module 25 needs to learn the source IP-MAC address association of the received data packet for

IP addresses in the subnetworks that are directly connected to the network switch 12a if the packet arrived from a non-router port. The host CPU 26 is responsible for programming the registers in memory 53 so that the switch module 25 knows which port is connected to the router.

The MAC queuing logic 52 may also be configured to learn an IP-MAC association if the MAC queuing logic 52 of the port identifier module 24 determines the received data packet is intended for the router and maybe part of the intersubnetwork traffic.

Furthermore, the MAC queuing logic 52 of the packet identifier module 24 may be configured to learn the IP-MAC association of a received packet if the received data packet is intended for the router and is part of the inter-subnetwork traffic. Specifically, the MAC queuing logic 52 compares the MAC destination address of the received data packet with the MAC address of the router stored in the memory 53. If the result of the compare operation is successful, the received data packet is intended for the router. Subsequently, the MAC queuing logic 52 of the port identifier module 24 notifies the switch module 25 to selectively store the layer 2 source address and the associated layer 3 address address as an associated layer 2-layer 3 address pair in the address table 30.

The MAC queuing logic 52 of the packet identifier module 42 may be configured to implement any of these functions depending on the traffic flow in the network switch 12 or user preferences. The MAC queuing logic 52 may also be configured to implement a variety of other functions as deemed necessary by the user. Fig. 3 illustrates a flow chart for learning implemented by the packet identifier module 24 illustrated in Fig. 2. In step 310, a data packet is received at the port identifier module 24 from a one of the ports 20.

The port identifier module 24 is configured to determine whether the received data packet is being received from a non-router port in step 320. The Host CPU is responsible for programming which port is connected to a router.

If the received data packet is being received on a non-router port in step 320, then the MAC queuing logic 52 of the port identifier module 24 asserts the Learn signal to notify the switch module 25 to store the layer 2 address, or MAC address, and the associated layer 3 address, or IP address, as an associated layer 2-layer 3 address in address table in memory 30 in step 330.

If the received data packet is being received from a router port in step 320, then the MAC queuing logic 52 of the port identifier module 24 deasserts the Learn signal to the switch module 25 in step 340. The IP-MAC association of the received data packet is not learned.

Fig. 4 illustrates an alternative flow chart for learning implemented by the packet identifier module 24 illustrated in Fig. 2. In this rule, an IP-MAC association is learned when the received data packet is from a non-router port and has a destination MAC address of the router. In step 410, a data packet is received at the port identifier module 24 from a one of the ports 20.

The port identifier module 24 is configured to determine whether the received data packet is being received from a non-router port, and the MAC destination address of the data packet is the router, in step 410. The host CPU 26 is responsible for programming which port is connected to a router, and the MAC queuing logic 52 compares the destination MAC address of the received data packet with the MAC address of the router.

If the comparisons are successful from step 420, then received data packet is being received on a non-router port and the destination MAC address is the router in step 430. The MAC queuing logic 52 of the port identifier module 24 notifies the switch module 25 to store the layer 2 source address, or MAC source address, and the associated layer 3 source address, or IP source address, as an associated layer 2-layer 3 address in address table in memory 30 in step 430.

If either or both of the comparisons fail from step 420, then the port identifier module 24 fails to notifies the switch module 25 in step 440. The IP-MAC association of the received data packet is not learned.

Fig. 5 illustrates another alternative flow chart for learning implemented by the packet identifier module 24 illustrated in Fig. 4. In this rule, an IP-MAC association is learned when the received data packet is part of the inter-subnetwork traffic and the destination MAC address is the router. In step 510, a data packet is received at the port identifier module 24 from a one of the ports 20.

The port identifier module 24 is configured to determine whether the received data packet is being received from a non-router port in step 510. The MAC queuing logic 52 masks the destination IP address with all the other SUBNET_MASK in the switch module 25. The masked results are then compared with all the other SUBNET D addresses in the switch 12a.

Furthermore, the MAC queuing logic 52 also compares the destination MAC address of the received data packet with the MAC address of the router.

If all the comparisons are successful from step 520, the MAC queuing logic 52 of the port identifier module 24 notifies the switch module 25 to store the layer 2 source address, or MAC source address, and the associated layer 3 source address, or IP source address, as an associated layer 2-layer 3 address in address table in memory 30, in step 530.

If any of the comparisons fails from step 520, the MAC queuing logic 52 of the port identifier module 24 fails to notifies the switch module 25 in step 540. The IP-MAC association of the received data packet is not learned.

According to the disclosed embodiment, a packet identifier module is configured for determining whether a received data packet originated from a router. If the packet identifier module identifies the received data packet as being from a network node other than the router, the switch module selectively stores the layer 2 address and the associated layer 3 address of the data packet as an associated layer 2-layer 3 address pair in an address table. By storing IP-MAC associations of selected data packets, the network switch may reduce the search time in the address table when the switch references the address table during switching. As a result, the packet identifier module allows the network switch to provide layer 3 and layer 2 switching capabilities for 100 Mbps or gigabit links without blocking of the data packets. While this invention has been described with what is presently considered to be the most practical preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

What is Claimed Is

1. A method in a network switch, the method comprising: receiving a data packet by one port of the network switch; determining whether the one port received the data packet from a router; and selectively storing in an address table a layer 2 address and an associated layer 3 address from the data packet as an associated layer 2-layer 3 address pair based on the determination that the one port received the data packet from a network node other than the router.

2. The method of claim 1, wherein: the selectively storing step includes storing the layer 2 address and the associated layer 3 address as the associated layer 2-layer 3 address pair based on the determination that the one port received the data packet from a network node other than the router, and in response to determining that a destination layer 2 address within the data packet specifies the router.

3. The method of claim 2, wherein: the layer 2 address and the associated layer 3 address are source addresses.

4. The method of claim 1, wherein: the network switch includes a second port and a third port coupled to a first subnetwork and a second subnetwork, respectively.

5. The method of claim 4, further comprising: determining whether the data packet includes address information specifying transfer of the data packet between the second port and the third port.

6. The method of claim 5, wherein: the selectively storing step includes storing the layer 2 address and the associated layer 3 address as the associated layer 2-layer 3 address pair based on the determination that the one port received the data packet from a network node other than the router, and in response that the data packet includes the address information specifying transfer of the data packet between the second port and the third port.

7. The method of claim 2, further comprising: determining by a port identifier module in the network switch that the data packet includes address information specifying a transfer of the data packet between a second port and a third port, wherein the second port and the third port are coupled to a first and second subnetwork, respectively.

8. A network switch, comprising: a plurality of ports for receiving and transmitting a plurality of data packets, wherein one port of said plurality of ports is coupled to a router; a packet identifier module is configured for determining whether a received data packet is from router; and a switch module is configured for selectively storing a layer 2 address and an associated layer 3 address from the received data packet as an associated layer 2-layer 3 address pair in an address table based on received data packet being received from a network node other than the router.

9. The network switch according to claim 8, wherein: the packet identifier module is configured for determining whether the received data packet includes address information that specifies a destination address of the router; and the switch module is configured for selectively storing the layer 2 address and the associated layer 3 address from the received data packet as the associated layer 2-layer 3 address pair based on received data packet being received from a network node, and in response to the address information including the destination address of the router.

10. The network switch according to claim 8, wherein: the layer 2 address and the associated layer 3 address are source addresses.

11. The network switch according to claim 8, wherein: a second port of the plurality of ports is coupled to a first subnetwork; a third port of the plurality of ports is coupled to a second subnetwork; and said packet identifier module is configured for determining whether the received data packet includes address information specifying a transfer of the received data packet between the first subnetwork and second subnetwork.

12. The network switch according to claim 11, wherein: the switch module selectively stores the layer 2 address and the associated layer 3 address of the received data packet as the associated layer 2-layer 3 address pair based on the received data packet being received from a network node, and in response to the address information specifying a transfer of the received data packet between the first subnetwork and second subnetwork.

13. The network switch according to claim 8, further comprising a second port of the plurality of ports is coupled to a first subnetwork; a third port of the plurality of ports is coupled to a second subnetwork; and said packet identifier module is configured for determining whether the received data packet includes address information specifying a transfer of the received data packet between the first subnetwork and second subnetwork.

14. The network switch according to claim 8, wherein: each port of the plurality of ports is configured to include the packet identifier module.