CN1304994C - Exchanger and router chip drawn by running chip general stardards and core logic and method - Google Patents
Exchanger and router chip drawn by running chip general stardards and core logic and method Download PDFInfo
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- CN1304994C CN1304994C CNB031356788A CN03135678A CN1304994C CN 1304994 C CN1304994 C CN 1304994C CN B031356788 A CNB031356788 A CN B031356788A CN 03135678 A CN03135678 A CN 03135678A CN 1304994 C CN1304994 C CN 1304994C
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Abstract
The present invention relates to a design process of a very large scale integrated circuit (VLSI), which belongs to the design of an application specific integrated circuit (ASIC) in the communicating technology. The present invention is used for designing a two-layer/three-layer network exchanger and a router chip. The method is characterized in that network exchange protocol, data information in a register and a table, information in a data packet, etc. write the general specification of the chip in a computer and a core logic program which also is a verified program to define the integrated circuit and the chip. New functions, the state of a set controllable switch, etc. can also be added according to the specific requirements of users or network development to compile a running exchange or route logic program to define the integrated circuit. The traditional literal narrative chip design of engineers is replaced by the running computer programs, and therefore, the readability is strong, and the logicality is clear. Verification and modification can be done at any time in the computer, and the period of compilation, self testing and logic testing is shortened. Improvement can be done at any time according to the requirements of the users, the information is effectively fed back to the users, and the extra processing efficiency is improved. Because various condition requirements can be met by the controllable switch, the design efficiency of the chip is greatly improved and the efficiency of the chip is improved and expanded.
Description
(1) technical field: the present invention relates to the design cycle of VLSI (very large scale integrated circuit), proposed to formulate the method for chip, be fit to the formulation of 2 layers/3 layer network switches and router chip by the chip overall specifications that can move and core logic.Belong to the design of application-specific integrated circuit ASIC in the mechanics of communication.
(2) background technology: definite step of conventional switch and router chip is as follows: 1. the design engineer formulates the design proposal and the specification of chip according to network exchange agreement and packet information needed data etc. with the character narrate mode.2. the design engineer converts character narrate to working procedure; 3. the checking slip-stick artist determines proving program according to design proposal; 4. at last working procedure and proving program are moved in computing machine and verified, determine integrated circuit and chip.At first, because exchange logic is to be formed by a lot of network exchange combination of protocols, carry out exchange logic design with literal, the slip-stick artist needs the long duration to remove to understand character narrate and change, prolong the chip design time, and can not in time reflect the deficiency in the design.They are two years old, in the design of exchange logic, a nearly hundreds of register and about more than 20 forms, wherein any configuration different with according to the packet that enters switch and router inequality, can produce multiple different exchange logic, this is an extremely complicated combinational logic; By the difference on the what character narrate sharpness, cause logical design and logic checking inaccurate, Different Results appears, reduced the efficient of formulating chip, restricted the performance of chip.
(3) summary of the invention: the present invention is intended to improve the deficiency of formulating in the network switch and the above-mentioned design cycle of router chip, shortens chip and determines the cycle, improves performance.Its technical scheme is as follows: 2 layers/3 layer switch and the router chips that can move, comprise chip overall specifications, integrated circuit, port, register, form, it is characterized in that determining and the improvement design of this chip all being carried out on computers of the overall specifications of chip and integrated circuit, write respectively and the overall specifications of definite chip, write and determine integrated circuit behind the core logic and design is realized improving in their backs of making amendment with the computerese that can move.
The determining of this chip also comprises the proving program that can move, just the above-mentioned chip overall specifications of moving and core logic program as proving program, determined or improved integrated circuit by them.Said chip can also comprise by user's specific (special) requirements or/and the requirement of network development what's new with the overall specifications and the core logic program of computing machine language compilation chip, also is a proving program in computing machine, is determined or improved integrated circuit by it.Said chip can also be included in the exchange or the logical routing program in each function place establish a gate-controlled switch, and be deposited with in register or the form, state according to gate-controlled switch exchanges or the logical routing program with the computing machine language compilation is different, also be proving program, determined or improved integrated circuit by it.
2 layers/3 layer switchs that can move and the formulating method of router chip, the step of carrying out comprises on computers: the A that designs program that (C) obtains after the empirical tests, determine the step of integrated circuit Ua; It is characterized in that this method carries out on computers, also comprise the steps:
(a) will exchange or route in desired data and information input and depositing in various registers of what and the form; Writing the overall specifications and the core logic program A1 of chip in computing machine with the computerese that can move, also is proving program A1;
This method is carried out on computers, also comprises the following steps:
Above-mentioned steps (a) and (b) He (C) also comprise the following steps (1) respectively and (2)-(7) and (8):
1. will exchange or route in desired data and information input and depositing in various registers of what and the form: these data and information can be made amendment with the change of network exchange agreement or user's request; These data of input and information can produce with this three part: 1a. slip-stick artist requires the configuration corresponding data according to checking, and 1b. is by slip-stick artist's setting range, and computing machine produces data at random in this scope; 1c. produce data by computer random fully; The data that this 3 part produces by the corresponding computer programs input, with information and the data that these 3 kinds of modes produce, can truly simulate the input of data in network exchange or the route.
With the definite definite step of what (as: it is standard with IEEE802.3 that Ethernet is selected the network exchange agreement) with which kind of network exchange agreement;
Writing chip overall specifications and core logic program A1 with the computerese that can move in computing machine, also is proving program A1;
2. import the step of packet with what;
3. according to the network exchange agreement packet is carried out classification of type (as: being divided into main broadcaster's bag, unicast packet, multicast bag), and detection data packet length, compare with data in register and the form according to classification and packet internal information, determine the relatively selection step of effective data packets;
4. divide two steps: 4.1, according to the classification of packet, determine whether to do exchange or route; 4.2. according to destination address and packet internal information, the specified data bag is a selection step of determining to do 3 layers of route or 2 layers of exchange behind 2 layers of bag or the 3 layers of bag again;
5. divide two step: 5.1. check in the packet data whether with form in data be complementary, determine whether normal exchange or route; If search failure, determine whether the relatively selection step of normal exchange or route again by the network exchange agreement; 5.2. the data in the inspection packet whether with form in data be complementary, determine whether to do 3 layers of route, if search failure, determine whether to do 3 layers of route by the network exchange agreement again; If do not make 3 layers of route, determine whether to do 2 layers of relatively selection step that exchanges or do not do to exchange by the network exchange agreement again;
6. normally exchange or route or packet loss;
7 produce the A2 that designs program by above-mentioned steps, are verified the design program step of A of final acquisition by proving program A1 again;
8. with the A that designs program of checking back acquisition, determine the step of the integrated circuit U a of chip.
On above-mentioned core logic procedure basis, increase function program, in above-mentioned steps, increase user's specific demand or/and network development what's new demand, and select the step determined.
When the above-mentioned various step of running, checking, logic detection are also carried out simultaneously, for satisfying the demand, every function all is provided with a gate-controlled switch, the user can open or close on demand, the method is at each function place of logical program gate-controlled switch to be set, and selects the step of determining according to the gate-controlled switch state.
The step that more than relates to selection can all can be controlled by gate-controlled switch, the user is different with the form configuration to register, make different choice, such as: the user opens the switch that a packet send central processor CPU, can be at different ports or different packets and whether the determination data bag send CPU, if close this switch, all packets can not sent to CPU.
Beneficial effect of the present invention is as follows: (1) substitutes traditional character narrate with the chip overall specifications that can move and core logic program, strengthened the readability of scheme, logic is more clear, and the design engineer can convert to rapidly and design program, and has shortened the chip design cycle greatly.(2). this can move the core logic program also is a proving program simultaneously, the mistake during not only in time checking is designed program, and can utilize the difference of verifying the result, the deficiency in the counterevidence scheme is also improved rapidly; Shortened that compiling, oneself detect, the cycle of logic detection, improved efficient, improved the performance of chip greatly.(3) can be by user's specific demand, improvement project, and realization checking (analogue simulation) is on computers immediately at any time given the user with information feedback efficiently, improves reprocessing efficient and enlarges the chip usability.(4). can need what's new by network development, enlarge the chip usability.(5). every function all is provided with a gate-controlled switch, satisfies various situation demands.
(4) description of drawings:
Fig. 1 embodiment of the invention: the FB(flow block) of determining router and exchanger chip
Fig. 2 embodiment of the invention: the computer program figure of router and exchanger chip formulating method
(5) embodiment:
See Fig. 1, according to data and information in network exchange agreement, register and the form, overall specifications and core with computing machine language compilation chip in computing machine exchange or logical routing journey A1 (also being proving program A1), the packet input is produced the A2 that designs program, and verify and logic detection with proving program A1, and obtain to design program A, make the integrated circuit U a of chip by it, and produce chip Za by integrated circuit Ua.
See Fig. 1, chip of the present invention can also be on the basis of above-mentioned core exchange or logical routing program A, according to user's specific demand and the new function of network development, write overall specifications and the exchange or the logical routing program B1 (also being proving program B1) of chip with the computerese that can move, increasing new procedures is also verified and logic detection, the acquisition B that designs program makes the integrated circuit U b of chip by it, and produces chip Zb by integrated circuit Ub.Can feed back to the user after this increase new procedures and the checking, after improving and reprocessing, the specific demand that can be used as new user joins among chip overall specifications and exchange or the logical routing program B1.
See Fig. 1, chip of the present invention can also be on the basis of said chip overall specifications and exchange or logical routing program B1, establish a gauge tap at each function place, and be deposited with in form and the register, write overall specifications and the exchange or the logical routing program C1 (also being proving program C1) of chip with the computerese that can move, through logic detection and checking to unlatching or closing control switch, the acquisition C that designs program, make the integrated circuit U c of chip by it, and produce chip Zc by integrated circuit Uc.
See Fig. 1, carry out obtaining after the logic detection carrying out logic detection again after the chip overall specifications that can move and core exchange or logical routing program carry out design verification.The C that designs program simultaneously also carries out logic detection.
See Fig. 2, the formulating method of router and exchanger chip in the embodiment of the invention: comprise the chip overall specifications and the core logic (proving program) that can move, also comprise and consider user's specific demand, the network development what's new is provided with 2 layers/3 layer switchs of comprehensive characteristics generations such as gauge tap and the formulating method of router chip.This formulating method carries out on computers, comprises following concrete steps:
1. will exchange or route in desired data, information and the input of gate-controlled switch state and deposit in various registers of what and the form: these data and information and gate-controlled switch state can be made amendment with the change of network exchange agreement or user's request; Available following three parts of the generation of these data, information and the gate-controlled switch state of input produce: 1a. slip-stick artist requires the configuration corresponding data according to checking, and 1b. is by slip-stick artist's setting range, and computing machine produces data at random in this scope; 1c. produce data by computer random fully; The data that this 3 part produces by the corresponding computer programs input, with information and the data that these 3 kinds of modes produce, can truly simulate the input of data in network exchange or the route.
With the definite definite step of what with which kind of network exchange agreement, as: it is standard with IEEE802.3 that Ethernet is selected the network exchange agreement.
Import the step of the requirement of user's specific (special) requirements and network development what's new with what;
In computing machine, write chip overall specifications and core exchange or logical routing program C1, be proving program C1 with the computerese that can move, (according to the network exchange agreement, user's specific demand, the network development what's new, gauge tap state etc. carries out);
2. import the step of packet with what.
3. the type of dividing data bag and definite effective data packets: this is divided into following four steps: (3.1) carry out classification of type according to the network exchange agreement to packet.For example: be divided into main broadcaster's bag, unicast packet, multicast bag.(3.2) detect the whether requirement of protocol compliant of data packet length.For example: Ethernet requires the bag length can not little what 64 bytes or big what 1536 bytes, and the data in effective byte are effective data packets.(3.3), determine whether to be effective data packets according to packet classification.For example: to Bridge Protocol Data Unit (BPDU), by the difference of its destination address as whether being the foundation of effective data packets.(3.4) according to the information in the packet, the data of depositing in the lookup table, satisfactory is effective data packets.For example: packet has the VLAN frame identifier, tables look-up and finds that this identifier is the invalidated identification symbol, and then packet is an invalid packets.
4. this program is divided into following two steps: (4.1) determine according to the classification of packet whether it does exchange or route.For example: broadcast packet (broadcast), must be to do 2 layers of exchange, but the user has opened a gate-controlled switch and has controlled the broadcast packet quantity of passing through this port in the unit interval, if broadcast packet quantity surpasses a threshold value in the unit interval, this broadcast packet will not done normal exchange.(4.2) according to destination address and packet internal information, the specified data bag is 2 layers of bag or 3 layers of bag, and then the state of inspection gate-controlled switch determines to do 2 layers of exchange or 3 layers of route.For example: packet is 3 layers of multicast bag, but the user has closed the switch of 3 layers of multicast packet switch, and this packet only can exchange as 2 layers of multicast bag.
5. comprise following two steps in this program: (5.1) check in the packet data whether with form in data be complementary, if in form, do not find the data that are complementary, then determine whether normal exchange or route according to network exchange agreement or customer requirements.For example: go to search the data that are complementary in the form with the MAC Address of packet,, then do not do exchange or route or do exchange or route according to demand if search failure.(5.2) check in the packet data whether with form in data be complementary, if in form, do not find the data that are complementary, then determine whether to do 3 layers of route according to network exchange agreement or customer requirements, if do not do 3 layers of route, determine whether that according to network exchange agreement or customer requirements needs do 2 layers of exchange or do not do exchange.For example: the data that are complementary in the IP address search form with 3 layers of multicast bag, if search failure, then it is used as 2 layers of multicast bag and handles.
6. normally exchange or route or packet loss, up to end.In Fig. 2, promptly to [not doing exchange or route], packet abandons automatically to not (being invalid packets) in the program 3 and [denying] in the program 4,5.
7. produce the C2 that designs program by above-mentioned steps, and verified (comprising logic detection), obtain to design program C (seeing Fig. 1,2) with proving program C1.
8. determine corresponding integrated circuit Uc (seeing Fig. 1, Fig. 2) with the C that designs program that obtains.Produce the network switch and router chip Zc (see figure 1) by above-mentioned determined integrated circuit Uc.
2 layers/3 layers exchange or the selection of route are to need determined by network development in this embodiment.
Claims (8)
1. 2 layers/3 layer switch and the router chips that can move, comprise chip overall specifications, integrated circuit, port, register, form, it is characterized in that determining and the improvement design of this chip all being carried out on computers of the overall specifications of chip and integrated circuit, write respectively and the overall specifications of definite chip, write and determine integrated circuit behind the core logic and design is realized improving in their backs of making amendment with the computerese that can move.
2. by the described chip of claim 1, it is characterized in that the definite of this integrated circuit or improve also comprising the proving program that can move, just the above-mentioned chip overall specifications of moving and core logic program as proving program, determined or improved integrated circuit by its checking.
3. by the described chip of claim 2, it is characterized in that this chip also comprises by user's specific (special) requirements or/and the requirement of network development what's new, in computing machine, use the overall specifications and the core logic program of the chip of computing machine language compilation, also be proving program, determined or improved integrated circuit by it.
4. by claim 2 or 3 described chips, it is characterized in that respectively being provided with a gate-controlled switch, and be deposited with in register or the form at each function place of exchange or logical routing program; According to the state difference of gate-controlled switch, in computing machine,, also be proving program with the exchange or the logical routing program of computing machine language compilation, determined or improved integrated circuit by it.
5. 2 layers/3 layer switchs that can move and the formulating method of router chip, the step of carrying out comprises on computers: the step of (c) being determined integrated circuit Ua by the A that designs program of final acquisition; It is characterized in that this method carries out on computers, also comprise the steps:
(a) will exchange or route in desired data and information input and depositing in various registers of what and the form; Writing the overall specifications and the core logic program A1 of chip in computing machine with the computerese that can move, also is proving program A1;
(b) the input packet and compare selection after, verified the design program step of A of final acquisition again with proving program A1.
6. by the described chip formulating method of claim 5, it is characterized in that this method carries out on computers, also comprise the following steps: above-mentioned steps (a) and (b) also comprise the following steps (1) and (2)～(7) respectively:
(1) will exchange or route in desired data and information input and depositing in various registers of what and the form; Determine definite step with which kind of network exchange agreement; Writing the overall specifications and the core logic program A1 of chip in computing machine with the computerese that can move, also is proving program A1;
(2) with the step of what input packet;
(3) according to the network exchange agreement packet is carried out classification of type, and detect data packet length, compare with data in register and the form, determine the relatively selection step of effective data packets according to classification and the packet internal information;
(4) divide two step: 4.1. classification, determine whether to do exchange or route according to packet; 4.2. according to destination address and packet internal information, the specified data bag is a selection step of determining to do 3 layers of route or 2 layers of exchange behind 2 layers of bag or the 3 layers of bag again;
(5) divide two step: 5.1. check in the packet data whether with form in data be complementary, determine whether normal exchange or route; If search failure, determine whether the relatively selection step of normal exchange or route again by the network exchange agreement; 5.2. the data in the inspection packet whether with form in data be complementary, determine whether to do 3 layers of route, if search failure, determine whether to do 3 layers of route by the network exchange agreement again; If do not make 3 layers of route, determine whether to do 2 layers of relatively selection step that exchanges or do not do to exchange by the network exchange agreement again;
(6) normally exchange or route or packet loss;
(7) produce the A2 that designs program by above-mentioned steps, after being verified by proving program A1 again, the step of the final A that obtains to design program.
7. by the formulating method of the described chip of claim 6, it is characterized in that this method has increased user's specific (special) requirements in above-mentioned steps or/and the requirement of network development what's new, and select the step determined as requested.
8. by the formulating method of claim 6 or 7 described chips, it is characterized in that this method in above-mentioned steps, increased at each function place gate-controlled switch is set, and close according to opening or closing of switch and to select the step determined.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031356788A CN1304994C (en) | 2003-08-27 | 2003-08-27 | Exchanger and router chip drawn by running chip general stardards and core logic and method |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031356788A CN1304994C (en) | 2003-08-27 | 2003-08-27 | Exchanger and router chip drawn by running chip general stardards and core logic and method |
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| CN1591822A CN1591822A (en) | 2005-03-09 |
| CN1304994C true CN1304994C (en) | 2007-03-14 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102012957A (en) * | 2010-12-17 | 2011-04-13 | 天津曙光计算机产业有限公司 | Verification method for packet classification logic codes based on five-tuple array |
| CN105487950B (en) * | 2015-11-30 | 2019-04-09 | 致象尔微电子科技（上海）有限公司 | Chip front-end simulation detection method and device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1241275A (en) * | 1996-10-30 | 2000-01-12 | 爱特梅尔股份有限公司 | Method and system for configuring array of logic devices |
| WO2001080493A2 (en) * | 2000-04-13 | 2001-10-25 | Advanced Micro Devices, Inc. | Method and device for layer 3 address learning |
| US6571373B1 (en) * | 2000-01-31 | 2003-05-27 | International Business Machines Corporation | Simulator-independent system-on-chip verification methodology |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1241275A (en) * | 1996-10-30 | 2000-01-12 | 爱特梅尔股份有限公司 | Method and system for configuring array of logic devices |
| US6571373B1 (en) * | 2000-01-31 | 2003-05-27 | International Business Machines Corporation | Simulator-independent system-on-chip verification methodology |
| WO2001080493A2 (en) * | 2000-04-13 | 2001-10-25 | Advanced Micro Devices, Inc. | Method and device for layer 3 address learning |
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