WO2001071804A2

WO2001071804A2 - Lateral asymmetric lightly doped drain mosfet

Info

Publication number: WO2001071804A2
Application number: PCT/US2001/008452
Authority: WO
Inventors: Ying Xu; Dragan Danilo Nebrigic
Original assignee: The Board Of Trustees Of The University Of Illinois
Priority date: 2000-03-22
Filing date: 2001-03-16
Publication date: 2001-09-27
Also published as: WO2001071804A3; AU2001247485A1

Abstract

A lateral, asymmetric lightly doped drain MOSFET that allows for a higher packing density, reduced on-resistance and protection from voltage punch through and many short channel effects. The lateral, asymmetric lightly doped drain MOSFET includes a semiconductor surface having a first surface and a second surface, a substantially uniformly doped source region disposed at the first surface of the substrate, a drain region disposed at the first surface of the substrate defining a channel region between the source region and the drain region, a gate dielectric material disposed on the first surface of the semiconductor and a gate disposed atop the gate dielectric material. The drain region includes a first doped section and a second doped section. The second doped section is located adjacent to the channel region and is more lightly doped than the first doped section of the drain region.

Description

LATERAL ASYMMETRIC LIGHTLY DOPED DRAIN MOSFET

FIELD OF THE INVENTION

This invention relates to a sub-micron lateral MOSFET design. More particularly, the invention relates to a sub-micron lateral MOSFET design that may operate at sub-one volt voltage levels with high efficiency.

BACKGROUND OF THE INVENTION

A lateral MOSFET design is generally cheap to fabricate because the current flow structure is located close to the surface of the semiconductor substrate and the MOSFET is compatible with conventional CMOS fabrication techniques. As designers have attempted to design smaller MOSFETs having smaller gate lengths, however, decreased voltage thresholds and/or increased packing densities of the MOSFETs, several problems have intensified. When the physical dimensions such as the gate dielectric and the channel length of a MOSFET are decreased, for example, failures due to voltage punch through and short channel effects such as band-to-band tunneling, hot carrier effects, drain-to-source punch through, oxide breakdown and junction breakdown are more likely to occur. In fact, many industry standard design rules such as HP0.25um have been established to preclude fabrication of a MOSFET where the gate dielectric level or the channel length are too small to effectively prevent a failure due to voltage punch through or a short channel failure.

Because of these problems, designers have sought other MOSFET structures in order to overcome these failures. In power applications where higher conduction cuπ-ent levels are encountered, for example, designers have turned to vertical MOSFET structures in which the gate and the source are located on a first surface of a semiconductor substrate and the drain is located on the opposite surface of the semiconductor substrate. Because the channel length is located vertically, the vertical MOSFETs may be packed more densely in the surface area of a semiconductor substrate without detrimentally decreasing the channel length of the MOSFET to the point where short channel effects may cause the MOSFET to fail.

Although in some instances this may allow for relatively high current levels over traditional lateral MOS structures, the vertical structures require additional fabrication steps in order to be integrated on a single chip with a CMOS integrated circuit, which results in a more expensive fabrication process. In addition, a vertical MOSFET such as one shown in United States Patent No. 5,930,630 issued to Hshieh et al. on July 27, 1999 cannot generally operate at sub-one volt voltage levels because vertical MOSFETS are primarily designed for higher voltage operation, which requires higher junction breakdown voltages and better isolation methods to prevent failure. Further, vertical devices in which the drain is on the opposite side of the substrate or deeply embedded in the substrate have a longer current conduction path than some lateral structures resulting in higher on-resistance and reduced efficiency. Operation in lower voltage regions such as a sub-one volt region requires an ultra-low voltage threshold voltage that is difficult to achieve in a traditional vertical MOSFET design because the effective channel length is longer due to the vertical conduction path.

In other applications such as digital integrated circuits, however, where the voltage levels are low enough so that the signal level MOSFETS and power MOSFETS may be fabricated in the same CMOS technology in order to minimize costs, designers have used symmetric lightly doped drain ("LDD") lateral MOSFETS such as the one shown in United States Patent No. 5,925,914 issued to Jiang et al on July 20, 1999. In these symmetric LDD MOSFETS, the drain and source regions have symmetric lightly doped sections adjacent to or underlying the gate in an attempt to compensate for voltage punch through and short channel effects. These lightly doped sections, however, increase the surface area and the on-resistance of each individual MOSFET. Further, the asymmetric design also decreases the likelihood of band-to-band tunneling creating a parasitic diode between the gate and the drain. A typical minimum threshold voltage for a present day symmetric LDD structure MOSFET, for example, is approximately greater than or equal to about 0.5 volts for an n-type MOSFET and less than or equal to about - 0.7 volts for a p-type MOSFET. In addition, higher packing density of MOSFETs, especially in power MOSFETs, has led to heat dissipation problems. As a result, the density of the MOSFETs may be limited to ensure that the heat radiated from the MOSFETs does not cause thermal failure of any of the MOSFETS.

SUMMARY OF THE INVENTION

The invention overcomes the above-noted and other deficiencies in the prior art by providing a lateral, asymmetric lightly doped drain MOSFET and a method of manufacturing the lateral, asymmetric lightly doped drain MOSFET that may be produced as part of a single CMOS integrated circuit.

In particular, in one aspect consistent with the invention, a lateral, asymmetric lightly doped drain MOSFET design allows for a higher packing density, reduced on- resistance and protection from voltage punch through and many short channel effects. The lateral, asymmetric lightly doped drain MOSFET comprises a semiconductor surface having a first surface and a second surface, a substantially uniformly doped source region disposed at the first surface of the substrate, a drain region disposed at the first surface of the substrate defining a channel region between the source region and the drain region, a gate dielectric material disposed on the first surface of the semiconductor and a gate disposed atop the gate dielectric material. The drain region includes a first doped section and a second doped section. The second doped section is located adjacent to the channel region and is more lightly doped than the first doped section of the drain region.

These and other objects and advantages of the present invention shall be made apparent from the accompanying drawings and the detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and, together with the general description of the invention given above, and the detailed description of the embodiments given below, serve to explain the principles of the present invention. Figure 1 shows a cross-sectional view of one embodiment of a MOSFET of the present invention.

Figures 2A through 2U are cross-sectional diagrams that show various stages of forming a twin- well CMOS MOSFET in accordance with one embodiment of the present invention.

Figure 3 shows a top view of one embodiment of a multiple-finger power MOSFET module of the present invention.

Figure 4 shows a block diagram of four multiple-finger power MOSFET modules of the present invention cascaded.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a lateral, asymmetric lightly doped drain ("LDD") MOSFET that is compatible with CMOS integrated circuits. The asymmetric design of the MOSFET provides a higher packing density than a symmetric LDD MOSFET because the surface area used for the lightly doped source region of a symmetric LDD MOSFET is not required. The asymmetric LDD MOSFET of the present invention also provides a lower on-resistance, Rds-on, because the higher resistance lightly doped source region of a symmetric LDD MOSFET is removed. Further, because an enhancement MOSFET has a higher potential applied to the drain-to-gate junction than to the gate-to source junction, the lightly doped drain region of an LDD MOSFET of the present invention may be used to compensate for voltage punch through and short channel effects that are likely to occur near the drain-to-gate junction without the disadvantages inherent in the use of a lightly doped source region.

A cross sectional view of a single-well CMOS integrated circuit including an n- type MOSFET 10 of the present invention and a p-type MOSFET 60 of the present invention is shown in Figure 1. The CMOS integrated circuit is formed in a semiconductor substrate 2. In the embodiment shown in Figure 1, for example, the semiconductor substrate 2 may include a p-doped silicon substrate 4 with a p-epitaxial layer 6 in which the n-type MOSFET 10 and the p-type MOSFET 60 are formed. In this embodiment, the MOSFETs 10 and 60 include sources 20 and 70, gates 30 and 80 and drains 40 and 90, respectively. For ease of illustration of both an n-type and a p-type MOSFET of the present invention, Figure 1 shows a single- well CMOS integrated circuit configuration, i.e., both n-type and p-type MOSFETs fabricated on a single substrate. The MOSFET design of the present invention, however, may alternatively be fabricated as a double-well CMOS integrated circuit, exclusively n-type MOSFETs or exclusively p-type MOSFETs on a single substrate. Also, although the n-type and p-type MOSFETs are shown as fabricated in a p-doped substrate, the n-type and p-type MOSFETs may alternatively be fabricated in an n-doped substrate. In this embodiment, an n-type MOSFET would include a p-well and the p-type MOSFET would preferably be fabricated in the n-epitaxial layer of the substrate or in an n-well fabricated in the n- epitaxial layer of the substrate.

The source 20 of the n-type MOSFET 10 includes a source contact 22 and an n⁺ doped source region 24 formed in the semiconductor substrate 2. The source contact 22 may be formed by a doped semiconductor layer or by a conductive layer deposited on the surface of the semiconductor substrate 2. The source contact 22 is in electrical contact with the n⁺ doped source region 24. In applications where the field intensity is the area of the gate-to source junction is less than the field intensity in the area of the drain-to-gate junction such as in an enhancement MOSFET, a uniformly doped source region 24 may be used because a lightly doped region is generally not required for the source region 24 at the edge of the gate 30 or under the gate 30 in order to prevent an oxide breakdown in the area of the gate-to-source junction. This allows for a lower series resistance, Rds-on, of the n-type MOSFET 10 because the higher resistance of a lightly doped region is not required. The uniformly doped source region 24 also allows for a smaller surface area of the substrate 2 required for a single MOSFET because the lack of a more lightly doped region allows the uniformly doped source region 24 to be placed adjacent to the channel 36 and the gate dielectric 34 of the MOSFET 10. The smaller surface area required for the MOSFET 10 also allows for a higher layout density of multiple MOSFETs arranged in an array.

The n-type MOSFET 10 also includes a gate 30 that is preferably comprised of a doped polysilicon layer. The gate 30 is located atop of a gate dielectric layer 34 and may be doped in order to adjust the voltage threshold level of the MOSFET 10. The gate 30 may also include a layer of compounded silicid metal (e.g., CoSi₂, TiSi , PtSi) deposited onto the doped poly silicon layer in order to reduce the resistance of the gate 30. The gate dielectric layer 34 may be any type of gate dielectric known in the art such as silicon dioxide (Si02) or silicon nitride grown or deposited on the surface of the semiconductor substrate 2 above the channel 36 of the MOSFET 10. In one embodiment, an ultra-thin, uniform gate dielectric layer may be used to achieve ultra-low threshold voltage levels for the MOSFET 10.

The drain 40 of the n-type MOSFET 10 includes a drain contact 42 and a doped drain region 44 formed in the semiconductor substrate 2. The drain region 44 preferably includes a first doped section 46 and a second doped section 48. The second doped section 48 that all or partially underlies and/or is adjacent to the gate 30 is more lightly doped than the first doped section 46 in order to decrease the voltage concentration at the edge of the overlap of the gate and the drain regions. This improves the punch through voltage, reduces the gate-to-drain parasitic capacitance and minimizes the short channel effect of the MOSFET 10. In one embodiment, the second doped section 48 is preferably doped using a low energy level implantation step to form a shallow LDD section. In an enhancement MOSFET, for example, the field concentration in the gate-to-drain overlap region is generally higher than in the source-to-gate overlap region. An asymmetric design including a lightly doped drain section 48 but not a lightly doped source region protects against punch through problems in the gate-to-drain overlap region but also saves valuable surface area by not including a lightly doped source region where it is not necessary. Although the lower doping level of the second doped section 48 of the drain region 44 may increase the series resistance of the MOSFET 10, the overall effect of the lighter doping may be at least partially offset by doping the source contact 22 and the drain contact 42 to decrease the series resistance of the MOSFET 10. In one embodiment of the present invention, for example, the source contact 22 and the drain contact 42 may include metal layers (e.g., aluminum) disposed on the semiconductor substrate 2 that are doped and treated to lower the resistance of the contacts such as by rapid thermal annealing (RTA) and/or depositing salicid and/or tungsten on the contacts such as by chemical vapor deposition, etc. A p-base region 52 may be formed by doping a region of the semiconductor substrate 2 adjacent to the drain region 44. In this embodiment, the p-base region 52 minimizes the leakage current flow from the drain region 44 when the MOSFET is in an off-state. In one embodiment of the present invention, the p-base regions may include rounded corners such as 5 in order to more evenly distribute the electric field gradient.

The source 70 of the p-type MOSFET 60 includes a source contact 72 and a p⁺ doped source region 74. The source contact 72 may include a doped semiconductor layer or a conductive layer deposited on the surface of the semiconductor substrate 2. The source contact 72 is in electrical contact with the p doped source region 74. The source region 74, in this embodiment, is formed in an n-well 62 in the semiconductor substrate 2. Again, in an enhancement MOSFET, a uniformly doped source region 74 may be used because a lightly doped region is generally not required for the source region 74 at the edge of the gate 80 or under the gate 80. This allows for a lower series resistance, Rds- on, of the p-type MOSFET 60 because the higher resistance of a lightly doped region is not required. The uniformly doped source region 74 also allows for a smaller surface area of the substrate 2 required for a single MOSFET because the lack of a more lightly doped region allows the uniformly doped source region 74 to be placed adjacent to the channel 86 and the gate dielectric layer 84 of the MOSFET 60. The smaller surface area required for the MOSFET 60 also allows for a higher layout density of multiple MOSFETs arranged in an array.

The p-type MOSFET 60 also includes a gate 80 that is preferably comprised of a doped polysilicon layer. The gate 80 is located atop of a gate dielectric layer 84 and may be doped in order to adjust the voltage threshold level of the MOSFET 60. The gate 80 may also include a layer of compounded silicid metal (e.g., CoSi₂, TiSi , PtSi) deposited onto the doped polysilicon layer in order to reduce the resistance of the gate 80. The gate dielectric layer 84 may be any type of gate dielectric known in the art such as silicon dioxide (Si02) or silicon nitride grown or deposited on the surface of the semiconductor substrate 2 above the channel 86 of the MOSFET 60. In one embodiment, an ultra-thin, uniform gate dielectric layer may be used to achieve ultra-low threshold voltage levels for the MOSFET 60. The drain 90 of the p-type MOSFET 60 includes a drain contact 92 and a doped drain region 94. The drain region 94, in this embodiment, is formed in an n-well 62 of the semiconductor substrate 2. The drain region 94 preferably includes a first doped section 96 and a second doped section 98. The second doped section 98 that all or partially underlies and/or is adjacent to the gate 80 is doped more lightly than the first doped section 96 in order to decrease the voltage concentration at the edge of the overlap of the gate and the drain regions. This improves the punch through voltage and minimizes the short channel effect of the MOSFET 60. In one embodiment, the second doped section 98 is preferably doped using a low energy level implantation step to form a shallow LDD section. In an enhancement MOSFET, for example, the field concentration in the gate-to-drain overlap region is generally higher than in the source-to-gate overlap region. An asymmetric design including a lightly doped drain section 98 but not a lightly doped source region protects against punch through problems in the gate-to-drain overlap region but also saves valuable surface area by not including a lightly doped source region where it is not necessary. Although the lower doping level of the second doped section 98 of the drain region 44 may increase the series resistance of the MOSFET 60, the overall effect of the lighter doping may be at least partially offset by doping the source contact 72 and the drain contact 92 to decrease the series resistance of the MOSFET 60. In one embodiment of the present invention, for example, the source contact 72 and the drain contact 92 may include metal layers disposed on the semiconductor substrate 2 that are doped and treated such as by rapid thermal annealing (RTA) and have salicid and/or tungsten deposited on the contacts such as by chemical vapor deposition, etc. to lower the resistance of the contacts.

An n-base region 54 may be formed by doping a region of the semiconductor substrate 2 adjacent to the drain region 94. In this embodiment, the n-base region 54 minimizes the leakage current flow from the drain region 94 when the MOSFET is in an off-state. In one embodiment of the present invention, the n-base regions may include rounded corners such as 55 in order to more evenly distribute the electric field gradient.

A lateral, asymmetric MOSFET of the present invention may be designed to operate in a variety of applications. For example, the threshold of a particular lateral, asymmetric MOSFET of the present invention may be calculated using the following equation when Vsb=0, which may be achieved through a well-tie region, i.e., a doped region that allows for application of a voltage potential to the substrate:

Vt = φ_ms - 2φ_f - (Q_lot + Q_bo) / C_ox

(1) where φms is the work function difference between gate and substrate, φf is Fermi level of the semiconductor substrate material, which is, kT n.

'+ 'for p-type and '- 'for n-type

"f - ^ ' -' q ^N d. ope

(2) Qtot is the charge at the interface between the gate oxide and the substrate, Qbo is the charge stored in the channel region between the drain and source, and Cox is the gate oxide capacitance per unit area, which is, ε ^lox

(3) From these equations, it can be seen that the threshold voltage can be controlled through (1) control of the work functions, which are defined by substrate doping and gate doping, (2) control of the gate capacitance Cox, and (3) control of the interface charge. Control of the interface charge is generally difficult because it largely depends upon the gate voltage and the quality and uniformity of the gate oxide.

In one embodiment, an asymmetric LDD MOSFET of the present invention may be fabricated as an ultra-low voltage threshold MOSFET. The ultra-low voltage threshold MOSFET of the present invention may be used as a component in many applications in which efficient sub-one volt operation is desired such as logic circuits, memory cells, analog components, RF components, power MOSFET circuits such as power integrators, power converters and power regulators. In one embodiment, the MOSFET may be an on-chip integrated high current power MOSFET that is manufactured using CMOS technology such as 0.35 um or 0.25 um technologies. In one particular embodiment, for example, the MOSFET of the present invention may be used in power integrator circuits such as the ones disclosed in copending United States Application Serial No. 09/532,918 entitled "Dynamically-Controlled, Intrinsically Regulated Charge Pump Power Converter" filed on March 22, 2000 by Nebrigic et al. (P&G Case No. 7993) and United States Application Serial No. 60/191,138 entitled "Oscillator-less DC/DC Power Converter" filed on March 22, 2000 by Nebrigic et al. (P&G Case No. 7994P).

In a particular embodiment, the MOSFET may be designed to be a medium power MOSFET manufactured using 0.35 um CMOS technology having an ultra-low voltage threshold, a low on-resistance (Rds-on), voltage punch through resistance up to at least about 8 volts, and a low leakage current. For example, a MOSFET having a threshold voltage less than or equal to about 0.3 volts for an n-type MOSFET or greater than or equal to about -0.5 volts for a p-type MOSFET may be achieved by the present invention. A low on-resistance (Rds_on) such as less than or equal to about 0.1 ohms for an ultra- low threshold voltage MOSFET array capable of delivering at least about 0.4 watts of energy under continuous conduction may also be achieved.

For the purposes of the present invention, the term "ultra-low threshold" refers to a threshold level for an n-type MOSFET of less than about 0.5 volts. Preferably, the threshold voltage of an ultra-low threshold n-type MOSFET is less than or equal to about 0.45 volts, more preferably less than or equal to about 0.4 volts, even more preferably less than or equal to about 0.35 volts, yet even more preferably less than or equal to about 0.3 volts, even more preferably less than or equal to about 0.25 volts, and yet even more preferably less than or equal to about 0.2 volts. The term "ultra-low threshold" for a p- type MOSFET refers to a threshold level of greater than about -0.7 volts. Preferably, the threshold voltage of an ultra-low threshold p-type MOSFET is greater than or equal to about -0.65 volts, more preferably greater than or equal to about -0.6 volts, even more preferably greater than or equal to about -0.55 volts, yet even more preferably greater than or equal to about -0.5 volts, even more preferably greater than or equal to about - 0.45 volts, and yet even more preferably greater than or equal to about -0.4 volts.

In a typical CMOS process, the standard wafer substrate is a p-type silicon substrate doped by the manufacturer on the order of 1 x 10¹⁵ and has a silicon intrinsic carrier concentration, ni, at room temperature of about 1.45 x 10 i n /cm ^ . In order to achieve an ultra-low threshold, a uniform oxide having a thickness less than or equal to about 50 Angstroms is preferred. If the gate doping level is about 1.0 x 10²¹ /cm³ for an n-type MOSFET and the interface oxide charge is on the order of 1 x 10^("8), the capacitance would be about 7 x 10^("5) F/cm², φms would be about -0.649 V, φf would be about -0.29 V, the charge terms would be generally negligible compared to the work function terms, and the threshold voltage would be about -0.06 for the n-type MOSFET. A threshold voltage adjustment step may be performed in the process by ion implantation to adjust the threshold voltage level. The change of threshold voltage due to ion implantation is,

XX t = imptant ^{! C}o_X

(5)

Therefore, an implant dosage of about 1.3 x 10¹⁴ atoms/cm² may be used to achieve about a 0.3 volt threshold. Similarly, n-well doping and p+ implantation for a p- type MOSFET may be obtained.

A MOSFET of the present invention such as an ultra-low threshold MOSFET may be formed by the processes shown in Figures 2A through 2U, which depict a twin-well CMOS process performed on a p-type silicon substrate 2. The process shown in Figures 2 A through 2U is only one example of a process that may be used to produce a MOSFET of the present invention. Other processing steps or orders of processing steps are contemplated and may be used. For example, a single-well CMOS process, an NMOS process or a PMOS process may be used. Also, the order of steps listed below may be altered to achieve a MOSFET of the present invention. For example, where the order of steps is not important such as the processing steps that need to be isolated to form a portion of a p-type and an n-type MOSFET, the particular order of the processing steps may not be important.

As shown in Figure 2A, a lightly doped epitaxial layer 6 is preferably grown on a doped p-type silicon substrate 4. The native oxide is then etched from the substrate.

Alternatively, other semiconductor substrate materials such as Silicon Carbide (SiC),

Silicon Germanium (SiGe), and Silicon on Insulator (SOI) may be used as the semiconductor substrate 2.

As shown in Figures 2B and 2C, the well regions 61 and 62 for the n-type MOSFET 10 and the p-type MOSFET 60 are preferably formed such as through implantation and thermal diffusion. For example, the p-well region 61 for the n-type MOSFET 10 may be formed by masking the semiconductor substrate 2 except for the active regions of the n-type MOSFETS of the integrated circuit with mask 65, implanting a p-type dopant through the open regions of tjhe mask, and heating the semiconductor substrate 2 so that the dopant in the p-well region 61 is thermally diffused in order to achieve a uniformly doped p-well region 61. P-type dopants include boron and other elements known in the art for use as p-type dopants. P-type dopants generally include elements in Group III of the Periodic Table. One or a combination of multiple p-type dopants may be used in a particular doping step. After any implant step listed in this description, the semiconductor substrate 2 is preferably heated so that the dopant is thermally diffused in order to achieve a more uniformly doped region. An n-well region 62 of a p-type MOSFET 60 may be formed by masking the semiconductor substrate 2 except for the active regions of the p-type MOSFETS of the integrated circuit, implanting an n-type dopant through the open regions of the mask, and heating the semiconductor substrate 2 so that the dopant in the n-well region 62 is thermally diffused in order to achieve a uniformly doped n-well region 62. N-type dopants include phosphorous and/or arsenic and other elements known in the art for use as n-type dopants. N-type dopants generally include elements in Group V of the Periodic Table. One or a combination of multiple n-type dopants may be used in a particular doping step.

A channel-stop implant region 58 is preferably formed in the inactive regions between MOSFETS 10 and 60 on the semiconductor substrate 2 in order to prevent the formation of a inversion region in the semiconductor substrate 2 under the field oxide layers between adjacent transistors that might otherwise be formed from a potential applied to another portion of the integrated circuit such as a conductive metal layer that overlies a field oxide layer. As shown in Figure 2D, the channel-stop implant region 58 may be formed by masking the active regions 14 and 64 of the semiconductor substrate 2 and implanting a p-type dopant into the semiconductor substrate 2 in the inactive regions of the integrated circuit located between the transistors.

A first threshold implant of the active regions 14 and 64 may be performed in order to form the channel regions 36 and 86 of the n-type and p-type MOSFETS, respectively. As shown in Figure 2E, for example, the semiconductor substrate may be masked except for the active region of the n-type MOSFET 10. The active region of the n-type MOSFET 10 may then be implanted with an p-type dopant, and the substrate 2 may be heated to thermally diffuse the dopant in the channel region 36 in order to achieve a uniformly doped channel region 36. As shown in Figure 2F, the active region of the p- type MOSFET 60 may also be implanted with an n-type dopant such, and the substrate 2 may be heated to thermally diffuse the dopant in the channel region 86 in order to achieve a uniformly doped channel region 86.

The field oxide regions 56 may be formed by masking the active regions of the MOSFETS 10 and 60 of the integrated circuit and growing a thick thermal oxide in the inactive regions between the MOSFETS 10 and 60 as shown in Figure 2G. Then, the threshold of the active regions 14 and 64 of the n-type and p-type MOSFETS 10 and 60, respectively, are preferably optimized by performing a second threshold adjustment implantation of each active region in order to achieve better uniformity of the channel regions 36 and 86. In this step, the surface of the semiconductor substrate 2 is preferably masked except for the active regions 14 of the n-type MOSFETS 10. The active regions of the n-type MOSFETS may be implanted with a p-type dopant using a low energy level implantation such as less than about 10 KeN in order to keep the dopant material close to the surface of the substrate 2. For example, the low energy implant may be performed at about 4 KeN or about 5 KeV. The active regions 64 of the p-type MOSFETS 60 may also have a second threshold adjustment implant performed by masking the semiconductor substrate 2 except in the active regions of the p-type MOSFETS and implanting an n-type dopant in the active regions of the p-type MOSFETS using a low energy level implantation such as less than about 10 KeN in order to keep the dopant material close to the surface of the substrate 2. The low energy implant, for example, may also be performed at about 4 KeN or about 5 KeN.

Gate dielectric layers 34 and 84 may also be grown or deposited on the surface of the substrate 2 in the active regions 14 and 64 of the n-ype and the p-type MOSFETS 10 and 60 of the integrated circuit as shown in Figure 2H. The gate dielectric layers 34 and 84 may be any type of gate dielectric known in the art such as silicon dioxide (Si02) or silicon nitride grown or deposited on the surface of the semiconductor substrate 2 above the channels 36 and 86 of the MOSFETS 10 and 60. In one embodiment, for example, the gate dielectric layers 34 and 84 may be a silicon dioxide layer grown through a dry oxide process. The surface of the semiconductor substrate 2 may be cleaned using a chlorine vapor cleaning step before the gate dielectric layers 34 and 84 are grown in order to achieve a better dielectric quality, and the silicon dioxide may be grown for about 30 seconds at a temperature of about 1000 C and under a pressure of about 10 Torr. In this embodiment a thin, uniformly grown silicon dioxide layer may be grown to a thickness of about 40 Angstroms. After the dielectric growth, a thermal annealing process may also be used to further enhance the uniformity of the dielectric layer. The short time and high pressure allow for a thin dioxide layer to be grown uniformly and with less defects in order to improve the oxide punch through immunity. An ultra-thin, uniform gate dielectric layer allows for lower threshold voltage levels for the MOSFETS 10 and 60.

As shown in Figures 21 through 2L, the gates 30 and 80 may be formed atop the gate dielectric layers 34 and 84. For example, the gate may be formed by masking the surface of the substrate 2 except for the gate regions of the n-type and p-type MOSFETS 10 and 60, depositing a polysilicon layer such as by chemical vapor deposition and etching the polysilicon layer to form the gates 30 and 80 of the MOSFETS 10 and 60. The gates 30 and 80 may then be doped, for example, with an n-type dopant material such as to a level on the order of about 1 x 10 as shown in Figure 2J.

A base region, such as p-base region 52 and n-base region 54, may also be formed in the active regions of the n-type and p-type MOSFETS 10 and 60 such as shown in

Figures 2M and 2N in order to isolate the drain regions from the p-wells 61 of the n-type

MOSFETS and the n-wells 62 of the p-type MOSFETS. In an n-type MOSFET, for example, a p-base region 52 may be formed in the p-well region 61 such as shown in

Figure 2M. In this embodiment, the semiconductor substrate 2 except for the drain portions of the n-type MOSFETS may be masked, and the drain portion between the gate

30 and the field oxide 56 of each of the n-type MOSFETS may be implanted with a p- type dopant to a level on the order of about 1 x 10¹⁶, and the substrate may be heated to diffuse the dopant and to create a uniform p-base region 52. In a p-type MOSFET, however, an n-base region 54 may be formed in the n-well region 62 such as shown in

Figure 2N. In this embodiment, the semiconductor substrate 2 except for the drain portions of the p-type MOSFETS may be masked, and the drain portion between the gate

80 and the field oxide 56 of each of the p-type MOSFETS may be implanted with an n- type dopant to a level on the order of about 1 x 10¹⁶, and the substrate may be heated to diffuse the dopant and to create a uniform n-base region 54. A base region may reduce the junction capacitance and may also provide for better drain to substrate breakdown voltage.

The source regions 20 and 70 and drain regions 40 and 90 of the MOSFETS 10 and 60 may be formed by masking the integrated circuit and implanting the regions such as shown in Figures 2O and 2P. In the n-type MOSFETS, for example, the source and drain regions 20 and 40 may be implanted with an n-type dopant. In the p-type

MOSFETS, the source and drain regions 70 and 90 may be implanted with a p-type dopant. Then, the second doped sections 48 and 98 of the drains may be formed by counter-doping the portion of the drain regions 44 and 94 located adjacent to the gate as shown in Figures 2Q and 2R. For example, the second doped sections 48 and 98 may be counter-doped with a p-type dopant for the n-type MOSFETS 10 and with an n-type dopant for the p-type MOSFETS 60. Alternatively, the first doped sections 46 and 96 and the second doped sections 48 and 98 of the drain regions may be separately doped to create the desired doping levels and depths. Preferably the second doped sections 48 and

98 of the drains 40 and 90 are doped using a low energy level implantation step such as less than about 10 KeN. For example, the low energy level implantation may be performed at about 4 KeV or about 5 KeN. In one embodiment, the source region 24 of the n-type MOSFET may be uniformly doped such as to a level in the range of about 1 x

10 ¹⁷ to about 1 x 10 ¹⁸ with an n-type dopant. The first doped section 46 of the drain region 44, may be doped to a level in the range of about 1 x 10 ¹⁷to about 1 x 10¹⁸ with an n-type dopant, and the second doped section 48 may be doped to a level in the range of about 1 x 10 ^I4 to about 1 x 10 ¹⁵. The source region 74 of the p-type MOSFET may be uniformly doped such as to a level in the range of about 1 x 10 ^π to about 1 x 10 ¹⁸ with a p-type dopant. The first doped section 96 of the drain region 94, may be doped to a level in the range of about 1 x 10 ¹⁷ to about 1 x 10 ¹⁸ with a p-type dopant, and the second doped section 98 may be doped to a level in the range of about 1 x 10 ¹⁴to about 1 x 10 ¹⁵ with a p-type dopant. Guard band and well tie regions 68 and 69 may also be formed such as shown in Figures 2S and 2T. The guard band prevents latch up in the integrated circuit and the well tie serves to electrically connect the surface of the semiconductor substrate to the well region of the MOSFETS 10 and 60. The guard band and well tie functions may be performed by a single doped region in the substrate for each MOSFET such as shown in Figure 2S and 2T, or may be performed by multiple doped regions. In one embodiment, the dual purpose guard band and well tie regions 68 and 69 may be doped to a level in the range of about 1 x 10¹⁷ to 1 x 10¹⁸ with a p-type dopant for the n-type MOSFET 10 and an n-type dopant for the p-type MOSFET 60, respectively.

The gate connection lines may be formed by a first metal layer. An oxide layer may be grown such as by a chemical vapor deposition (CND) process. An opening in the oxide may be etched at the gates of the MOSFETS in order to allow the metal layer to be deposited at the gates of the MOSFETS. Preferably, each of the contacts undergoes a rapid thermal annealing (RTA) step and a salicid deposition process to reduce the contact resistance of the gate metal layer.

An inter-layer dielectric layer such as an oxide or nitride layer may be grown over the first metal layer that is electrically connected to the gates in order to isolate the metal layer from later layers. This dielectric layer may also be planarized and etched to form vias for inter-metal layer contacts.

The source and drain contacts 42 and 92 may be formed by a second metal layer that is deposited and patterned such as shown in Figure 2U. An oxide may be grown such as by a chemical vapor deposition (CVD) process. An opening in the oxide may be etched at the drain and source regions of the MOSFETS in order to allow the metal contacts to be deposited at the source and drain regions of the MOSFETS. Preferably, each of the contacts undergoes a rapid thermal annealing (RTA) step and a salicid deposition process to reduce the contact resistance of the source and drain contacts 22,

72, 42 and 92, respectively. Alternatively, the metal layers may be formed in another order. For example, the source and drain contacts may be formed in a first metal layer and the gate contact lines may be formed in a second metal layer, or each of the source, drain and gate contact lines may be formed in independent layers.

Finally, a passivation step may be performed to protect the integrated circuit. The passivation layer may be deposited and patterned to expose the bonding pads of the integrated circuit. The passivation layer, for example, may be an oxide and/or insulating polymer layer.

These steps are only exemplary. A lateral, asymmetric LDD MOSFET of the present invention may be fabricated using other techniques, orders of steps, etc. known in the art.

Where higher current driving levels are required such as in a power MOSFET application, a high current density module such as the ones shown in Figures 3 and 4 having multiple "fingers" may be used for a lateral MOSFET such as an asymmetric LDD MOSFET of the present invention or for a symmetric LDD MOSFET. A power MOSFET module may have a channel width to channel length ratio, for example, of about 1,000 to 1, about 2,000 to 1, about 5,000 to 1, about 10,000 to 1, about 20,000 to 1, about 50,000 to 1, about 100,000 to 1 and about 200,000 to 1. Due to the high channel width to channel length ratio of a power MOSFET, a slight savings in transistor or gate length may result in a significant area savings for each power MOSFET. Alternatively, a lateral, asymmetric LDD MOSFET of the present invention such as a signal MOSFET may have a channel width to length ratio, for example, of about 10:1 or about 20:1. In this case, the surface area savings is particularly significant in integrated circuits comprising many smaller MOSFETs.

A MOSFET of the present invention may be formed into a high current density module. Figure 3, for example, shows a top view of one embodiment of a high current density module 300 formed by an individual MOSFET having multiple gate "fingers."

For example, the high current density module 300 shown in Figure 3 comprises a

MOSFET having twenty gate fingers 330 arranged in two sets of ten parallel gate fingers

330 that extend away from a central gate contact line 332 along the face of the substrate.

In this embodiment, the individual fingers may share drain and source regions with each other as shown in Figure 3. Source contact lines 323 are connected to the source contacts

322 such as by via 351. Drain contact lines 343 are connected to the drain contacts 342 such as by via 353. Although Figure 3 only shows one via at each contact point for ease of illustration, each contact point may establish an electrical connection by multiple vias or any other method known in the art. In one particular embodiment of the present invention, a module 300 may also include one or more guard bands that isolate all or a portion of the MOSFET from the remainder of the substrate. As shown in Figure 3, for example, each guard band 350 isolates about one half of the overall module 300 from the remainder of the substrate and other adjacent devices. The guard band 350 may alternatively isolate all or any portion of a module 300. The guard band 350 may, for example, include an implanted region that prevents latch up between multiple modules disposed adjacent to each other on a semiconductor substrate by guarding the parasitic latch-up conduction path.

Alternatively, the module 300 may include any other number of one, two or more individual MOSFETs that together are capable of driving the desired current level. In this embodiment, the individual MOSFETs 310 may include common elements such as the common sources and drains shown in Figure 3, in order to increase the packing density of the individual MOSFETs. The module 300 may also include a common source line 323, a common gate line 332, and a common drain line 343 . The common source line 323 may be in electrical contact with the source contacts, such as source contact 322, of the individual MOSFETs 310. The common gate line 332 may be in electrical contact with the gates, such as the gate 330, of the individual MOSFETs 310. The common drain line 343 may be in electrical contact with the drain contacts, such as the drain contact 342, of the individual MOSFETs 310.

The power MOSFET also preferably provides uniform heat distribution due to the rectangular junction layout, which further provides for an even higher packing density. The rectangular layout has an optimized high current density (current per unit area) and low heating density (heat per unit area). The heat distribution may be uniform over the entire block and, therefore, may prevent an extreme hot spot, which may exist in a long strip type of layout to implement the same gate width. (Any protruding geometry such as corners may introduce a hot spot such as a high gradient change in heat distribution or current density, etc.)

The power MOSFET design of the present invention is also scaleable in an array that allows for multiple individual transistor modules to be combined to provide a desired current carrying level. The array may also include a guard band that prevents latch up between multiple arrays so that the arrays may be more easily scaleable. Multiple modules may be operated alone or may be combined into an array of modules that are scaleable in order to provide varying current levels. Figure 4, for example, shows a block diagram of an array of four modules 402, 404, 406 and 408 that may be operated in parallel to provide about four times the current driving level of a single module such as the module 300 shown in Figure 3. In this embodiment, the source lines 422, 424, 426 and 428 of each module are electrically connected to each other. Also, the gate lines 432, 434, 436 and 438 of each module are electrically connected to each other, and the drain lines 442, 444, 446 and 448 of each module are elecrtrically connected to each other. Any number of modules may be operated together in an array in^* order to allow for a variable current driving capability. Guard bands may be included to isolate each module 402, 404, 406 and 408 from the other modules in the array.

Claims

WHAT IS CLAIMED IS:

1. A MOSFET characterized by:

(a) a semiconductor substrate having a first surface and a second surface;

(b) a source region disposed at the first surface of the semiconductor substrate, the source region being substantially uniformly doped;

(c) a drain region disposed at the first surface of the semiconductor substrate and spaced apart from the source region defining a channel region between the source region and the drain region, the drain region including a first doped section and a second doped section, the second doped section being located adjacent to the channel region and being more lightly doped than the first doped section;

(d) a gate dielectric material disposed on the first surface of the semiconductor substrate adjacent to the channel region; and

(e) a gate disposed atop the gate dielectric material.

2. The MOSFET of Claim 1, further characterized in that the power transistor is an n- type MOSFET and the voltage threshold for the power transistor is less than or equal to approximately 0.3 volts.

3. The MOSFET as in any of the preceding Claims, further characterized in that the power transistor is a p-type MOSFET and the voltage threshold for the power transistor is greater than or equal to approximately -0.5 volts.

4. The MOSFET as in any of the preceding Claims, further characterized by a p-base region disposed in the semiconductor substrate between the second doped region of the drain region and the channel region.

5. The MOSFET as in any of the preceding Claims, further characterized by a n-base region disposed in the semiconductor substrate between the drain region and the channel region.

6. A method of fabricating a MOSFET characterized by the steps of:

(a) providing a semiconductor substrate including a doped epitaxial layer;

(b) forming a first threshold doped region in an active region of the semiconductor substrate;

(c) forming a gate dielectric layer on a surface of the semiconductor substrate;

(d) forming a gate atop the gate dielectric layer;

(e) forming a substantially uniformly doped source region in the semiconductor substrate at the surface of the semiconductor substrate;

(f) forming a doped drain region in the semiconductor substrate at the surface of the semiconductor substrate spaced apart from the source region defining a channel region located in the first threshold doped region below the gate, the doped drain region including a first doped section and a second doped section, the second doped section being located adjacent to the channel region and being more lightly doped than the first doped section.

7. The method of fabricating the MOSFET of Claim 6, further characterized in that the substrate is a doped p-type silicon substrate.

8. The method of fabricating the MOSFET of Claims 6 or 7, further characterized in that the substrate is a doped n-type silicon substrate.

9. A MOSFET module, characterized by:

(a) a semiconductor substrate having a first surface and a second surface;

(b) a first source region disposed at the first surface of the semiconductor substrate, the first source region being substantially uniformly doped;

(c) a drain region disposed at the first surface of the semiconductor substrate and spaced apart from the first source region defining a first channel region between the first source region and the drain region, the drain region including a first doped section and a second doped section, the second doped section being located adjacent to the first channel region and being more lightly doped than the first doped section;

(d) a first gate dielectric material disposed on the first surface of the semiconductor substrate adjacent to the first channel region;

(e) a first gate finger disposed atop the first gate dielectric material,

(f) a second source region disposed at the first surface of the semiconductor substrate and spaced apart from the drain region opposite the first source region and defining a second channel region, the first source region and the second source region being electrically connected by a common source line;

(g) second gate dielectric disposed on the first surface of the semiconductor substrate adjacent to the second channel region; and

(h) second gate finger disposed atop the second gate dielectric material, the first gate finger and a second gate finger each extending from a common gate line, the first and second gate fingers being substantially parallel.

10. The MOSFET module of Claim 9, further characterized in that the drain region includes a third doped region doped more lightly than the first doped region, the third doped region being located adjacent to the second channel region.