WO2001071416A8 - Optical logic gates with an optical correction - Google Patents

Optical logic gates with an optical correction

Info

Publication number
WO2001071416A8
WO2001071416A8 PCT/US2001/008541 US0108541W WO0171416A8 WO 2001071416 A8 WO2001071416 A8 WO 2001071416A8 US 0108541 W US0108541 W US 0108541W WO 0171416 A8 WO0171416 A8 WO 0171416A8
Authority
WO
WIPO (PCT)
Prior art keywords
optical
correction
logic gates
error correction
logic operations
Prior art date
Application number
PCT/US2001/008541
Other languages
French (fr)
Other versions
WO2001071416A9 (en
WO2001071416A1 (en
Inventor
Per Olof Hedekvist
Ashish Bhardwaj
Kerry J Vahala
Original Assignee
California Inst Of Techn
Per Olof Hedekvist
Ashish Bhardwaj
Kerry J Vahala
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by California Inst Of Techn, Per Olof Hedekvist, Ashish Bhardwaj, Kerry J Vahala filed Critical California Inst Of Techn
Priority to AU2001245821A priority Critical patent/AU2001245821A1/en
Publication of WO2001071416A1 publication Critical patent/WO2001071416A1/en
Publication of WO2001071416A8 publication Critical patent/WO2001071416A8/en
Publication of WO2001071416A9 publication Critical patent/WO2001071416A9/en

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F3/00—Optical logic elements; Optical bistable devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/35—Non-linear optics
    • G02F1/353—Frequency conversion, i.e. wherein a light beam is generated with frequency components different from those of the incident light beams
    • G02F1/3536—Four-wave interaction
    • G02F1/3538—Four-wave interaction for optical phase conjugation

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Optics & Photonics (AREA)
  • Optical Communication System (AREA)
  • Error Detection And Correction (AREA)

Abstract

An all optical logic gate comprises parallel semiconductor optical amplifiers (200, 202, 204) with input devices (215, 220, 225) for carrying out logic operations among multiple optical signals based on their wavelengths and polarization properties. The applications for the logic operations includes adding, logical inversion and error correction. The error correction can take the form of parity bit generation or correction of data bits.
PCT/US2001/008541 2000-03-17 2001-03-16 Optical logic gates with an optical correction WO2001071416A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001245821A AU2001245821A1 (en) 2000-03-17 2001-03-16 Optical logic gates with an optical correction

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US19070700P 2000-03-17 2000-03-17
US60/190,707 2000-03-17
US24138701P 2001-03-16 2001-03-16
US60/241,387 2001-03-16

Publications (3)

Publication Number Publication Date
WO2001071416A1 WO2001071416A1 (en) 2001-09-27
WO2001071416A8 true WO2001071416A8 (en) 2001-11-29
WO2001071416A9 WO2001071416A9 (en) 2002-12-19

Family

ID=26886364

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/008541 WO2001071416A1 (en) 2000-03-17 2001-03-16 Optical logic gates with an optical correction

Country Status (2)

Country Link
AU (1) AU2001245821A1 (en)
WO (1) WO2001071416A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100425374B1 (en) * 2001-11-14 2004-03-30 한국과학기술연구원 Realization Method and Apparatus of All-Optical Half Adder by Using SOA-Based Devices
CN102955323A (en) * 2012-11-15 2013-03-06 华东师范大学 Optical logic gate device on basis of coherent feedback and working method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4863247A (en) * 1986-12-29 1989-09-05 The United States Of America As Represented By The Secretary Of The Navy Optical arithmetic logic using the modified signed-digit redundant number representation
US5173905A (en) * 1990-03-29 1992-12-22 Micron Technology, Inc. Parity and error correction coding on integrated circuit addresses
US5224194A (en) * 1991-04-02 1993-06-29 At&T Bell Laboratories All-optical timing restoration

Also Published As

Publication number Publication date
WO2001071416A9 (en) 2002-12-19
AU2001245821A1 (en) 2001-10-03
WO2001071416A1 (en) 2001-09-27

Similar Documents

Publication Publication Date Title
US7538699B2 (en) Single ended pseudo differential interconnection circuit and single ended pseudo differential signaling method
EP1312091B8 (en) Memory device and method having data path with multiple prefetch i/o configurations
KR20040098904A (en) Data input circuit in memory device
KR100613463B1 (en) Data output device & output method of semiconductor device
US20080168325A1 (en) Semiconductor memory device and method for driving the same
WO2003090230A3 (en) Variable delay compensation for data-dependent mismatch in characteristic of opposing devices of a sense amplifier
WO2003009475A3 (en) Line driver
KR100613464B1 (en) Data output device & output method of semiconductor device
WO2006001910A3 (en) Memory device with a data hold latch
WO2002003459A3 (en) High-speed low-power semiconductor memory architecture
WO2002091190A3 (en) Memory with a bit line block and/or a word line block for preventing reverse engineering
Chowdhury et al. Parity checking and generating circuit with nonlinear material in all-optical domain
CN110060721A (en) A kind of dynamic RAM data transmission channel
WO2001071416A8 (en) Optical logic gates with an optical correction
US8223822B2 (en) Signal transceiver for differential data communication of ternary data and method therefor
WO2005002052A3 (en) Bi-directional buffering for memory data lines
US8045647B2 (en) Low power, high speed receiver circuit for use in a semiconductor integrated circuit
DE69621103T2 (en) Information bit sequence transmission methods with selective protection against transmission errors as well as transmission methods therewith
KR100546338B1 (en) Buffer circuit with outputting data strobe signal selectively according to the number of data bits
US7102545B2 (en) Simultaneous bidirectional input/output circuit
US20040234010A1 (en) High-speed serial link receiver with centrally controlled offset cancellation and method
WO2003043016A3 (en) A biasing technique for a high density sram
KR100604836B1 (en) Memory system employing simultaneous bi-directional input/output circuit on address bus line
JP2005236992A (en) Multi-level shifter circuit for flat panel source driver
US8750497B2 (en) Cryptographic device for implementing S-box

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: C1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: C1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

CFP Corrected version of a pamphlet front page

Free format text: REVISED ABSTRACT RECEIVED BY THE INTERNATIONAL BUREAU AFTER COMPLETION OF THE TECHNICAL PREPARATIONS FOR INTERNATIONAL PUBLICATION

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: C2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: C2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

COP Corrected version of pamphlet

Free format text: PAGES 1/15-15/15, DRAWINGS, REPLACED BY NEW PAGES 1/9-9/9; DUE TO LATE TRANSMITTAL BY THE RECEIVINGOFFICE

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase in:

Ref country code: JP

DPE2 Request for preliminary examination filed before expiration of 19th month from priority date (pct application filed from 20040101)