CN110060721A - A kind of dynamic RAM data transmission channel - Google Patents
A kind of dynamic RAM data transmission channel Download PDFInfo
- Publication number
- CN110060721A CN110060721A CN201910275496.6A CN201910275496A CN110060721A CN 110060721 A CN110060721 A CN 110060721A CN 201910275496 A CN201910275496 A CN 201910275496A CN 110060721 A CN110060721 A CN 110060721A
- Authority
- CN
- China
- Prior art keywords
- buffer
- input
- output
- phase inverter
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
Abstract
The invention discloses a kind of structures of data transmission channel, especially dynamic RAM data transmission channel, belong to dynamic RAM design field.One kind is provided has and effectively reduce chip layout area, prevents transmission line hanging, dynamic RAM data transmission channel the advantages that convenient for setting initial value.Including a plurality of data line, it is characterized in that every data transmission line is made of the bidirectional buffer of multiple serial connections, the corresponding memory block of each group of bidirectional buffer；The bidirectional buffer being wherein connected in series is made of two buffers, and the output of the first buffer is connected to the output of the second buffer, and the output of the second buffer is connected to the first buffer.The advantages that compared with the read-write data channel that multiple one-way dampers of traditional serial connection are formed, having and reduce chip layout area, prevent transmission line hanging, being convenient for setting initial value.
Description
Technical field
The invention discloses a kind of structure of data transmission channel, especially dynamic RAM data transmission channel,
Belong to dynamic RAM design field.
Background technique
Dynamic RAM (DRAM), the region with multiple memory blocks, the region of these memory blocks is properly termed as depositing
Store up core.When DRAM read operation, need to read the data for storing core memory and be transferred to input and output (DQ) module,
Again from DQ driving data to external pads；When DRAM write operation, need to be transferred to DQ mould from external pads input data
Block, DQ module drive data to storage core in.Data interaction between core and DQ is stored, is exactly logical by reading and writing data data
Road is realized.Reading and writing data channel is usually made of multiple groups transmission line.
For double data rate (DDR) DRAM, prefetching technique generally can be all used.It is newest DDR3, DDR4, low
Power consumption DDR3 (LPDDR3), low-power consumption DDR4 (LPDDR4) support the prefetching technique of 8 bits.Pass through prefetching technique, Ke Yi
In the case where not changing memory architecture, message transmission rate is maximized.
In the operating process that these above-mentioned DRAM once read and write, the data interaction bit number of core and data channel is stored
For the product for prefetching bit number Yu I/O bit wide.By taking LPDDR3 as an example, 32 I/O, 8 bits is supported to prefetch, so read-write every time
The data interaction for storing core and DQ in the process is 256 bits.The corresponding one group of transmission line of each bit, needs altogether 256 groups of biographies
Defeated line.And traditional transmission line is to be write (DW) line by 2 individual data reading (DR) lines and data and constituted, such a structure increases
The chip area of chip.
Summary of the invention
Have the object of the present invention is to provide one kind and effectively reduce chip layout area, prevent transmission line hanging, convenient for setting
The dynamic RAM data transmission channel for the advantages that determining initial value.
The multichannel read-write data channel of dynamic RAM data transmission provided by the invention includes plurality of transmission lines, often
There are the bidirectional buffer and latch of multiple serial connections on transmission lines.Each latch along transmission line be connected to two it is two-way
Between buffer.Compared with the read-write data channel that multiple one-way dampers of traditional serial connection are formed, has and reduce core
The advantages that chip layout area prevents transmission line hanging, sets initial value.
The present invention provides the multichannels of memory data transmission to read and write data channel, including a plurality of data line.
Every data transmission line is formed by the bidirectional buffer of multiple serial connections, and each group of bidirectional buffer is one corresponding
Memory block.The bidirectional buffer being wherein connected in series is made of 2 buffers, and the output of the first buffer is connected to the second buffering
The output of device, the output of the second buffer are connected to the first buffer.
Data line has reading and writes both direction, and reading direction is the bit for reading storage unit from storage array
Data are transferred to input/output block；Writing direction is that the data of a bit of external pads input are transferred to storage array.
One example of buffer includes NAND gate, nor gate, P-channel metal-oxide-semiconductor field effect transistor
(PMOS) and n channel metal oxide semiconductor field effect transistor (NMOS).Input signal is connected to the first of NAND gate
Input, enable signal are connected to the second input of NOT gate, and the output of NAND gate is connected to the grid of PMOS, and input signal is connected to
First input of nor gate, the inversion signal of enable signal are connected to the second input of nor gate, and the output of nor gate is connected to
The grid of NMOS, the drain terminal of PMOS and the drain terminal of NMOS are connected with each other and are connected to output signal.
Another example of buffer: including phase inverter, the first PMOS, the 2nd PMOS, the first NMOS and second
NMOS.Input signal is connected to the input of phase inverter, and the output of phase inverter is connected to the grid of the 2nd PMOS and the first NMOS, enables
The inversion signal of signal is connected to the grid end of the first PMOS, and the drain terminal of the first PMOS is connect with the source of the 2nd PMOS, and second
The drain terminal of the drain terminal of PMOS and the first NMOS are connected with each other and are connected to output signal, and the source of the first NMOS is with the 2nd NMOS's
Drain terminal connection, enable signal are connected to the grid end of the 2nd NMOS.
Buffer can pass through buffering active circuit activation.
Buffering active circuit includes: including serial connection first or door, second or door, third or door, the 4th or door, first
Buffer, the second buffer, third buffer, the 4th buffer.First or door, second or door, third or door, the 4th or door
Each output is connected respectively to the first buffer, the second buffer, third buffer, the 4th buffer, each to activate or disable
From buffer.
Another data line of the invention is achieved in that be formed by the bidirectional buffer of multiple serial connections, and every two
There is a latch between a bidirectional buffer, it is in addition to this identical as previous data path.
Latch includes the first phase inverter and the second phase inverter and NMOS.One power on signal is added to NMOS's
On grid.The drain terminal of NMOS connects the input terminal of the first phase inverter and the output end of the second phase inverter, generates read-write data-signal,
Data line for each reading and writing data channel.The output of first phase inverter is connected to the input of the second phase inverter.
Another implementation of latch: including the first phase inverter and the second phase inverter and PMOS.Power on signal is added
Onto the grid of PMOS.The source of PMOS connects the input terminal of the first phase inverter and the output end of the second phase inverter, generates read-write data
Signal, the data line for each reading and writing data channel.The output of first phase inverter is connected to the input of the second phase inverter.
Another implementation of latch: including phase inverter and NAND gate.Power on signal is input into the second of NAND gate
A input.The output of phase inverter is input into first input of NAND gate.The input of phase inverter is connected with the output of NAND gate
Together, read-write data-signal, the data line applied to each reading and writing data channel are generated.
Another implementation of latch: including phase inverter and nor gate.Power on signal is input into the second of nor gate
A input.The output of phase inverter is input into first input of nor gate.The input of phase inverter is connected with the output of nor gate
Together, read-write data-signal, the data line applied to each reading and writing data channel are generated.
A kind of dynamic RAM data transmission channel, including a plurality of data line, it is characterized in that
Every data transmission line is made of the bidirectional buffer of multiple serial connections, the corresponding storage of each group of bidirectional buffer
Block；The bidirectional buffer being wherein connected in series is made of two buffers, and the output of the first buffer is connected to the second buffer
Output, the output of the second buffer is connected to the first buffer.
A kind of dynamic RAM data transmission channel, including a plurality of data line；It is characterized in that
Every data transmission line is made of the bidirectional buffer of multiple serial connections, there is a lock between every two bidirectional buffer
Storage, the corresponding memory block of each bidirectional buffer.
The bidirectional buffer is made of two buffers, and the output of the first buffer is connected to the defeated of the second buffer
Out, the output of the second buffer is connected to the input of the first buffer.
The data line has reading and writes both direction, and reading direction is read storage unit from storage array one
The data of bit are transferred to input/output block；Writing direction is that the data of a bit of external pads input are transferred to storage battle array
Column.
The buffer includes NAND gate, nor gate, PMOS and NMOS.Input signal is connected to the first of NAND gate
Input, enable signal are connected to the second input of NOT gate, and the output of NAND gate is connected to the grid of PMOS, and input signal is connected to
First input of nor gate, the inversion signal of enable signal are connected to the second input of nor gate, and the output of nor gate is connected to
The grid of NMOS, the drain terminal of PMOS and the drain terminal of NMOS are connected with each other and are connected to output signal.
The buffer includes phase inverter, the first PMOS, the 2nd PMOS, the first NMOS and the 2nd NMOS.Input
Be signally attached to the input of phase inverter, the output of phase inverter is connected to the grid of the 2nd PMOS and the first NMOS, enable signal it is anti-
It connects with signal to the grid end of the first PMOS, the drain terminal of the first PMOS is connect with the source of the 2nd PMOS, the drain terminal of the 2nd PMOS
It is connected with each other and is connected to output signal with the drain terminal of the first NMOS, the source of the first NMOS is connect with the drain terminal of the 2nd NMOS,
Enable signal is connected to the grid end of the 2nd NMOS.
The latch includes the first phase inverter and the second phase inverter and NMOS.One power on signal is added to
On the grid of NMOS.The drain terminal of NMOS connects the input terminal of the first phase inverter and the output end of the second phase inverter, generates read-write number
It is believed that number, the data line for each reading and writing data channel.The output of first phase inverter is connected to the input of the second phase inverter.
The latch further includes the first phase inverter and the second phase inverter and PMOS.Power on signal is added to PMOS
Grid on.The source of PMOS connects the input terminal of the first phase inverter and the output end of the second phase inverter, generates read-write data-signal, uses
Data line in each reading and writing data channel.The output of first phase inverter is connected to the input of the second phase inverter.
The latch includes phase inverter and NAND gate, and power on signal is input into the second input of NAND gate, instead
The output of phase device is input into the first input of NAND gate, and the input of phase inverter and the output of NAND gate link together, generates
Read and write data-signal.
The latch includes phase inverter and nor gate, and power on signal is input into the second input of nor gate, reverse phase
The output of device is input into the first input of nor gate, and the input of phase inverter and the output of nor gate link together, and generates reading
Write data signal.
The buffer needs to activate by buffering active circuit.
The buffering active circuit include: including serial connection first or door, second or door, third or door, the 4th or
Door, the first buffer, the second buffer, third buffer, the 4th buffer.First or door, second or door, third or door,
Four or each output of door be connected respectively to the first buffer, the second buffer, third buffer, the 4th buffer, with activation
Or the respective buffer of disabling.
The multichannel read-write data channel of dynamic RAM data transmission channel provided by the invention includes plurality of transmission lines, often
There are the bidirectional buffer and latch of multiple serial connections on transmission lines.Each latch along transmission line be connected to two it is two-way
Between buffer.Compared with the read-write data channel that multiple one-way dampers of traditional serial connection are formed, has and reduce core
The advantages that chip layout area prevents transmission line hanging, is convenient for setting initial value.
Detailed description of the invention
Attached drawing 1 is traditional memory construction block diagram with one-way data transfer line.
Attached drawing 2 is the memory construction block diagram with bidirectional data transfers line of the invention.
Attached drawing 3,4 is buffer circuits figure of the invention.
Attached drawing 5 is the memory construction block diagram of the bidirectional data line with latch of the invention.
Attached drawing 6-9 is latch circuit figure of the invention.
Attached drawing 10 is the structure chart of the buffering active circuit of memory of the invention.
Specific embodiment
In the detailed description of following embodiment, the attached drawing in this document is referred to, these attached drawings, which illustrate, specifically may be used
With the embodiment of practice.
One typical DRAM may include eight or more memory blocks, for example, memory block 0, memory block 1, memory block 2,
Memory block 3-7, the region of these memory blocks are properly termed as storage core.Each memory block may include bit line, wordline, storage list
Member, bit line detection amplifier, part and global row decoder, column decoder etc..Each memory block can be responded to the storage
The data read/write order of block.
Embodiment one
A kind of dynamic RAM data transmission channel, including a plurality of data line, it is characterized in that
Every data transmission line is made of the bidirectional buffer of multiple serial connections, the corresponding storage of each group of bidirectional buffer
Block；The bidirectional buffer being wherein connected in series is made of two buffers, and the output of the first buffer is connected to the second buffer
Output, the output of the second buffer is connected to the first buffer.
The bidirectional buffer is made of two buffers, and the output of the first buffer is connected to the defeated of the second buffer
Out, the output of the second buffer is connected to the input of the first buffer.
The data line has reading and writes both direction, and reading direction is read storage unit from storage array one
The data of bit are transferred to input/output block；Writing direction is that the data of a bit of external pads input are transferred to storage battle array
Column.
The buffer includes NAND gate, nor gate, PMOS and NMOS.Input signal is connected to the first of NAND gate
Input, enable signal are connected to the second input of NOT gate, and the output of NAND gate is connected to the grid of PMOS, and input signal is connected to
First input of nor gate, the inversion signal of enable signal are connected to the second input of nor gate, and the output of nor gate is connected to
The grid of NMOS, the drain terminal of PMOS and the drain terminal of NMOS are connected with each other and are connected to output signal.
The buffer includes phase inverter, the first PMOS, the 2nd PMOS, the first NMOS and the 2nd NMOS.Input
Be signally attached to the input of phase inverter, the output of phase inverter is connected to the grid of the 2nd PMOS and the first NMOS, enable signal it is anti-
It connects with signal to the grid end of the first PMOS, the drain terminal of the first PMOS is connect with the source of the 2nd PMOS, the drain terminal of the 2nd PMOS
It is connected with each other and is connected to output signal with the drain terminal of the first NMOS, the source of the first NMOS is connect with the drain terminal of the 2nd NMOS,
Enable signal is connected to the grid end of the 2nd NMOS.
The buffer needs to activate by buffering active circuit.
The buffering active circuit include: including serial connection first or door, second or door, third or door, the 4th or
Door, the first buffer, the second buffer, third buffer, the 4th buffer.First or door, second or door, third or door,
Four or door, each output be connected respectively to the first buffer, the second buffer, third buffer, the 4th buffer, with activation
Or the respective buffer of disabling.
Embodiment two
A kind of dynamic RAM data transmission channel, including a plurality of data line；It is characterized in that
Every data transmission line is made of the bidirectional buffer of multiple serial connections, there is a lock between every two bidirectional buffer
Storage, the corresponding memory block of each bidirectional buffer.
The bidirectional buffer is made of two buffers, and the output of the first buffer is connected to the defeated of the second buffer
Out, the output of the second buffer is connected to the input of the first buffer.
The data line has reading and writes both direction, and reading direction is read storage unit from storage array one
The data of bit are transferred to input/output block；Writing direction is that the data of a bit of external pads input are transferred to storage battle array
Column.
The buffer includes NAND gate, nor gate, PMOS and NMOS.Input signal is connected to the first of NAND gate
Input, enable signal are connected to the second input of NOT gate, and the output of NAND gate is connected to the grid of PMOS, and input signal is connected to
First input of nor gate, the inversion signal of enable signal are connected to the second input of nor gate, and the output of nor gate is connected to
The grid of NMOS, the drain terminal of PMOS and the drain terminal of NMOS are connected with each other and are connected to output signal.
The buffer includes phase inverter, the first PMOS, the 2nd PMOS, the first NMOS and the 2nd NMOS.Input
Be signally attached to the input of phase inverter, the output of phase inverter is connected to the grid of the 2nd PMOS and the first NMOS, enable signal it is anti-
It connects with signal to the grid end of the first PMOS, the drain terminal of the first PMOS is connect with the source of the 2nd PMOS, the drain terminal of the 2nd PMOS
It is connected with each other and is connected to output signal with the drain terminal of the first NMOS, the source of the first NMOS is connect with the drain terminal of the 2nd NMOS,
Enable signal is connected to the grid end of the 2nd NMOS.
The latch includes the first phase inverter and the second phase inverter and NMOS.One power on signal is added to
On the grid of NMOS.The drain terminal of NMOS connects the input terminal of the first phase inverter and the output end of the second phase inverter, generates read-write number
It is believed that number, the data line for each reading and writing data channel.The output of first phase inverter is connected to the input of the second phase inverter.
The latch further includes the first phase inverter and the second phase inverter and PMOS.Power on signal is added to PMOS
Grid on.The source of PMOS connects the input terminal of the first phase inverter and the output end of the second phase inverter, generates read-write data-signal, uses
Data line in each reading and writing data channel.The output of first phase inverter is connected to the input of the second phase inverter.
The latch includes phase inverter and NAND gate, and power on signal is input into the second input of NAND gate, instead
The output of phase device is input into the first input of NAND gate, and the input of phase inverter and the output of NAND gate link together, generates
Read and write data-signal.
The latch includes phase inverter and nor gate, and power on signal is input into the second input of nor gate, reverse phase
The output of device is input into the first input of nor gate, and the input of phase inverter and the output of nor gate link together, and generates reading
Write data signal.
The buffer needs to activate by buffering active circuit.
The buffering active circuit include: including serial connection first or door, second or door, third or door, the 4th or
Door, the first buffer, the second buffer, third buffer, the 4th buffer.First or door, second or door, third or door,
Four or each output of door be connected respectively to the first buffer, the second buffer, third buffer, the 4th buffer, with activation
Or the respective buffer of disabling.
The physical circuit of above-mentioned two embodiment is described as follows:
Fig. 1 illustrates the memory block diagram of traditional data transmission channel with one-way data transfer line.In order to facilitate saying
It is bright, 2 groups of data lines are illustrated only in figure, other data lines are not shown.Each memory block in DRAM can lead to
Storage array i to i+m and storage array j to j+n is crossed to realize.Such as memory block 0 can be realized with storage array i, storage
Block 4 can be realized with storage array j.Memory block 1 can realize that memory block 5 can use storage array j+1 with storage array i+1
It realizes, etc..Transmission line 22a includes two one-way buffer lines, when issuing DRAM read command, along direction input/output block 14
Alignment buffer (data reading line) DR<k>, the data bit k for will be read from memory block be transferred to input/output block 14；Work as sending
When DRAM write order, along alignment buffer (data the write line) DW<k>for being directed toward memory block, being used for will be defeated from input/output block 14
The data bit z entered is transferred to memory block.Transmission line 22b includes two one-way buffer lines, for being directed toward the slow of input/output block 14
Breast the tape DR<k+1>, and the data bit k+1 for will read from memory block is transferred to input/output block 14；For being directed toward memory block
Alignment buffer DW<k+1>, the data bit z+1 for will input from input/output block 14 is transferred to memory block.Every group of one-way data
Transmission line occupies the arrangement space of 2 lines on domain, and the data line if necessary to transmission is relatively more, then may increase chip
Final area.
Fig. 2 illustrates the memory block diagram of the data transmission channel with bidirectional data transfers line of the invention.For side
Just illustrate, 2 groups of data lines are illustrated only in figure, and other data lines are not shown.With one-way data transfer shown in FIG. 1
Line is compared, and every group of bidirectional data transfers line is realized by the bidirectional buffer of multiple serial connections, and 1 line is only taken up on domain
Arrangement space, such as data line DRW<k>.The bidirectional buffer being wherein connected in series is made of 2 buffers, the first buffering
The output of device is connected to the output of the second buffer, and the output of the second buffer is connected to the input of the first buffer.Each
The bidirectional buffer of serial connection can be used for reading data from corresponding memory block or data be written to corresponding memory block.Such as
When issuing DRAM read command, transmission line 22c can pass through the alignment buffer from each storage array i to i+m or j to j+n
DRW<k>is realized, for the kth position data of memory block to be transferred to input/output block 14；The bidirectional buffer 22d of serial connection
DRW<k+1>can be realized by the alignment buffer from each storage array i to i+m or j to j+n, for by the of memory block
K+1 data are transferred to input/output block 14.
In addition when issuing DRAM write order, another buffer line DRW<k>of the bidirectional buffer 22c of serial connection
Each storage array i to i+m can be arrived by input/output block 14, storage array j to j+n is realized, is used for external pads
Data z of input are transferred to memory block from input/output block 14.In addition, the bidirectional buffer 22d's of serial connection is another
A buffer line DRW<k+1>can arrive each storage array i to i+m by input/output block 14, and storage array j to j+n comes real
Existing, data z+1 for inputting external pads are transferred to memory block from input/output block 14.According to memory block to input
Output block needs the quantity of the bit number transmitted and memory block, and the present invention is adapted to include number of transmission lines and number of buffers
The variation of amount.
Fig. 3-4 illustrates buffer block diagram of the invention.Buffer can be realized by a variety of circuits, illustrate this electricity
Road, help understand the present invention.
With reference to Fig. 3, buffer includes NAND gate 25, nor gate 26, PMOS 27 and NMOS 28.Input signal In connection
To the first input of NAND gate 25, enable signal EN is connected to the second input of NOT gate 25, and the output of NAND gate 25 is connected to
The grid of PMOS 27, input signal In are connected to the first input of nor gate 26, and the inversion signal ENB of enable signal EN is connected to
Second input of nor gate 26, the output of nor gate 26 are connected to the grid of NMOS 28, the leakage of the drain terminal and NMOS 28 of PMOS 27
End is connected with each other and is connected to output signal Out.
With reference to Fig. 4, buffer includes phase inverter 30, PMOS 31, PMOS 32, NMOS 33 and NMOS 34.Input letter
Number In is connected to the input of phase inverter 30, and the output of phase inverter 30 is connected to the grid of PMOS 32 and NMOS 33, nor gate 31
Output is connected to the grid of NMOS 33, and the inversion signal ENB of enable signal EN is connected to the grid end of PMOS 31, the leakage of PMOS 31
End is connect with the source of PMOS 32, and the drain terminal of PMOS 32 and the drain terminal of NMOS 33 are connected with each other and are connected to output signal
The source of Out, NMOS 33 is connect with the drain terminal of NMOS 34, and enable signal EN is connected to the grid end of NMOS 31.
Fig. 5 illustrates the memory block diagram with the bidirectional data line with latch of the invention.In certain embodiments,
The bidirectional buffer 22c and 22d of serial connection can also include latch 42.Each latch 42 is connected to two along transmission line
Between bidirectional buffer, the bidirectional buffer 22c and 22d of serial connection.By setting high or low voltage for respective route,
Latch 42 can prevent transmission line hanging.Latch 42 can be existed by powering on the control of (pwrup#) signal for transmission line to be arranged
Original state when powering on.
Fig. 6-9 illustrates latch circuit of the invention.Latch can be realized by a variety of circuits.Different locks can be used
Storage keeps the voltage characteristic of buffer, illustrates this circuit, help understands the present invention.
With reference to Fig. 6, latch includes phase inverter 50 and 52 and NMOS 54.One pwrup# signal is added to NMOS
On 54 grid.The input terminal of the drain terminal connection phase inverter 50 of NMOS 54 and the output end of phase inverter 52, generate RW_Data signal,
Data line for each reading and writing data channel.The output of phase inverter 50 is connected to the input of phase inverter 52.
As shown in fig. 7, latch includes phase inverter 56 and 58 and PMOS 60.Pwrup# signal is added to PMOS 60
Grid on.The input terminal of the source connection phase inverter 56 of PMOS 60 and the output end of phase inverter 58, generate RW_Data signal, are used for
The data line in each reading and writing data channel.The output of phase inverter 56 is connected to the input of phase inverter 58.
With reference to Fig. 8, latch includes phase inverter 62 and NAND gate 64.Pwrup# signal is input into the second of NAND gate 64
Input.The output of phase inverter 62 is input into the first input of NAND gate 64.The input of phase inverter 62 and the output of NAND gate 64
It links together, generates RW_Data signal, the data line applied to each reading and writing data channel.
With reference to Fig. 9, latch includes phase inverter 66 and nor gate 68.Pwrup# signal is input into the second of nor gate 68
Input.The output of phase inverter 66 is input into the first input of nor gate 68.The output of nor gate 68 is connected to phase inverter 66
Input generates RW_Data signal, the data line applied to each reading and writing data channel.
Figure 10 illustrates the buffering active circuit of memory of the present invention.The enable signal of buffer can be by buffering activation electricity
Road generates.A kind of buffer activity circuit, the buffer 81-84 including serial connection or door 71-74 and data read/write channel 80.
Or each output of door 71-74 is connected to one of buffer 81-84, to activate or disable respective buffer 81-84.Based on string
Row connection or door 71-74, if one of them of data bit 1-4 be it is high, the data bit is corresponding or goalkeeper exports high letter
Number buffer connected to it.The high RST of output along serial connection or door line transmit, also along this route open
Buffer.Therefore or buffer corresponding to door will be activated enabling, and the buffer for driving high data bit to activate from one to
The buffer of next activation.
For example, it is assumed that data bit 1,3,4 be it is low, and data bit 2 is high, then or door 72 will export a high RST because
Its input is high data bit 2.Or door 72 will export a high RST to buffer 82 and/or door 73.High RST can edge or door chain
Propagate downwards, including or door 73 and 74, and activate buffer 83 and 84.Another or door 71 and buffer 81 do not activate, because
It is low for data bit 1.
Those skilled in the art can increase or decrease according to the design and requirement of different memory for buffering
Active circuit and data read/write channel or door and reading and writing data buffer quantity.In addition, other equivalent circuits can be used for
Realize buffer activity method of the invention.
Although the present invention is described some embodiments, it is to be appreciated that the invention is not limited to
These embodiments.On the contrary, the present invention is understood that and explains in its broadest sense, as claim is reflected.Cause
This, these claims are construed as not only including equipment described here, method and system, every other and into one
The change and modification of step will be apparent from for having the people of common skill in this respect.
Claims (12)
1. a kind of dynamic RAM data transmission channel, including a plurality of data line, it is characterized in that every data transmits
Line is made of the bidirectional buffer of multiple serial connections, the corresponding memory block of each group of bidirectional buffer；Wherein it is connected in series
Bidirectional buffer be made of two buffers, the output of the first buffer is connected to the output of the second buffer, the second buffering
The output of device is connected to the first buffer.
2. a kind of dynamic RAM data transmission channel, including a plurality of data line；It is characterized in that every data transmission
Line is made of the bidirectional buffer of multiple serial connections, has a latch between every two bidirectional buffer, each is two-way
Buffer corresponds to a memory block.
3. dynamic RAM data transmission channel according to claim 1 or 2, it is characterized in that the bidirectional buffering
Device is made of two buffers, and the output of the first buffer is connected to the output of the second buffer, and the output of the second buffer connects
It is connected to the input of the first buffer.
4. dynamic RAM data transmission channel according to claim 1 or 2, it is characterized in that the data are transmitted
Line has reading and writes both direction, read direction be the data for the bit that storage unit is read are transferred to from storage array input it is defeated
Block out；Writing direction is that the data of a bit of external pads input are transferred to storage array.
5. dynamic RAM data transmission channel according to claim 1 or 2, it is characterized in that the buffer packet
NAND gate, nor gate, PMOS and NMOS are included, input signal is connected to the first input of NAND gate, and enable signal is connected to non-
Second input of door, the output of NAND gate are connected to the grid of PMOS, and input signal is connected to the first input of nor gate, enables
The inversion signal of signal is connected to the second input of nor gate, and the output of nor gate is connected to the grid of NMOS, the drain terminal of PMOS and
The drain terminal of NMOS is connected with each other and is connected to output signal.
6. dynamic RAM data transmission channel according to claim 1 or 2, it is characterized in that the buffer packet
Phase inverter, the first PMOS, the 2nd PMOS, the first NMOS and the 2nd NMOS are included, input signal is connected to the input of phase inverter,
The output of phase inverter is connected to the grid of the 2nd PMOS and the first NMOS, and the inversion signal of enable signal is connected to the grid of the first PMOS
End, the drain terminal of the first PMOS are connect with the source of the 2nd PMOS, and the drain terminal of the 2nd PMOS and the drain terminal of the first NMOS are connected with each other
And it is connected to output signal, the source of the first NMOS is connect with the drain terminal of the 2nd NMOS, and enable signal is connected to the 2nd NMOS's
Grid end.
7. dynamic RAM data transmission channel according to claim 2, it is characterized in that the latch includes
First phase inverter and the second phase inverter and NMOS, a power on signal are added on the grid of NMOS,
The drain terminal of NMOS connects the input terminal of the first phase inverter and the output end of the second phase inverter, generates read-write data-signal, the
The output of one phase inverter is connected to the input of the second phase inverter.
8. dynamic RAM data transmission channel according to claim 2, it is characterized in that the latch also wraps
It includes the first phase inverter and the second phase inverter and PMOS, power on signal is added on the grid of PMOS, the source connection first of PMOS is anti-
The output end of the input terminal of phase device and the second phase inverter generates read-write data-signal, and it is anti-that the output of the first phase inverter is connected to second
The input of phase device.
9. dynamic RAM data transmission channel according to claim 2, it is characterized in that the latch packet
Phase inverter and NAND gate are included, power on signal is input into the second input of NAND gate, and the output of phase inverter is input into NAND gate
The first input, the input of phase inverter and the output of NAND gate links together, and generates read-write data-signal.
10. dynamic RAM data transmission channel according to claim 2, it is characterized in that the latch includes
Phase inverter and nor gate, power on signal are input into the second input of nor gate, and the output of phase inverter is input into nor gate
First input, the input of phase inverter and the output of nor gate link together, and generate read-write data-signal.
11. dynamic RAM data transmission channel according to claim 3, it is characterized in that the buffer needs
It is activated by buffering active circuit.
12. dynamic RAM data transmission channel according to claim 11, it is characterized in that the buffering activates
Circuit includes: including serial connection first or door, second or door, third or door, the 4th or door, the first buffer, the second buffering
Device, third buffer, the 4th buffer, first or door, second or door, third or door, the 4th or each output of door connect respectively
It is connected to the first buffer, the second buffer, third buffer, the 4th buffer, to activate or disable respective buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910275496.6A CN110060721A (en) | 2019-04-08 | 2019-04-08 | A kind of dynamic RAM data transmission channel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910275496.6A CN110060721A (en) | 2019-04-08 | 2019-04-08 | A kind of dynamic RAM data transmission channel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110060721A true CN110060721A (en) | 2019-07-26 |
Family
ID=67318486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910275496.6A Pending CN110060721A (en) | 2019-04-08 | 2019-04-08 | A kind of dynamic RAM data transmission channel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110060721A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023123649A1 (en) * | 2021-12-29 | 2023-07-06 | 长鑫存储技术有限公司 | Integrated circuit structure, memory and integrated circuit layout |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1038171A (en) * | 1988-05-26 | 1989-12-20 | 浙江大学 | The distance tracking method of continuous probe moving object |
| US6622213B2 (en) * | 2000-08-09 | 2003-09-16 | Via Technologies, Inc. | Two-way cache system and method for interfacing a memory unit with a peripheral device using first and second cache data regions |
| CN1495896A (en) * | 2002-08-23 | 2004-05-12 | ���ش�洢����ʽ���� | Storage system and data transmission method |
| US20050104622A1 (en) * | 2003-11-18 | 2005-05-19 | Admtek Incorporated | Output buffer with low-voltage devices to driver high-voltage signals for PCI-X applications |
| CN101051528A (en) * | 2006-04-04 | 2007-10-10 | 联发科技股份有限公司 | Memory controller with bi-directional buffer for high speed access data and related method thereof |
| CN101617242A (en) * | 2007-02-23 | 2009-12-30 | 美光科技公司 | I/O compression in the integrated circuit and pin reduce |
| JP2013142951A (en) * | 2012-01-10 | 2013-07-22 | Renesas Electronics Corp | Information processing device and communication method |
| JP2015164083A (en) * | 2014-02-28 | 2015-09-10 | マイクロン テクノロジー， インク． | semiconductor device |
| US20170062039A1 (en) * | 2015-08-26 | 2017-03-02 | eveRAM Technology America, Inc. | Memory device that supports multiple memory configurations |
| CN109154919A (en) * | 2016-05-19 | 2019-01-04 | 美光科技公司 | To execute the device and method of internal module data/address bus reverse phase |
| CN109313617A (en) * | 2016-07-01 | 2019-02-05 | 英特尔公司 | Load reduced non-volatile memory interface |
-
2019
- 2019-04-08 CN CN201910275496.6A patent/CN110060721A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1038171A (en) * | 1988-05-26 | 1989-12-20 | 浙江大学 | The distance tracking method of continuous probe moving object |
| US6622213B2 (en) * | 2000-08-09 | 2003-09-16 | Via Technologies, Inc. | Two-way cache system and method for interfacing a memory unit with a peripheral device using first and second cache data regions |
| CN1495896A (en) * | 2002-08-23 | 2004-05-12 | ���ش�洢����ʽ���� | Storage system and data transmission method |
| US20050104622A1 (en) * | 2003-11-18 | 2005-05-19 | Admtek Incorporated | Output buffer with low-voltage devices to driver high-voltage signals for PCI-X applications |
| CN101051528A (en) * | 2006-04-04 | 2007-10-10 | 联发科技股份有限公司 | Memory controller with bi-directional buffer for high speed access data and related method thereof |
| CN101617242A (en) * | 2007-02-23 | 2009-12-30 | 美光科技公司 | I/O compression in the integrated circuit and pin reduce |
| JP2013142951A (en) * | 2012-01-10 | 2013-07-22 | Renesas Electronics Corp | Information processing device and communication method |
| JP2015164083A (en) * | 2014-02-28 | 2015-09-10 | マイクロン テクノロジー， インク． | semiconductor device |
| US20170062039A1 (en) * | 2015-08-26 | 2017-03-02 | eveRAM Technology America, Inc. | Memory device that supports multiple memory configurations |
| CN109154919A (en) * | 2016-05-19 | 2019-01-04 | 美光科技公司 | To execute the device and method of internal module data/address bus reverse phase |
| CN109313617A (en) * | 2016-07-01 | 2019-02-05 | 英特尔公司 | Load reduced non-volatile memory interface |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023123649A1 (en) * | 2021-12-29 | 2023-07-06 | 长鑫存储技术有限公司 | Integrated circuit structure, memory and integrated circuit layout |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6798711B2 (en) | Memory with address management | |
| US7035161B2 (en) | Semiconductor integrated circuit | |
| US5301142A (en) | Semiconductor memory | |
| KR20040098904A (en) | Data input circuit in memory device | |
| JPH0522997B2 (en) | ||
| US7161867B2 (en) | Semiconductor memory device | |
| US7532538B2 (en) | Tri-state output driver arranging method and memory device using the same | |
| US7283420B2 (en) | Multi-port memory device | |
| US6378008B1 (en) | Output data path scheme in a memory device | |
| US7173864B2 (en) | Data latch circuit and semiconductor device using the same | |
| US8054699B2 (en) | Semiconductor memory device having a double branching bidirectional buffer | |
| CN101425331A (en) | Clock control circuit and data alignment circuit including the same | |
| KR100372247B1 (en) | semiconductor memory device having prefetch operation mode and data transfer method for reducing the number of main data lines | |
| CN104252875A (en) | Semiconductor integrated circuit | |
| US6219283B1 (en) | Memory device with local write data latches | |
| CN110060721A (en) | A kind of dynamic RAM data transmission channel | |
| US5598371A (en) | Data input/output sensing circuit of semiconductor memory device | |
| CN209657808U (en) | A kind of dynamic RAM data transmission channel | |
| KR100402045B1 (en) | Semiconductor memory device improving data read-out access | |
| US6678201B2 (en) | Distributed FIFO in synchronous memory | |
| US6714475B2 (en) | Fast accessing of a memory device using decoded address during setup time | |
| US7042791B2 (en) | Multi-port memory device with global data bus connection circuit | |
| US7046575B2 (en) | Bus connection circuit for read operation of multi-port memory device | |
| KR20020054506A (en) | method for maintaining data coherency in late-select type semiconductor memory device and data coherency maintaining circuit therefore | |
| KR100546297B1 (en) | Semiconductor integrated circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190726 |
|
| RJ01 | Rejection of invention patent application after publication |