WO2001069658A2 - Element antifusible programmable une seule fois et procede associe - Google Patents

Element antifusible programmable une seule fois et procede associe Download PDF

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Publication number
WO2001069658A2
WO2001069658A2 PCT/US2001/007175 US0107175W WO0169658A2 WO 2001069658 A2 WO2001069658 A2 WO 2001069658A2 US 0107175 W US0107175 W US 0107175W WO 0169658 A2 WO0169658 A2 WO 0169658A2
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WO
WIPO (PCT)
Prior art keywords
doped region
fuse element
process flow
poly diode
time programmable
Prior art date
Application number
PCT/US2001/007175
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English (en)
Other versions
WO2001069658A3 (fr
Inventor
Todd Mitchell
Original Assignee
Philips Semiconductors, Inc.
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Semiconductors, Inc., Koninklijke Philips Electronics N.V. filed Critical Philips Semiconductors, Inc.
Priority to JP2001567025A priority Critical patent/JP2003526941A/ja
Priority to EP01918392A priority patent/EP1208597A2/fr
Publication of WO2001069658A2 publication Critical patent/WO2001069658A2/fr
Publication of WO2001069658A3 publication Critical patent/WO2001069658A3/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Definitions

  • the present disclosure relates to a one time programmable anti-fuse element and method. Specifically, the present invention relates to forming a one time programmable anti-fuse element on a semiconductor substrate.
  • a specified amount of current is passed through the element in order to "blow” (destroy) the element. This destruction is irreversible, thus the term “one time programmable.”
  • By "blowing" the one time programmable anti-fuse element conductive pathways can be selectively formed.
  • One time programmable anti-fuse elements can be used in security applications such as setting private individuals preferences in electronic equipments (e.g., a CD. player).
  • a blown anti-fuse element is less detectable offers better security because private information entered by the user becomes more difficult to detect.
  • a prior art approach uses an amorphous silicon based process to form the one time programmable anti-fuse element.
  • amorphous silicon based process used to form the one time programmable anti-fuse element.
  • steps are a sputtering step, a masking step, and a etching step that do not ordinarily occur in an existing standard semiconductor device formation process flow.
  • a sputtering step a sputtering step
  • a masking step a masking step
  • etching step that do not ordinarily occur in an existing standard semiconductor device formation process flow.
  • Each of these steps requires its own stepper. As a result, performing these steps perturbs the standard process flow.
  • a semiconductor substrate 100 such as, for example, silicon
  • An oxide layer 110 has been shown deposited on substrate 100.
  • An amorphous silicon 111 has been formed on oxide layer 110.
  • Amorphous silicon 111 functions as the one time programmable anti-fuse element.
  • a metallic layer 122 touches one end of amorphous silicon 111 while another metallic layer 124 touches the other end of amorphous silicon 111.
  • another metallic layer 140 is separated from amorphous silicon 111 by inter-metallic oxide 130 (IMO 130).
  • IMO 130 inter-metallic oxide 130
  • two contact via etches 143-144 allow metallic layer 140 to connect to amorphous silicon 111.
  • contact via etches 143-144 are filled with conducting material such as, for example, tungsten, copper, or titanium.
  • the structure as shown in Figure 1 constitutes a one time programmable anti-fuse element because a current can be forced through amorphous silicon 111 to "blow the anti-fuse.” Specifically, as current flows into amorphous silicon 111, the current changes the phase of amorphous silicon 111 and the aerial property of amorphous silicon 111 so that amorphous silicon 111 goes from a high electric resistance phase to a low electric resistance phase. In other words, amorphous silicon 111 goes into a conductive phase.
  • substrate 100 and oxide layer 110 are deposited as in typically standard process flow.
  • amorphous silicon 111 requires a different process chamber and additional steppers.
  • amorphous silicon is blanket deposited with part of the layer etched away.
  • IMO is deposited. This process flow uses sputtering of amorphous silicon that requires special masking and special etching.
  • the present invention answers all of the needs discussed above. Furthermore, the present invention offers advantages not available in the prior art : approach.
  • the present invention provides a one time programmable anti-fuse element whose formation does not require process steps foreign to a standard semiconductor device formation process flow. Furthermore, the present invention provides a one time programmable anti-fuse element that can be produced without using amorphous silicon. Further still, the present invention provides a one time programmable anti-fuse element whose condition (e.g., blown or intact) is difficult to detect.
  • a method for creating a one time programmable anti-fuse element. Specifically, a first doped region of a poly silicon region is formed above- a shallow trench isolation (STI) region. A second doped region of the poly silicon region is also formed above the STI region. A dielectric material is deposited above the poly silicon region. In addition, a side wall spacer etch blocking mask is used to complete the formation of said poly silicon region.
  • STI shallow trench isolation
  • a side wall spacer etch blocking mask is used to complete the formation of said poly silicon region.
  • Figure 1 depicts the side sectional view of a one time programmable anti-fuse element according to a prior art approach.
  • Figure 2A depicts the side sectional view of one fabrication phase of forming a one time programmable anti-fuse element concurrently with the formation of a semiconductor device in accordance with one embodiment of the present invention.
  • Figure 2B depicts the side sectional view of another fabrication phase of forming the one time programmable anti-fuse element concurrently with the formation of the semiconductor device in accordance with the embodiment in Figure 2A.
  • Figure 2C depicts the side sectional view of another fabrication phase of forming the one time programmable anti-fuse element concurrently with the formation of the semiconductor device in accordance with the embodiment in Figure 2A.
  • Figure 2D depicts the side sectional view of another fabrication phase of forming the one time programmable anti-fuse element concurrently with the formation of the semiconductor device in accordance with the embodiment in Figure 2A.
  • Figure 2E depicts the side sectional view of another fabrication phase of forming the one time programmable anti-fuse element concurrently with the formation of the semiconductor device in accordance with the embodiment in Figure 2A.
  • Figure 2F depicts the side sectional view of another fabrication phase of forming the one time programmable anti-fuse element concurrently with the formation of the semiconductor device in accordance with the embodiment in Figure 2A.
  • Figure 2G depicts the side sectional view of another fabrication phase of forming the one time programmable anti-fuse element concurrently with the formation of the semiconductor device in accordance with the embodiment in Figure 2A.
  • Figure 2H depicts the side sectional view of another fabrication phase of forming the one time programmable anti-fuse element concurrently with the formation of the semiconductor device in accordance with one embodiment in Figure 2A.
  • Figure 3 is a flow chart outlining the steps performed in accordance with one embodiment of the present invention.
  • Figures 2A to 2H depict side sectional views of one embodiment of the present invention in progressive stages of forming a one time programmable anti-fuse element. Because these stages can also be used without perturbation to the process flow for creating a standard semiconductor device such as a transistor, the formation of the transistor is shown concurrently in the same progressive stages. However, as understood herein, the one time programmable anti- fuse element does not need to be formed concurrently with a standard semiconductor device such the transistor shown.
  • the illustrated concurrent formations of the one time programmable anti-fuse element and the transistor are meant to highlight one advantageous feature of the present invention. That is, the one time programmable anti-fuse element can be formed using the standard process flow of forming a standard semiconductor device, while not requiring process steps foreign to the standard process flow.
  • the present embodiment does not use amorphous silicon to form the one time programmable anti-fuse element. Rather, the present embodiment uses a poly diode to form the one time programmable anti-fuse element. As an added benefit not found in the prior art approach, once the poly diode is blown, the damage to the poly diode is harder to detect than the damage done to the amorphous silicon based anti-fuse device of the prior art. Thus, the present embodiment is better suited for security applications.
  • the poly diode can be formed concurrently with the existing process flow for fabricating a standard semiconductor device such as a transistor.
  • a standard semiconductor device e.g., a transistor
  • the concurrent formations to be shown highlight the fact that forming the poly diode as the one time programmable anti-fuse element does not perturb the standard process for forming a standard semiconductor device.
  • STI regions 201-203 are formed within semiconductor substrate 200 that can be, for example, silicon. STI regions 201-203 are typically filled with an oxide using high density plasma deposition process.
  • the present poly diode will be formed above STI region 201.
  • STI regions 202-203 are typically used to isolate neighboring electrical -devices.
  • a poly silicon region 222 which will become a part of a poly diode as- a one time programmable anti-fuse element, is formed above STI region 201.
  • the formation of poly silicon region 222 is adapted to be formed concurrently with the same process flow that is used to form poly silicon region 224, which will become a part of a standard semiconductor transistor.
  • poly silicon region 224 will be used as a gate of the standard semiconductor transistor.
  • poly silicon regions 222 and 224 are shown to highlight the fact that the same process flow can be used without perturbation to the process flow.
  • spacer oxide regions 231-232 and 234-235 are deposited.
  • poly silicon region 222 includes a first doped region shown as a n-doped region 213, and a second doped region shown as a p- doped region 217.
  • poly silicon region 222 is adapted to be used as a poly diode.
  • the first and second doped regions need not be doped, respectively, with n-type and p-type dopants.
  • the first and second doped regions are doped, respectively, with p-type and n-type dopants. More generally, the first and second doped regions are doped, respectively, with dopants of a first conducting type and a second conducting type.
  • spacer oxide regions 231-232 are deposited beside the ends of poly silicon region 222. Also, oxide region 233 are deposited above poly silicon region 222 to cover both n-doped " region 213 and p-doped region 217 such that two contact surfaces 281-282 are partially exposed.
  • spacer oxide regions 234-235 have been deposited beside ends of poly silicon region 224 that will become a part of the transistor.
  • the concurrent depositions of spacer oxide regions 231-232 (adjacent to poly silicon regions 222) and 234-235 (adjacent to poly silicon region 224) are shown to highlight the fact that these two depositions use the same process flow without perturbation to the process flow.
  • spacer oxide regions 231-232 and 234-235 need not be deposited concurrently.
  • a titanium layer 250 is deposited.
  • titanium layer 250 covers substrate 100, spacer oxide regions 231-232, oxide region 233, and contact surfaces 281-282.
  • poly silicon region 224 as a part of the standard semiconductor transistor, titanium layer 250 covers spacer oxide regions 234-235 and poly silicon region 224.
  • the concurrent depositions of titanium layer 250 above poly silicon regions 222 and 224 are shown to highlight the fact that these two depositions use the same process flow without perturbation to the process flow.
  • titanium layer 250 need not be deposited concurrently for both poly silicon regions 222 and 224.
  • titanium layer 250 can still be deposited above silicon region 222 for forming a one time programmable anti-fuse element.
  • RTA rapid thermal annealing
  • silicide formation occur everywhere except at chemically unreacted portions 251-255 of titanium layer 250 that touch, as shown respectively, oxide 231-235.
  • Silicide portions that are formed by RTA have low electrical resistance. As will be described in Figure 2E, these silicide portions are to be used as electrical contacts.
  • RTA is applied for both poly silicon regions 222 and 224 to highlight the fact that forming the one time programmable anti-fuse element in accordance with the present embodiment does not introduce processing steps foreign to the standard process flow for forming a standard semiconductor device such as the transistor being formed here. However, as understood herein, even without the transistor being formed here, RTA can still be applied for forming the one time programmable anti- fuse element.
  • silicide portion 262 sits above contact surface 281 to form the electrical contact for n-doped region 213, whereas silicide portion 263 sits above contact surface 283 to form the electrical contact for p-doped region 217.
  • silicide portions 265-267 become, respectively, the electrical contacts for drain, gate, and source of the semiconductor transistor.
  • FIG 2E the concurrent etchings of titanium layer 250 above poly silicon regions 222 and 224 are shown to highlight the fact that these two etchings use the same process flow without perturbation to the process flow.
  • titanium layer 250 need not be etched concurrently for both poly silicon regions 222 and 224.
  • titanium layer 250 can still be etched above silicon region 222 for forming a one time programmable anti-fuse element.
  • inter-metallic oxide (IMO) 270 is deposited as shown. Also as shown, concurrently with the formation of contact via etches 273-275 within IMO 270, contact via etches 271-272 have been formed within IMO 270.
  • IMO inter-metallic oxide
  • contact via etches 271-272 for the one time programmable anti-fuse element
  • 273- 275 for the transistor being formed
  • contact via etches 271-272 for the one time programmable anti-fuse element need not be formed concurrently with contact via etches 273-275 for the transistor being formed.
  • contact via etches 271-272 can still be formed above silicon region 222 for forming the one time programmable anti-fuse element.
  • contact via etches 271-275 are filled, respectively, with conducting plugs such as, for example, tungsten plugs 291-295.
  • planarization such as, for example, chemical mechanical polishing (CMP) is performed so that the exposed surface of IMO 270 is level with the exposed ends of tungsten plugs 291-295.
  • CMP chemical mechanical polishing
  • planarization is applied for tungsten plugs 291-292 (for poly silicon regions 222) and 293-295 (for poly silicon region 224) to highlight the fact that forming the one time programmable anti-fuse element in accordance with the present embodiment does not introduce processing steps foreign to the standard process flow for forming a standard semiconductor device such as the transistor being formed here. However, as understood herein, even without the transistor being formed here, planarization can still be applied for forming the one time programmable anti-fuse element.
  • a metallic layer 290 is deposited above IMO 270. Specifically, metallic layer 290 connects electrically to poly silicon region 222 through both tungsten plugs 291-292 and silicide contacts 262- 263. Also, metallic layer 290 connects electrically to drain, gate, and source of the semiconductor transistor through, respectively, tungsten plugs 293- 295. Thus, formation of the electric paths from metallic layer 290 to poly silicon region 222 does not perturb the existing standard process flow for forming the standard semiconductor transistor (or any other standard semiconductor device).
  • poly silicon region 222 can be programmed by driving a forward biased electric current through poly silicon region 222 from metallic layer 290..
  • the forward biased electric current travels from metallic layer 290 through tungsten plug 291 and silicide contact 262 to enter n-doped region 213.
  • the forward biased electric current travels to p-doped region 217, through silicide contact 263 and tungsten plug 292 to reach metallic layer 290.
  • poly silicon region 222 As the electric current travels through poly silicon region 222, poly silicon region 222 is "blown" (i.e., destroyed) as a one time programmable anti-fuse element, thereby forming conducting path from n-doped region 213 to p- doped region 217.
  • FIG. 3 is a flow chart outlining steps performed in accordance with one embodiment of the present invention.
  • STI regions are formed in a semiconductor substrate.
  • Standard semiconductor device such as a transistor is typically fabricated in the region between two STI regions. Nevertheless, according to the present embodiment, a one time programmable anti-fuse element will be formed using a poly silicon region above one of the STI regions.
  • a n-doped region of the poly silicon region on the STI region is formed using the standard process flow typically used for creating a standard semiconductor device such as a transistor.
  • a p-dpped region of the poly silicon region is formed using the standard process flow. With its n-d ⁇ ped and p-doped regions, the poly silicon region is adapted to be used as a diode.
  • step 320 a dielectric material is deposited above the poly silicon region using the standard process flow.
  • a side wall spacer etch blocking mask from the standard process flow is used to cover the sides of the poly silicon region. Also, using the standard process flow, an oxide block partially covers the top surface of the poly silicon region.
  • a titanium layer is deposited using the standard process flow to cover the poly silicon region, its side oxide block, and its side wall spacer etch blocking mask.
  • step 335 RTA of the standard process flow is performed to the titanium.
  • Portions of the titanium undergo chemical reaction. Specifically, portions of the titanium layer that touch the semiconductor substrate and/or the poly silicon region undergo chemical reaction that causes the formation of silicide.
  • step 340 portions of the titanium layer that do not react with the substrate or the poly silicon region (i.e., the non-silicide portion of the titanium layer) are etched away using the standard process flow. After the etching process, silicide contacts remain on ends of the poly silicon region.
  • step 345 IMO is deposited above the poly silicon region using the standard process flow.
  • step 350 using the standard process flow, contact via etches are formed in the IMO so that, thereafter, silicide contacts of the poly diode are exposed.
  • step 355 contact via etches reaching the poly diode are filled with tungsten plugs using the standard process flow.
  • step 360 IMO and tungsten plugs are planarized using the standard process flow. Typically, the planarization is implemented with CMP.
  • step 365 using the standard process flow, a metallic layer is deposited above IMO and the tungsten plugs. In so doing, electrical conducting paths are formed from the metallic layer to the poly silicon region as a poly diode. At this point, the poly diode can be used as a one time programmable anti-fuse element.
  • step 370 poly diode is "blown" as a : one time programmable anti- fuse element.
  • a forward biased current is driven from the metallic layer through the poly diode to "blow the poly diode as the anti-fuse element.”
  • the damage of the blown anti-fuse in the present embodiment is difficult to detect.
  • the steps implemented do not perturb the existing process flow for a standard semiconductor device (e.g., a transistor).
  • these steps can be implemented concurrently with the fabrication process flow for a standard semiconductor device (e.g., a transistor) such that no perturbation of the process flow is introduced.
  • the existing process flow in forming a standard semiconductor device can also be used in creating a poly diode of the present invention as a one time programmable anti-fuse element.
  • the blown anti-fuse element of the present invention unlike the prior art anti-fuse element made of amorphous silicon, is very difficult to detect.
  • the one time . programmable anti-fuse element of the present invention is well suited for security applications.

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un procédé et un système servant à produire un élément antifusible programmable une seule fois, qui, contrairement aux éléments actuels, ne comporte pas de silicium amorphe. On utilise plutôt un masque de blocage de gravure d'espaceur de parois latérales pour former une polydiode servant d'élément antifusible programmable une seule fois. En particulier, le procédé de production de l'élément antifusible programmable une seule fois comprend des étapes de flux de production standard existants généralement utilisées dans la fabrication d'un dispositif semi-conducteur standard tel qu'un transistor. Ces étapes peuvent être mises en oeuvre simultanément au flux de production d'un dispositif semi-conducteur standard. De manière avantageuse, la production de cette polydiode comme élément antifusible programmable une seule fois ne perturbe pas le flux de production existant. De plus, un courant polarisé dans le sens direct peut être amené par la polydiode afin de la détruire (« griller ») comme élément programmable une seule fois. Comme avantage supplémentaire par rapport à des éléments antifusibles grillés actuels, l'élément antifusible grillé est plus difficile à détecter. De manière avantageuse, l'élément antifusible de l'invention convient bien pour des applications de sécurité.
PCT/US2001/007175 2000-03-13 2001-03-06 Element antifusible programmable une seule fois et procede associe WO2001069658A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001567025A JP2003526941A (ja) 2000-03-13 2001-03-06 一回限りプログラム可能なアンチヒューズ素子およびその製造方法
EP01918392A EP1208597A2 (fr) 2000-03-13 2001-03-06 Element antifusible programmable une seule fois et procede associe

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US52426200A 2000-03-13 2000-03-13
US09/524,262 2000-03-13

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WO2001069658A2 true WO2001069658A2 (fr) 2001-09-20
WO2001069658A3 WO2001069658A3 (fr) 2002-03-14

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JP (1) JP2003526941A (fr)
WO (1) WO2001069658A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2382220A (en) * 2001-11-20 2003-05-21 Zarlink Semiconductor Ltd Polysilicon diode antifuse

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EP0468136A2 (fr) * 1990-04-02 1992-01-29 National Semiconductor Corporation Structures de contact pour dispositifs semi-conducteurs et leur méthode de fabrication
US5242851A (en) * 1991-07-16 1993-09-07 Samsung Semiconductor, Inc. Programmable interconnect device and method of manufacturing same
US5905670A (en) * 1997-05-13 1999-05-18 International Business Machines Corp. ROM storage cell and method of fabrication
US5976943A (en) * 1996-12-27 1999-11-02 Vlsi Technology, Inc. Method for bi-layer programmable resistor

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JPS573292A (en) * 1980-06-10 1982-01-08 Nec Corp Semiconductor storage device
JPH09116108A (ja) * 1995-10-20 1997-05-02 Nissan Motor Co Ltd 半導体記憶装置

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Publication number Priority date Publication date Assignee Title
EP0468136A2 (fr) * 1990-04-02 1992-01-29 National Semiconductor Corporation Structures de contact pour dispositifs semi-conducteurs et leur méthode de fabrication
US5242851A (en) * 1991-07-16 1993-09-07 Samsung Semiconductor, Inc. Programmable interconnect device and method of manufacturing same
US5976943A (en) * 1996-12-27 1999-11-02 Vlsi Technology, Inc. Method for bi-layer programmable resistor
US5905670A (en) * 1997-05-13 1999-05-18 International Business Machines Corp. ROM storage cell and method of fabrication

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PATENT ABSTRACTS OF JAPAN vol. 006, no. 062 (P-111), 21 April 1982 (1982-04-21) -& JP 57 003292 A (NEC CORP), 8 January 1982 (1982-01-08) *
PATENT ABSTRACTS OF JAPAN vol. 1997, no. 09, 30 September 1997 (1997-09-30) -& JP 09 116108 A (NISSAN MOTOR CO LTD), 2 May 1997 (1997-05-02) *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2382220A (en) * 2001-11-20 2003-05-21 Zarlink Semiconductor Ltd Polysilicon diode antifuse
EP1320131A2 (fr) * 2001-11-20 2003-06-18 Zarlink Semiconductor Limited Antifusibles
US6815264B2 (en) 2001-11-20 2004-11-09 Zarlink Semiconductor Limited Antifuses
EP1320131A3 (fr) * 2001-11-20 2004-12-01 Zarlink Semiconductor Limited Antifusibles

Also Published As

Publication number Publication date
JP2003526941A (ja) 2003-09-09
EP1208597A2 (fr) 2002-05-29
WO2001069658A3 (fr) 2002-03-14

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