WO2001065595A2 - A method of forming an opening or cavity in a substrate for receiving an electronic component - Google Patents
A method of forming an opening or cavity in a substrate for receiving an electronic component Download PDFInfo
- Publication number
- WO2001065595A2 WO2001065595A2 PCT/IB2001/000555 IB0100555W WO0165595A2 WO 2001065595 A2 WO2001065595 A2 WO 2001065595A2 IB 0100555 W IB0100555 W IB 0100555W WO 0165595 A2 WO0165595 A2 WO 0165595A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- opening
- cavity
- layer
- electronic component
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000000463 material Substances 0.000 claims abstract description 21
- 238000000608 laser ablation Methods 0.000 claims abstract description 16
- 230000000873 masking effect Effects 0.000 claims abstract 5
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 7
- 238000002679 ablation Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000004698 Polyethylene Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- -1 polyethylene Polymers 0.000 description 2
- 229920000573 polyethylene Polymers 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 229920002799 BoPET Polymers 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 1
- 239000005041 Mylar™ Substances 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004760 aramid Substances 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000002648 laminated material Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000004800 polyvinyl chloride Substances 0.000 description 1
- 229920000915 polyvinyl chloride Polymers 0.000 description 1
- 239000012286 potassium permanganate Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/481—Insulating layers on insulating parts, with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0154—Polyimide
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0397—Tab
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0207—Partly drilling through substrate until a controlled depth, e.g. with end-point detection
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/025—Abrading, e.g. grinding or sand blasting
Definitions
- This invention relates to a method of forming an opening or cavity in a substrate.
- the substrate is preferably of the type which can include an electronic component or integrated circuit.
- An example of such a substrate is a printed circuit board (PCB).
- PCB printed circuit boards
- soldering and wire bonding techniques are expensive and require cumbersome equipment in order to achieve efficiency in the fabrication process. Additionally there may be a requirement to heat the solder twice; firstly on preparation of the PCB and again when mounting components on the PCB
- JP 10098081 discloses using a carbon gas laser to cut a perimeter trench for an opening in a substrate having a copper foil laminated on both sides, the remaining substrate material being removed in a second step.
- the copper foil is then patterned by lithography and etching to form leads to retain a component.
- the present invention arose in order to provide smaller interconnect dimensions on a PCB, thereby rendering it capable of being produced thinner and eliminating the need for synthetic plastics leaded chip carriers (PLCCs).
- the present invention can also be used to manufacture chip carriers with beneficial properties and lower cost.
- Figure 1 shows a diagrammatic view of an embodiment of an apparatus for forming interconnects on a substrate
- Figures 2a and 2b are diagrammatic sectional and plan views of a single component mounted on the substrate produced using the apparatus of Figure 1 ;
- Figures 3a to 3c are plan views showing examples of interconnects; and Figure 4 shows a method of forming a contact through a via hole.
- Figure 1 is an overall view of an apparatus 10 for forming interconnects on a substrate 12.
- the apparatus 10 includes a laser 14, focussed through a suitable lens system 16, which in use, reflects off mirror 18.
- a CO 2 laser having a power of 50 - 500 Watts and a beam diameter of 480 microns is used.
- An Excimer laser or YAG laser can be used as an alternative.
- Means for delivering the substrate such as a flat bed table 24.
- Means for selectively removing regions from a first layer of material may include a photo imager (not shown) and an etch bath (not shown).
- Means for removing volumes of the substrate may be a laser 14 or an ion beam etching device (not shown) or a plasma etcher (not shown).
- Means for removing the material from the second surface may be a modified etch bath capable of etching an electrical conductor.
- Power output of the laser 14 is controlled by micro-processor 20.
- micro-processor 20 orientates mirror 18 and may also be used to focus the laser 14 via the lens system 16.
- a different depth cavity can be formed either by pulsing a larger number of pulses from the energy source or increasing the duration of each pulse.
- an array of cavities can be fabricated, the number and size of cavities in the array can be varied to produce different products or accommodate different devices.
- Substrate 12 shown in greater detail in Figure 2, is in the form of a laminated sheet or tape.
- Two layers 21 a and 21 b of metallic material, such as copper (or aluminium) sandwich a flexible substrate 12 comprises an etchable polymer such as polyethylene (tri-thalmate) (PET).
- PET polyethylene
- the thickness of the substrate is 190 microns, although thicknesses between 100 microns and 600 microns have been employed. Ideally if a silicon chip is to be inserted, it will be ground down from the back to give a similar thickness to that of the substrate. Alternatively, a substrate thickness is chosen according to the thickness of the semiconductor chip.
- a non-metallic base material such as PET substrate 12 is clad with a metal material on at least one of its surfaces by laminating a sheet of the metal material, using an adhesive bonding agent or by catalysing the base material and plating a layer of metal which coats the base material in uniform thickness.
- Substrate 12 may be introduced in a part finished or 'raw' form. If it is raw, the substrate needs to be treated. This is achieved by firstly coating the substrate with a photoresist. This may be applied as a curtain coat by thin uniform spraying, or using other known techniques. Conductor tracks, interconnects and die bonding sites are then photo- imaged on both surfaces. This is a routine step in printed wiring board processing.
- a circuit pattern is formed on the metal clad surface of the substrate.
- the circuit pattern has attachment locations 52 which correspond to bond pad dimensions and locations of a semiconductor component (not shown) to be inserted into the cavity defined on the substrate and connected to interconnects.
- Laser ablation occurs at extremely high rates, typically between 300 to 800 pulses per second.
- Micro-processor 20 varies the rate and duration of pulses from laser 14. This combination permits the vaporisation rate to be controlled and administered for the specific properties of the substrate material. The result is that ablation occurs at a precise X and Y location over a known area to a predetermined depth for a given array of M rows of cavities by N columns of cavities, defined over a specific area.
- the substrate is firstly coated, then photo-imaged. Etching and stripping then occur. Laser ablation of the opening or cavity is then performed.
- the next step is plasma and/or wet chemical cleaning using for example a potassium permanganate solution.
- metal is deposited on the mechanical tab structures such (or contacts) just formed. This is achieved by immersion alloy deposition from solution. This is an electrodeless process, although electroplating could be used as an alternative.
- the metal alloy chosen must be compatible with the application or bonding method chosen. Typical materials include tin, gold or silver based materials.
- material ablated from the cavity can redeposit on other parts of the substrate. Such deposits are usually removed during the plasma and/or wet cleaning step. However, if the material being ablated is polyimide removal can be difficult.
- an optional sacrificial layer can be deposited on the substrate surface or surfaces prior to the laser ablation step. The sacrificial layer can be photoresist for example. After ablation this layer can be easily removed by plasma and/or wet cleaning, and any redeposited material is removed at the same time.
- This contouring step can be achieved by CNC routing, die punching, or YAG laser contouring
- Electrodes are pre-defined by the etching process.
- a series of digitated connectors, spaced one from another and arranged to be in register with contacts of the component or die to be inserted into the cavity or die are formed by a metal etch process before laser ablation of the dielectric.
- the electrodes can be laser etched in the metal layer at the base of the cavity after the dielectric material has been ablated.
- modifications to a pre-etched pattern in this layer can be made with the laser after the cavity has been formed (for example by removing tabs to free the end of an elongate structure).
- the perforated substrate with contacts defined on one surface acts as a shelved recess for receiving electronic components (50).
- the simplest embodiment is an embodiment with one or two contacts, suitable for receiving, for example, capacitors (Figure 3a).
- Transistors require a third contact to be formed and a sketch of such is shown in Figure 3b.
- More complex devices, such as integrated circuits (ICs), Read Only Memory (ROM), Random Access Memory (RAM) or micro-processors require many contacts (51 ).
- An example is shown in Figure 3c.
- the elongate metal bond leads or tabs which form the electrical contacts perform a dual function. Firstly, they act as electrical pathways to/from components. Secondly, they retain components at least during the fabrication process, due to their mechanical properties. For example, devices can be compression mounted, where insertion of the device causes the projecting tabs to fold, creating resilient clip structures which keep the device in place. It has been found that silver coated contact tabs are particularly advantageous in this application.
- each etched region, on each surface is crucial. However, it will be appreciated that a certain degree of tolerance is permitted and die locations may be offset so as to provide for a suitable mechanical recess, capable of receiving and holding electrical components.
- Components can be bonded to the electrodes projecting adjacent the cavity by for example ultrasonic bonding and/or pressure bonding. Alternatively shrink- wrap films can be adapted to urge a component against the electrodes, or an adhesive tape or tab may be used.
- the invention may be used to create an array of cavities.
- An advantage of this arrangement is that a plurality of devices may be produced on a single substrate.
- the substrate may be flexible, and capable of being wound or folded so as to ease transportation by reducing its bulk.
- the substrate may be stored on a spool.
- Components may be introduced into previously formed cavities by any known technique, such as for example a pick-and-place machine, by air jet (vacuum) or by hand.
- An arrangement whereby a reduced air pressure is created at one surface is particularly convenient. The pressure difference draws electronic components into each cavity, so that the component (such as a semiconductor chip or die) may be bonded to the substrate.
- individual chip carriers may be die cut, routed, or sawn from a relatively large sheet or tape of the substrate.
- a particularly advantageous feature of the invention is that it facilitates a flatter chip carrier profile than is normally achievable.
- thickness of a chip carrier is fabricated in accordance with the invention is 17 micron greater than the die thickness.
- the resultant carrier profile is thinner than has been previously achievable.
- Many different types of electrical and electronic components can be placed into the substrate opening or cavity. These include resistors, capacitors, inductors, transistors, integrated circuits, tuners, wave-guides, piezoelectric devices, coils and/or heat-sinks.
- each opening or cavity may be adapted to receive an electro-optical device, such as a liquid crystal device or a light emitting diode. In this latter case conductive tracks may be defined on a surface, using a transparent material such as Indium Tin Oxide (ITO).
- ITO Indium Tin Oxide
- the opening formed by laser ablation has extended all the way through the substrate.
- a blank opening or cavity may be fabricated by stopping the ablation before all the substrate is removed. This technique is useful for making cavities in multilayer PCBs.
- Multilayer PCBs have prepreg dielectric layers, typically 70 microns thick, interleaved with conductive metal layers.
- the laser ablation process can be used to remove such material to expose bond pads in a subsurface metal layer.
- a flip chip die with solder bumps can then be placed on top of the bond pads, so that when the assembly is heated the solder flows and bonds the chip in place.
- An advantage of this technique is that the subsurface layers of the multilayer PCB can be used for signal input and output to the chip, which shortens the signal conductor length and reduces propagation delays.
- an elongate flap or tab of metal (30) is left at the bottom of the via hole (31).
- This flap or tab is longer than the depth of the via hole, and can optionally have an end shaped to form a serrated edge (32) or a barb or spike.
- This flap or tab can be urged into the via by blowing a gas or liquid towards the via, or by pushing using a pin or similar solid tool.
- the part of the flap or tab projecting though the other side of the via hole can then be crimped to a conductive track at the other side of the PCB, forming a through contact without the usual plating steps.
- the serrated edges are shown engaging with a second opening or cavity (33) in the substrate, which can be formed by laser ablation or otherwise. This technique may also be advantageous in conventional PCB manufacture, when openings or cavities for receiving electronic devices are not cut in the substrate.
- the laser ablation occurs through a patterned metal layer carried by the substrate, it is possible to use a separate metal sheet with corresponding holes cut therein as a mask positioned adjacent the substrate as an alternative.
- the laser ablation step exposed elongate contacts which projected into the resulting cavity.
- Such elongate metal members need not be electrical contacts, however - they can form mechanical structures such as for example for pressure switches.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Optics & Photonics (AREA)
- Laser Beam Processing (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
Claims
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/204,154 US6956182B2 (en) | 2000-05-26 | 2001-02-02 | Method of forming an opening or cavity in a substrate for receiving an electronic component |
EP01915623A EP1340414A2 (en) | 2000-02-28 | 2001-02-26 | A method of forming an opening or cavity in a substrate for receiving an electronic component |
JP2001564387A JP2003526205A (en) | 2000-02-28 | 2001-02-26 | Method of making an opening or cavity in a substrate for receiving an electronic component |
AU2001242703A AU2001242703A1 (en) | 2000-02-28 | 2001-02-26 | A method of forming an opening or cavity in a substrate for receiving an electronic component |
US11/070,559 US20050145609A1 (en) | 2001-02-26 | 2005-03-02 | Method of forming an opening or cavity in a substrate for receiving an electronic component |
US11/070,561 US20050155957A1 (en) | 2001-02-26 | 2005-03-02 | Method of forming an opening or cavity in a substrate for receiving an electronic component |
US11/070,560 US20050146025A1 (en) | 2001-02-26 | 2005-03-02 | Method of forming an opening or cavity in a substrate for receiving an electronic component |
US11/070,558 US7288739B2 (en) | 2001-02-26 | 2005-03-02 | Method of forming an opening or cavity in a substrate for receiving an electronic component |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US51425700A | 2000-02-28 | 2000-02-28 | |
US09/514,257 | 2000-02-28 | ||
GBGB0012754.8A GB0012754D0 (en) | 2000-02-28 | 2000-05-26 | Apparatus for forming interconnects on a substrate and related method |
GB0012754.8 | 2000-05-26 |
Related Child Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10204154 A-371-Of-International | 2001-02-02 | ||
US11/070,558 Continuation US7288739B2 (en) | 2001-02-26 | 2005-03-02 | Method of forming an opening or cavity in a substrate for receiving an electronic component |
US11/070,560 Continuation US20050146025A1 (en) | 2001-02-26 | 2005-03-02 | Method of forming an opening or cavity in a substrate for receiving an electronic component |
US11/070,559 Continuation US20050145609A1 (en) | 2001-02-26 | 2005-03-02 | Method of forming an opening or cavity in a substrate for receiving an electronic component |
US11/070,561 Continuation US20050155957A1 (en) | 2001-02-26 | 2005-03-02 | Method of forming an opening or cavity in a substrate for receiving an electronic component |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2001065595A2 true WO2001065595A2 (en) | 2001-09-07 |
WO2001065595A3 WO2001065595A3 (en) | 2002-01-03 |
Family
ID=26244351
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2001/000555 WO2001065595A2 (en) | 2000-02-28 | 2001-02-26 | A method of forming an opening or cavity in a substrate for receiving an electronic component |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1340414A2 (en) |
JP (1) | JP2003526205A (en) |
CN (2) | CN1668167A (en) |
AU (1) | AU2001242703A1 (en) |
WO (1) | WO2001065595A2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10213879C1 (en) * | 2002-03-27 | 2003-07-10 | Infineon Technologies Ag | Electronic component has semiconductor chips fitted into respective recesses in surface of electronic circuit board |
DE10213881C1 (en) * | 2002-03-27 | 2003-10-02 | Infineon Technologies Ag | Memory module has two semiconductor chips stacked on top of one another with underlying chip received in recess in surface of electronic circuit board |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10493559B2 (en) | 2008-07-09 | 2019-12-03 | Fei Company | Method and apparatus for laser machining |
CN102110866B (en) * | 2009-12-24 | 2013-08-28 | 深南电路有限公司 | Manufacturing process of waveguide slot |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3608410A1 (en) * | 1986-03-13 | 1987-09-17 | Siemens Ag | Production of fine structures for semiconductor contacts |
DE4326424A1 (en) * | 1993-08-06 | 1995-02-09 | Ant Nachrichtentech | Process for the production of TAB film supports |
GB2286787A (en) * | 1994-02-26 | 1995-08-30 | Oxford Lasers Ltd | Selective machining by dual wavelength laser |
EP0706309A1 (en) * | 1994-10-06 | 1996-04-10 | International Computers Limited | Printed circuit manufacture |
JPH1098081A (en) * | 1996-09-24 | 1998-04-14 | Hitachi Cable Ltd | Tape carrier for mounting semiconductor chip and manufacturing method thereof |
US5837154A (en) * | 1996-04-23 | 1998-11-17 | Hitachi Cable, Ltd. | Method of manufacturing double-sided circuit tape carrier |
DE19824225A1 (en) * | 1997-07-28 | 1999-02-04 | Matsushita Electric Works Ltd | Method of manufacturing a printed circuit board |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0793485B2 (en) * | 1988-05-16 | 1995-10-09 | カシオ計算機株式会社 | How to connect IC unit |
JP3506002B2 (en) * | 1997-07-28 | 2004-03-15 | 松下電工株式会社 | Manufacturing method of printed wiring board |
-
2001
- 2001-02-26 WO PCT/IB2001/000555 patent/WO2001065595A2/en active Application Filing
- 2001-02-26 JP JP2001564387A patent/JP2003526205A/en active Pending
- 2001-02-26 EP EP01915623A patent/EP1340414A2/en not_active Withdrawn
- 2001-02-26 CN CN 200510055975 patent/CN1668167A/en active Pending
- 2001-02-26 AU AU2001242703A patent/AU2001242703A1/en not_active Abandoned
- 2001-02-26 CN CNB018057071A patent/CN100366132C/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3608410A1 (en) * | 1986-03-13 | 1987-09-17 | Siemens Ag | Production of fine structures for semiconductor contacts |
DE4326424A1 (en) * | 1993-08-06 | 1995-02-09 | Ant Nachrichtentech | Process for the production of TAB film supports |
GB2286787A (en) * | 1994-02-26 | 1995-08-30 | Oxford Lasers Ltd | Selective machining by dual wavelength laser |
EP0706309A1 (en) * | 1994-10-06 | 1996-04-10 | International Computers Limited | Printed circuit manufacture |
US5837154A (en) * | 1996-04-23 | 1998-11-17 | Hitachi Cable, Ltd. | Method of manufacturing double-sided circuit tape carrier |
JPH1098081A (en) * | 1996-09-24 | 1998-04-14 | Hitachi Cable Ltd | Tape carrier for mounting semiconductor chip and manufacturing method thereof |
DE19824225A1 (en) * | 1997-07-28 | 1999-02-04 | Matsushita Electric Works Ltd | Method of manufacturing a printed circuit board |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 09, 31 July 1998 (1998-07-31) & JP 10 098081 A (HITACHI CABLE), 14 April 1998 (1998-04-14) cited in the application * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10213879C1 (en) * | 2002-03-27 | 2003-07-10 | Infineon Technologies Ag | Electronic component has semiconductor chips fitted into respective recesses in surface of electronic circuit board |
DE10213881C1 (en) * | 2002-03-27 | 2003-10-02 | Infineon Technologies Ag | Memory module has two semiconductor chips stacked on top of one another with underlying chip received in recess in surface of electronic circuit board |
Also Published As
Publication number | Publication date |
---|---|
AU2001242703A1 (en) | 2001-09-12 |
JP2003526205A (en) | 2003-09-02 |
CN1406452A (en) | 2003-03-26 |
CN1668167A (en) | 2005-09-14 |
CN100366132C (en) | 2008-01-30 |
WO2001065595A3 (en) | 2002-01-03 |
EP1340414A2 (en) | 2003-09-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4965702A (en) | Chip carrier package and method of manufacture | |
JP3771867B2 (en) | Structure having coplanar circuit features and method of making the same | |
US7297562B1 (en) | Circuit-on-foil process for manufacturing a laminated semiconductor package substrate having embedded conductive patterns | |
US5369881A (en) | Method of forming circuit wiring pattern | |
US6956182B2 (en) | Method of forming an opening or cavity in a substrate for receiving an electronic component | |
US5774340A (en) | Planar redistribution structure and printed wiring device | |
US7288739B2 (en) | Method of forming an opening or cavity in a substrate for receiving an electronic component | |
KR101336485B1 (en) | Through hole forming method and printed circuit board manufacturing method | |
JPH08125342A (en) | Flexible multilayered wiring board and its manufacture | |
EP1340414A2 (en) | A method of forming an opening or cavity in a substrate for receiving an electronic component | |
JP2004031710A (en) | Method for manufacturing wiring board | |
EP1517599A1 (en) | A method of interconnecting opposite sides of an electronic component interconnection device | |
JP2003198133A (en) | Method for manufacturing flexible build-up printed wiring board | |
JPH05343856A (en) | Multilayer printed wiring board and manufacture thereof | |
JP3062142B2 (en) | Method for manufacturing multilayer printed wiring board | |
JPH10335759A (en) | Flexible printed wiring board | |
JPH05211386A (en) | Printed wiring board and manufacture thereof | |
JP2003142823A (en) | Manufacturing method for both-sided flexible circuit board | |
JP2685443B2 (en) | Processing method of printed circuit board | |
JPH05277774A (en) | Method for partially removing insulator layer of insulating substrate with conductor layer | |
JPH06318772A (en) | Circuit substrate and manufacturing method thereof | |
JPS6190496A (en) | Manufacture of multilayer interconnection substrate | |
JPH0645760A (en) | Multilayer board and manufacture thereof | |
JPH04314382A (en) | Manufacture of wiring board | |
JP2005089820A (en) | Etching method, and method for manufacturing circuit device by using it |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
AK | Designated states |
Kind code of ref document: A3 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1020027011171 Country of ref document: KR |
|
ENP | Entry into the national phase in: |
Ref country code: JP Ref document number: 2001 564387 Kind code of ref document: A Format of ref document f/p: F |
|
WWE | Wipo information: entry into national phase |
Ref document number: 018057071 Country of ref document: CN |
|
WWP | Wipo information: published in national office |
Ref document number: 1020027011171 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2001915623 Country of ref document: EP |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10204154 Country of ref document: US |
|
WWP | Wipo information: published in national office |
Ref document number: 2001915623 Country of ref document: EP |