WO2001047173A3 - A multi-rate transponder system and chip set - Google Patents

A multi-rate transponder system and chip set Download PDF

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Publication number
WO2001047173A3
WO2001047173A3 PCT/DK2000/000723 DK0000723W WO0147173A3 WO 2001047173 A3 WO2001047173 A3 WO 2001047173A3 DK 0000723 W DK0000723 W DK 0000723W WO 0147173 A3 WO0147173 A3 WO 0147173A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
circuit
outgoing
clock
bit rate
Prior art date
Application number
PCT/DK2000/000723
Other languages
French (fr)
Other versions
WO2001047173A2 (en
Inventor
Henrik Ingvar Johansen
Original Assignee
Giga Aps
Henrik Ingvar Johansen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Giga Aps, Henrik Ingvar Johansen filed Critical Giga Aps
Priority to AU21522/01A priority Critical patent/AU2152201A/en
Priority to EP00984926A priority patent/EP1243087B1/en
Priority to CA002395538A priority patent/CA2395538C/en
Priority to DE60029826T priority patent/DE60029826T2/en
Publication of WO2001047173A2 publication Critical patent/WO2001047173A2/en
Publication of WO2001047173A3 publication Critical patent/WO2001047173A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Static Random-Access Memory (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

A multi-rate transponder system and circuit for receiving an incoming serial data stream and transmitting an outgoing serial data stream are disclosed. The system comprises a receiving part comprising a Clock and Data Recovery circuit, a data transfer circuit, a clock transfer circuit and a reference clock circuit, and a system controller comprising system data receiving means, system data transfer means, system data processing means and a slide-buffer, and a transmitting part comprising a transmitter Phase Locked Loop adapted to generate an output clock signal, a transmitter clock circuit, and a data reception circuit adapted to receive the outgoing data signal from the system data transfer means and to generate the serial outgoing data stream at the nominal bit rate or at the corresponding transport network bit rate independently of the bit rate of the incoming serial data stream, based on the outgoing data signal and the output clock signal.
PCT/DK2000/000723 1999-12-21 2000-12-21 A multi-rate transponder system and chip set WO2001047173A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU21522/01A AU2152201A (en) 1999-12-21 2000-12-21 A multi-rate transponder system and chip set
EP00984926A EP1243087B1 (en) 1999-12-21 2000-12-21 A multi-rate transponder system and chip set
CA002395538A CA2395538C (en) 1999-12-21 2000-12-21 A multi-rate transponder system and chip set
DE60029826T DE60029826T2 (en) 1999-12-21 2000-12-21 MULTI-TRANSPORT SYSTEM AND CHIPSET

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/468,606 US6631144B1 (en) 1999-12-21 1999-12-21 Multi-rate transponder system and chip set
US09/468,606 1999-12-21

Publications (2)

Publication Number Publication Date
WO2001047173A2 WO2001047173A2 (en) 2001-06-28
WO2001047173A3 true WO2001047173A3 (en) 2001-11-15

Family

ID=23860489

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DK2000/000723 WO2001047173A2 (en) 1999-12-21 2000-12-21 A multi-rate transponder system and chip set

Country Status (8)

Country Link
US (1) US6631144B1 (en)
EP (1) EP1243087B1 (en)
CN (1) CN1227833C (en)
AT (1) ATE335318T1 (en)
AU (1) AU2152201A (en)
CA (1) CA2395538C (en)
DE (1) DE60029826T2 (en)
WO (1) WO2001047173A2 (en)

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US7050463B1 (en) * 2000-10-31 2006-05-23 Texas Instruments Incorporated Automatic bit-rate detection scheme for use on SONET transceiver
JP4426739B2 (en) * 2001-06-26 2010-03-03 日本オプネクスト株式会社 Optical module and manufacturing method thereof
US7142623B2 (en) * 2002-05-31 2006-11-28 International Business Machines Corporation On-chip system and method for measuring jitter tolerance of a clock and data recovery circuit
US8155236B1 (en) 2002-06-21 2012-04-10 Netlogic Microsystems, Inc. Methods and apparatus for clock and data recovery using transmission lines
US7664401B2 (en) 2002-06-25 2010-02-16 Finisar Corporation Apparatus, system and methods for modifying operating characteristics of optoelectronic devices
US7437079B1 (en) * 2002-06-25 2008-10-14 Finisar Corporation Automatic selection of data rate for optoelectronic devices
US7561855B2 (en) 2002-06-25 2009-07-14 Finisar Corporation Transceiver module and integrated circuit with clock and data recovery clock diplexing
US7486894B2 (en) 2002-06-25 2009-02-03 Finisar Corporation Transceiver module and integrated circuit with dual eye openers
US7809275B2 (en) 2002-06-25 2010-10-05 Finisar Corporation XFP transceiver with 8.5G CDR bypass
US7477847B2 (en) 2002-09-13 2009-01-13 Finisar Corporation Optical and electrical channel feedback in optical transceiver module
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US7352835B1 (en) * 2003-09-22 2008-04-01 Altera Corporation Clock data recovery circuitry with dynamic support for changing data rates and a dynamically adjustable PPM detector
US7480358B2 (en) * 2004-02-25 2009-01-20 Infineon Technologies Ag CDR-based clock synthesis
US7397825B2 (en) * 2004-03-10 2008-07-08 Scientific-Atlanta, Inc. Transport stream dejitterer
KR100603616B1 (en) * 2004-12-16 2006-07-24 한국전자통신연구원 Apparatus for clock synchronization using source synchronous clock in optical transmission system
KR100687723B1 (en) * 2004-12-17 2007-02-27 한국전자통신연구원 Apparatus for testing the performance of optical transceiver
US7532697B1 (en) * 2005-01-27 2009-05-12 Net Logic Microsystems, Inc. Methods and apparatus for clock and data recovery using a single source
US20060215296A1 (en) * 2005-03-24 2006-09-28 Gennum Corporation Bidirectional referenceless communication circuit
CN100407699C (en) * 2005-04-01 2008-07-30 华为技术有限公司 Signal disconnection and combination method and apparatus
US7304498B2 (en) * 2005-07-20 2007-12-04 Altera Corporation Clock circuitry for programmable logic devices
US7432750B1 (en) * 2005-12-07 2008-10-07 Netlogic Microsystems, Inc. Methods and apparatus for frequency synthesis with feedback interpolation
US7738448B2 (en) * 2005-12-29 2010-06-15 Telefonaktiebolaget Lm Ericsson (Publ) Method for generating and sending signaling messages
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US20070253474A1 (en) * 2006-04-27 2007-11-01 Finisar Corporation Generating eye-diagrams and network protocol analysis of a data signal
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US7881608B2 (en) * 2007-05-10 2011-02-01 Avago Technologies Fiber Ip (Singapore) Pte. Ltd Methods and apparatuses for measuring jitter in a transceiver module
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Also Published As

Publication number Publication date
DE60029826D1 (en) 2006-09-14
CN1227833C (en) 2005-11-16
WO2001047173A2 (en) 2001-06-28
AU2152201A (en) 2001-07-03
EP1243087B1 (en) 2006-08-02
US6631144B1 (en) 2003-10-07
CA2395538A1 (en) 2001-06-28
ATE335318T1 (en) 2006-08-15
EP1243087A2 (en) 2002-09-25
CA2395538C (en) 2007-09-18
CN1435016A (en) 2003-08-06
DE60029826T2 (en) 2007-03-01

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