WO2001047014A1 - Organic flip chip packages with an array of through hole pins - Google Patents
Organic flip chip packages with an array of through hole pins Download PDFInfo
- Publication number
- WO2001047014A1 WO2001047014A1 PCT/US2000/016788 US0016788W WO0147014A1 WO 2001047014 A1 WO2001047014 A1 WO 2001047014A1 US 0016788 W US0016788 W US 0016788W WO 0147014 A1 WO0147014 A1 WO 0147014A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- carrier member
- organic substrate
- solder
- solder alloy
- pins
- Prior art date
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 92
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 46
- 239000000956 alloy Substances 0.000 claims abstract description 46
- 239000004593 Epoxy Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 63
- 238000000034 method Methods 0.000 claims description 18
- 229910052718 tin Inorganic materials 0.000 claims description 13
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 12
- 229910052787 antimony Inorganic materials 0.000 claims description 9
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 9
- 229910052709 silver Inorganic materials 0.000 claims description 9
- 239000004332 silver Substances 0.000 claims description 9
- 238000005304 joining Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000004891 communication Methods 0.000 claims description 7
- 229910052738 indium Inorganic materials 0.000 claims description 7
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 2
- 239000002991 molded plastic Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 230000008901 benefit Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000001465 metallisation Methods 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000003365 glass fiber Substances 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000178 monomer Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229920002647 polyamide Polymers 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000005979 thermal decomposition reaction Methods 0.000 description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 229910003271 Ni-Fe Inorganic materials 0.000 description 1
- 229920000265 Polyparaphenylene Polymers 0.000 description 1
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 150000001408 amides Chemical class 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229920001577 copolymer Polymers 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- 150000002148 esters Chemical class 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 150000003949 imides Chemical group 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920003217 poly(methylsilsesquioxane) Polymers 0.000 description 1
- 229920002492 poly(sulfone) Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 235000013824 polyphenols Nutrition 0.000 description 1
- -1 polyphenylene Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 125000001174 sulfone group Chemical group 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3447—Lead-in-hole components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09754—Connector integrally incorporated in the printed circuit board [PCB] or in housing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10295—Metallic connector elements partly mounted in a hole of the PCB
- H05K2201/10303—Pin-in-hole mounted pins
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
Definitions
- the present invention relates an organic member for mounting a semiconductor device, and more particularly to an organic carrier member having an array of through hole pins embedded in the organic carrier member.
- Integrated circuit (IC) devices whether individual active devices, individual passive devices, multiple active devices within a single chip, or multiple passive and active devices within a single chip, require suitable input output (I/O) connections between themselves and other circuit elements or structures. These devices are typically very small and fragile. Because of their size and fragility, they are commonly carried on substrates for support, i.e., carrier members.
- Area array chip interconnects use bumps or solder joints that directly couples the IC chip or die to the carrier member. This technique accommodates an increased number of I/O terminals and provides electrical signals immediately below the chip, improving voltage noise margins and signal speed.
- area array interconnect packaging technique is the flip chip (FC) solder interconnect on a carrier member.
- the IC die and other devices are "bumped" with solder bumps or balls, i.e. a plurality of discrete solder bumps are formed over metal contacts on the surface of the die.
- the chip is then turned upside down or “flipped” so that the device side or face of the IC die couples to the carrier member such as found in a plastic carrier member having balls, pins or land grid arrays.
- the solder bumps of the device are then attached to the carrier member forming an electrical and mechanical connection.
- a through-hole organic carrier member conventionally employs a multi-layer substrate constructed of a plurality laminated dielectric and conductive layers where individual IC chips are mounted to the top layer of the substrate.
- the conductive layers are made of a pre-defined metallization pattern sandwiched between dielectric layers within the substrate.
- Metallization patterns on certain layers act as voltage reference planes and also provide power to the individual chips.
- Metallization patterns on other layers route signals between individual chips. Electrical connections to individual terminals of each chip and/or between separate layers are made through well-known vertical interconnects called "vias".
- Input output (I/O) pins are embedded within the substrate and electrically connected to appropriate metalliation patterns existing within the substrate thereby routing electrical signals between a multi-chip integrated circuit package and external devices. As illustrated in Fig.
- a conventional flip chip assembly 8 includes a device or die 10 mechanically and electrically attached to substrate 16 by a plurality of solder bumps 12 connected to solder pads 14 on substrate 16. Solder pads 14 are electrically connected to an array of pin leads 18 by internal metallized layers (not shown for illustrative convenience) throughout substrate 16. Pin leads 18 are used to provide electrical connections to external circuitry. The assembly, thus, provides an electrical signal path from die 10 through solder/pad connections 12/14 through substrate 16 by way of internal metallization pattern to an external connection by way of I/O pin leads 18.
- substrate 16 has a plurality of solder pads 14, which are generally formed by screen printing a coating of solder on the substrate.
- Solder balls 12 on die 10 are generally formed by known solder bumping techniques and are conventionally formed of a high lead solder, such as solders containing 97-95 weight percent (wt%) lead / 3-5 wt% tin having a melting temperature of approximately 323 °C.
- a known technique for bonding a pin lead to an organic substrate involves inserting a pin in a preformed through hole in the multilayered substrate.
- the inserted pin is coated with a 10 wt% lead /10 wt% tin solder and heating the substrate causes the solder on the pin to reflow forming a bond between the pin and the internal metallized layer of the multilayered substrate.
- One problem associated with attaching pin leads to the internal metallized layer in an organic substrate is that the soldering temperature cannot be higher than the decomposition temperature of the polymeric material used to fabricated to the multilayered substrate, without adversely compromising the mechanical integrity of the substrate.
- solders employed for joining pin leads to the metallized layer should form strong mechanical bonds capable of withstanding pulling, placement, or testing of the assembly, i.e. socketing, with good electrical signal.
- An advantage of the present invention is an organic carrier member suitable for mounting a device with highly reliable pin leads.
- Another advantage of the present invention is a device assembly that maintains reliable electrical connections during its operation.
- the carrier member of the present invention comprises: an organic substrate having an internal conductive layer; a plurality of conductive contacts on the organic substrate for receiving a device to be mounted thereto in electrical communication with the internal conductive layer; a plurality of pins which extend away from the organic substrate with each pin having its top end portion embedded into the organic substrate and each top end portion joined to the internal conductive layer by a solder alloy having a reflow temperature of no greater than about 300 °C, e.g. the solder alloy has a reflow temperature of about 220 °C to about 270 °C.
- the conductive contacts comprise solder pads and the solder alloy bonding the top end portion of the pins has a reflow temperature higher than the reflow temperature of the solder pads, i.e., the temperature difference between reflowing the solder pads and the solder alloy joining the pins and the solder pads is no less than approximately 10 °C.
- Solder alloys of the present invention comprise about 85 wt% to about 82 wt% lead, about 12 wt% to about 8 wt% antimony, about 10 wt% to about 3 wt% tin and up to about 5 wt% silver. Additional solder alloys of the present invention comprise about 95 wt% to about 80 wt% tin, about 15 wt% to about 3 wt% antimony, up to about 50 wt% indium and up to about 5 wt% silver. Other solder alloys of the present invention comprise about 80 wt% to about 50 wt% lead and about 50 wt% to about 20 wt% indium.
- the organic substrate can comprise polyphenylene sulphide, polysulphone, polyethersulphone, polyarysulphone, phenol, polyamide, bismaleimide-triazine, epoxy or mixtures thereof with optionally fiberous materials, such as glass fibers, to fabricate a laminated structure with internal wiring connecting the solder pads with the leads at the bottom of the organic substrate.
- the organic substrate can be fabricated by any of the above resins, or mixtures thereof in to a non-laminated structure, such as a molded plastic part with internal wiring.
- Another aspect of the present invention is a device assembly comprising a device and a supporting organic carrier member having an array of pin leads embedded therein.
- the assembly comprises: a device having a plurality solderable contacts thereon, wherein the solderable contacts of the device are joined to the conductive contacts on the carrier member of the present invention.
- the device can be an integrated circuit die having a plurality solder bumps, such as a bumped IC die or bumped capacitor and mounted to the supporting carrier member.
- Another aspect of the present invention is a method of manufacturing a device assembly.
- the method comprises: providing carrier member for mounting a device, wherein the carrier member comprising: an organic substrate having an internal conductive layer; a plurality of solder pads on the organic substrate for receiving a device to be mounted thereto in electrical communication with the internal conductive layer; a plurality of pins which extend away from the organic substrate with each pin having its top end portion embedded into the organic substrate and each top end portion electrically bonded to the internal conductive layer by a solder alloy having a reflow temperature of no greater than about 300 °C; mounting a device having a plurality of solderable contacts thereon on to the carrier member such that the solderable contacts of the device are aligned with the solder pads on the organic substrate; and reflowing the solder pads on the organic substrate at a temperature no greater than the reflow temperature of the solder alloy bonding the pins to form an electrical connection between the solderable contacts of the device and the solder pads on the organic substrate.
- the embedded pins are joined to the internal conductive layer by reflowing a solder alloy therebetween at a temperature no less than about 205 °C to provide a mechanical and electrical joint between the internal conductive layer and the pins prior to providing the carrier member.
- the solder alloy comprises about 85 wt% to about 82 wt% lead, about 12 wt% to about 8 wt% antimony, about 10 wt% to about 3 wt% tin and up to about 5 wt% silver.
- Fig. 1 schematically depicts a conventional flip chip assembly.
- Fig. 2A-2B schematically illustrate a cross-sectional view of a pin lead joined to an internal conductive layer and embedded in an organic substrate of the present invention.
- the present invention stems from the discovery that employing solder alloys with a high melting or reflow temperature to join an internal conductive layer to an embedded pin lead improves the mechanical integrity of the embedded pin and prevents the joint from separating during subsequent thermal processing steps in manufacturing a device assembly.
- solder alloys with a high melting or reflow temperature to join an internal conductive layer to an embedded pin lead improves the mechanical integrity of the embedded pin and prevents the joint from separating during subsequent thermal processing steps in manufacturing a device assembly.
- conventional low temperature solder alloys employed in joining pin leads within organic carrier members melt internally during the die attach process causing volume expansion straining and ultimately breaking the formed joint.
- the present invention overcomes the undesirable reflow of internal solder alloys by using a high temperature solder alloy to form the joint between an internal conductive layer and embedded pin in an organic carrier member.
- the solder alloys of the present invention have a reflow temperature that is below the decomposition transition temperature of the organic carrier, yet higher than the reflow temperature of subsequent thermal processes and still forms a strong mechanical and electrical bond capable of undergoing many temperature cycles without discontinuity over the life-time operation of the device.
- Figs. 2A and 2B illustrate an organic carrier member of the present invention.
- carrier member 20 comprises an organic substrate 22 having an internal conductive layer 24.
- An array of conductive contacts 26, e.g. solder pads, are formed on organic substrate 22 for receiving a device (not shown).
- the array of solder pads 26 are patterned to correspond to the metallization pattern of a give device to be mounted thereon.
- the organic carrier member further comprises a plurality of pin leads 28. As shown in Fig. 2B, the pin lead extends from the organic substrate 22 with each pin having its top end portion 30 embedded into the organic substrate and each top end portion 30 electrically and mechanically joined to internal conductive layer 24 by a solder alloy 32.
- the pins can be configured in any desired footprint. Additionally, the organic carrier member can also contain plated through-hole thermal vias and/or a metal slug to dissipate the heat generated by an attached device.
- the internal conductive layers can be made by vapor deposing metal layers on dielectric layers used to fabricate a laminated structure. Metals useful in forming the conductive layers include aluminum, nickel, iron, copper, gold or alloys thereof at a thickness of about 5 microns to about 40 microns.
- the pin leads can be made of alloys or layers of cobalt, nickel, iron and plated with one or more layers of nickel or gold. Given the guidance and objectives of the present disclosure, the optimum solder compositions and organic substrate can be necessarily determined for a particular device assembly.
- formulated solder alloys have a high reflow temperature, i.e. the temperature which the solder is mobile enough to form an electrical connection.
- the formulated solders have a reflow temperature of about 220 °C to about 270 °C.
- Solder alloys of the present invention comprise about 85 wt% to about 82 wt% lead, about 12 wt% to about 8 wt% antimony, about 10 wt% to about 3 wt% tin and up to about 5 wt% silver.
- solder alloys useful in the present invention comprise about 95 wt% to about 80 wt% tin, about 15 wt% to about 3 wt% antimony, up to about 20 wt% indium and up to about 5 wt% silver. Still other solder alloys useful in the present invention comprise about 80 wt% to about 50 wt% lead and up to about 50 wt% indium.
- Table 1 below provides solder alloys together with their melting characteristics that are suitable for joining pin leads to internal conductive layers within organic substrates in accordance with the present invention. Table 1.
- the solder alloys of the present invention further advantageously have a reflow temperature which does not compromise the integrity of the organic substrate.
- the organic substrate comprises a high temperature stable polymeric material, such as sulphone, polyarysulphone, phenol, polyamide, bismaleimide-triazine, epoxy or mixtures thereof.
- Polyimides are radiation resistant high temperature stable materials that can be prepared as laminates for organic packages. For example, polyimide itself has a thermal decomposition temperature of over 300 °C.
- Polyimides can further be copolymerized with one or more imide substituted monomers to enhance dielectric and/or thermal properties.
- Typical monomers that can be copolymerized with polyimides include amides, phenolics, bismaleimide, epoxys and esters to form the corresponding polimide copolymers.
- the organic substrate of the present invention can be fabricated in the form of a molded part or as a laminated structure.
- a laminated structure with internal conductive layers with embedded pin leads at can be fabricated having one or more conductive layers and insulating polymer layers with optionally fiberous materials, such as glass fibers.
- the organic substrate can be fabricated from an organic epoxy-glass resin based material, such as bismaleimide-triazine (BT) resin or FR-4 board laminate having a high thermal decomposition temperature.
- the organic substrate comprises a bismaleimide-triazine epoxy laminate structure having an internal metal layer, such as a layer of copper.
- solder pads On the surface of the substrate are a plurality of solder pads arranged in a pattern to receive a semiconductor device.
- the pin leads are in electrical communication with the internal metal layer.
- a plurality of Co-Ni-Fe pin leads coated with nickel and/or gold are embedded in the laminate with each top end portion electrically and mechanically joined to the internal metal layer by a solder alloy having a reflow temperature of no greater than about 300 °C.
- the pin leads are joined to the internal conductive layer by inserting a pre-coated pin leads into a pre-formed through hole in the organic carrier member.
- the pin lead is joined to the internal conductive layer by reflowing the solder alloys of the present invention at a temperature no less than about 210 °C to form a mechanically and electrically strong bond therebetween.
- a device assembly is prepared by providing a carrier member of the present invention and mounting a device having a plurality of solderable contacts thereon on to the carrier member such that the solderable contacts of the device are aligned with the solder pads on the member.
- the device can be any device having a solderable conductive contact thereon.
- the device can be a high lead solder bumped IC, e.g. 97-95 wt% Pb/3-5 wt% Sn, having under bump metallurgy, i.e. comprising one or more layers or an alloy of chrome, copper, gold, titanium, nickel, etc. between the high lead solder bump and the IC, or a bumped capacitor, or any other device having a solderable conductive contact.
- an electrical interconnection is formed between the device and the member by the application of heat, such as by infrared radiation, a flow of dry heated gas, such as in a belt furnace, etc. to reflow the solder pads on the member and interconnect the device and carrier member.
- the solder pads on the carrier member are reflowed by a process of heating the organic carrier member from about 240 °C to about 260 °C, e.g. heating the carrier member to about 250 °C, by a process of a combined infrared/convection heater.
- the temperature difference between reflowing the solder pads and the solder alloy joining the pins is no less than approximately 10 °C, e.g. no less than about 5 °C.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001547650A JP2003518744A (en) | 1999-12-21 | 2000-06-15 | Organic flip-chip package with an array of through-hole pins |
EP00942924A EP1249041A1 (en) | 1999-12-21 | 2000-06-15 | Organic flip chip packages with an array of through hole pins |
KR1020027008124A KR20020065602A (en) | 1999-12-21 | 2000-06-15 | Organic flip chip packages with an array of through hole pins |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17129799P | 1999-12-21 | 1999-12-21 | |
US60/171,297 | 1999-12-21 | ||
US48210100A | 2000-01-13 | 2000-01-13 | |
US09/482,101 | 2000-01-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001047014A1 true WO2001047014A1 (en) | 2001-06-28 |
Family
ID=26866929
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/016788 WO2001047014A1 (en) | 1999-12-21 | 2000-06-15 | Organic flip chip packages with an array of through hole pins |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1249041A1 (en) |
JP (1) | JP2003518744A (en) |
KR (1) | KR20020065602A (en) |
WO (1) | WO2001047014A1 (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4170472A (en) * | 1977-04-19 | 1979-10-09 | Motorola, Inc. | Solder system |
US5303862A (en) * | 1992-12-31 | 1994-04-19 | International Business Machines Corporation | Single step electrical/mechanical connection process for connecting I/O pins and creating multilayer structures |
US5479319A (en) * | 1992-12-30 | 1995-12-26 | Interconnect Systems, Inc. | Multi-level assemblies for interconnecting integrated circuits |
US5938862A (en) * | 1998-04-03 | 1999-08-17 | Delco Electronics Corporation | Fatigue-resistant lead-free alloy |
-
2000
- 2000-06-15 JP JP2001547650A patent/JP2003518744A/en not_active Withdrawn
- 2000-06-15 EP EP00942924A patent/EP1249041A1/en not_active Withdrawn
- 2000-06-15 WO PCT/US2000/016788 patent/WO2001047014A1/en active Application Filing
- 2000-06-15 KR KR1020027008124A patent/KR20020065602A/en not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4170472A (en) * | 1977-04-19 | 1979-10-09 | Motorola, Inc. | Solder system |
US5479319A (en) * | 1992-12-30 | 1995-12-26 | Interconnect Systems, Inc. | Multi-level assemblies for interconnecting integrated circuits |
US5303862A (en) * | 1992-12-31 | 1994-04-19 | International Business Machines Corporation | Single step electrical/mechanical connection process for connecting I/O pins and creating multilayer structures |
US5938862A (en) * | 1998-04-03 | 1999-08-17 | Delco Electronics Corporation | Fatigue-resistant lead-free alloy |
Also Published As
Publication number | Publication date |
---|---|
JP2003518744A (en) | 2003-06-10 |
EP1249041A1 (en) | 2002-10-16 |
KR20020065602A (en) | 2002-08-13 |
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