WO2001041544A3 - Deposition of gate stacks including silicon germanium layers - Google Patents

Deposition of gate stacks including silicon germanium layers Download PDF

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Publication number
WO2001041544A3
WO2001041544A3 PCT/US2000/031676 US0031676W WO0141544A3 WO 2001041544 A3 WO2001041544 A3 WO 2001041544A3 US 0031676 W US0031676 W US 0031676W WO 0141544 A3 WO0141544 A3 WO 0141544A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
germanium
silicon germanium
polysilicon
silicon
Prior art date
Application number
PCT/US2000/031676
Other languages
French (fr)
Other versions
WO2001041544B1 (en
WO2001041544A2 (en
Inventor
Majiid M Mansoori
Original Assignee
Asm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asm Inc filed Critical Asm Inc
Publication of WO2001041544A2 publication Critical patent/WO2001041544A2/en
Publication of WO2001041544A3 publication Critical patent/WO2001041544A3/en
Publication of WO2001041544B1 publication Critical patent/WO2001041544B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/2807—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being Si or Ge or C and their alloys except Si

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Methods and structures are provided for forming silicon germanium gate electrodes over gate dielectrics. A thin polysilicon wetting layer (115) provides continuous coverage of the silicon dioxide layer (110) and reduces incubation time for the silicon germanium (120) thereupon. The continuity of the wetting layer (115) leads to a uniformly thick, planar gate electrode structure. At the same time, the polysilicon layer (115) can be made thin enough to minimize thermal requirements for segregating germanium to the electrode-oxide interface, and providing grain boundary diffusion to further facilitate germanium diffusion. Advantageously, the polysilicon wetting layer (115), silicon germanium (120) and a further silicon cap layer (125) are all formed in situ under atmospheric pressures.
PCT/US2000/031676 1999-12-11 2000-11-17 Deposition of gate stacks including silicon germanium layers WO2001041544A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US46019099A 1999-12-11 1999-12-11
US09/460,190 1999-12-11

Publications (3)

Publication Number Publication Date
WO2001041544A2 WO2001041544A2 (en) 2001-06-14
WO2001041544A3 true WO2001041544A3 (en) 2001-11-22
WO2001041544B1 WO2001041544B1 (en) 2002-01-31

Family

ID=23827714

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/031676 WO2001041544A2 (en) 1999-12-11 2000-11-17 Deposition of gate stacks including silicon germanium layers

Country Status (2)

Country Link
TW (1) TW477075B (en)
WO (1) WO2001041544A2 (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7540920B2 (en) 2002-10-18 2009-06-02 Applied Materials, Inc. Silicon-containing layer deposition with silicon compounds
WO2004036636A1 (en) * 2002-10-18 2004-04-29 Applied Materials, Inc. A film stack having a silicon germanium layer and a thin amorphous seed layer
US7682947B2 (en) 2003-03-13 2010-03-23 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
US7238595B2 (en) 2003-03-13 2007-07-03 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
US6905976B2 (en) * 2003-05-06 2005-06-14 International Business Machines Corporation Structure and method of forming a notched gate field effect transistor
US7468311B2 (en) 2003-09-30 2008-12-23 Tokyo Electron Limited Deposition of silicon-containing films from hexachlorodisilane
US8501594B2 (en) 2003-10-10 2013-08-06 Applied Materials, Inc. Methods for forming silicon germanium layers
US7132338B2 (en) 2003-10-10 2006-11-07 Applied Materials, Inc. Methods to fabricate MOSFET devices using selective deposition process
US7166528B2 (en) 2003-10-10 2007-01-23 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
US7078302B2 (en) 2004-02-23 2006-07-18 Applied Materials, Inc. Gate electrode dopant activation method for semiconductor manufacturing including a laser anneal
EP1763893A2 (en) 2004-02-27 2007-03-21 ASM America, Inc. Germanium deposition
US7205187B2 (en) 2005-01-18 2007-04-17 Tokyo Electron Limited Micro-feature fill process and apparatus using hexachlorodisilane or other chlorine-containing silicon precursor
US7569873B2 (en) 2005-10-28 2009-08-04 Dsm Solutions, Inc. Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys
US7674337B2 (en) 2006-04-07 2010-03-09 Applied Materials, Inc. Gas manifolds for use during epitaxial film formation
US7648853B2 (en) 2006-07-11 2010-01-19 Asm America, Inc. Dual channel heterostructure
US9127345B2 (en) 2012-03-06 2015-09-08 Asm America, Inc. Methods for depositing an epitaxial silicon germanium layer having a germanium to silicon ratio greater than 1:1 using silylgermane and a diluent
US9171715B2 (en) 2012-09-05 2015-10-27 Asm Ip Holding B.V. Atomic layer deposition of GeO2
US9218963B2 (en) 2013-12-19 2015-12-22 Asm Ip Holding B.V. Cyclical deposition of germanium
KR102629160B1 (en) 2018-01-29 2024-01-29 어플라이드 머티어리얼스, 인코포레이티드 Wetting layers for optical device enhancement

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0614226A1 (en) * 1992-10-05 1994-09-07 Texas Instruments Incorporated Gate electrode using stacked layers of TiN and polysilicon
EP0887843A1 (en) * 1997-06-25 1998-12-30 France Telecom Method of manufacturing a transistor with a silicon-germanium gate
EP0889504A1 (en) * 1997-06-30 1999-01-07 STMicroelectronics S.A. Method of manufacturing MOS transistor gates with a high germanium content
FR2775119A1 (en) * 1998-02-19 1999-08-20 France Telecom Interdiffusion barrier layer is formed for a silicon and silicon-germanium composite gate e.g. of a CMOS device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0614226A1 (en) * 1992-10-05 1994-09-07 Texas Instruments Incorporated Gate electrode using stacked layers of TiN and polysilicon
EP0887843A1 (en) * 1997-06-25 1998-12-30 France Telecom Method of manufacturing a transistor with a silicon-germanium gate
EP0889504A1 (en) * 1997-06-30 1999-01-07 STMicroelectronics S.A. Method of manufacturing MOS transistor gates with a high germanium content
FR2775119A1 (en) * 1998-02-19 1999-08-20 France Telecom Interdiffusion barrier layer is formed for a silicon and silicon-germanium composite gate e.g. of a CMOS device

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
BENSAHEL D ET AL: "SINGLE-WAFER PROCESSING OF IN SITU-DOPED POLYCRYSTALLINE SI AND SI1-XGEX", SOLID STATE TECHNOLOGY,US,COWAN PUBL.CORP. WASHINGTON, vol. 41, no. 3, 1 March 1998 (1998-03-01), pages S05 - S06,S08,S10, XP000735101, ISSN: 0038-111X *
BODNAR S ET AL: "Single-wafer Si and SiGe processes for advanced ULSI technologies", THIN SOLID FILMS,ELSEVIER-SEQUOIA S.A. LAUSANNE,CH, vol. 294, no. 1-2, 15 February 1997 (1997-02-15), pages 11 - 14, XP004073026, ISSN: 0040-6090 *
HELLBERG P -E ET AL: "WORK FUNCTION OF BORON-DOPED POLYCRYSTALLINE SIXGE1-X FILMS", IEEE ELECTRON DEVICE LETTERS,US,IEEE INC. NEW YORK, vol. 18, no. 9, 1 September 1997 (1997-09-01), pages 456 - 458, XP000696525, ISSN: 0741-3106 *
LEE W -C ET AL: "INVESTIGATION OF POLY-SI1-CHIGECHI FOR DUAL-GATE CMOS TECHNOLOGY", IEEE ELECTRON DEVICE LETTERS,US,IEEE INC. NEW YORK, vol. 19, no. 7, 1 July 1998 (1998-07-01), pages 247 - 249, XP000755204, ISSN: 0741-3106 *
OEZTUERK M C ET AL: "RAPID THERMAL CHEMICAL VAPOR DEPOSITION OF GERMANIUM AND GERMANIUM/SILICON ALLOYS ON SILICON: NEW APPLICATIONS IN THE FABRICATION OF MOS TRANSISTORS", MATERIALS RESEARCH SOCIETY SYMPOSIUM PROCEEDINGS,US,MATERIALS RESEARCH SOCIETY, PITTSBURG, PA, vol. 224, 30 April 1991 (1991-04-30), pages 223 - 234, XP000198032, ISSN: 0272-9172 *

Also Published As

Publication number Publication date
WO2001041544B1 (en) 2002-01-31
WO2001041544A2 (en) 2001-06-14
TW477075B (en) 2002-02-21

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