WO2001039430A3 - Programmateur de paquets programmable grande vitesse et gestionnaire de mémoire tampon - Google Patents

Programmateur de paquets programmable grande vitesse et gestionnaire de mémoire tampon Download PDF

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Publication number
WO2001039430A3
WO2001039430A3 PCT/CA2000/001389 CA0001389W WO0139430A3 WO 2001039430 A3 WO2001039430 A3 WO 2001039430A3 CA 0001389 W CA0001389 W CA 0001389W WO 0139430 A3 WO0139430 A3 WO 0139430A3
Authority
WO
WIPO (PCT)
Prior art keywords
packet
index
speed
arriving
buffer manager
Prior art date
Application number
PCT/CA2000/001389
Other languages
English (en)
Other versions
WO2001039430A2 (fr
Inventor
Alberto Leon-Garcia
Massoud Hashemi
Original Assignee
Leon Garcia Alberto
Massoud Hashemi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Leon Garcia Alberto, Massoud Hashemi filed Critical Leon Garcia Alberto
Priority to AU16848/01A priority Critical patent/AU1684801A/en
Publication of WO2001039430A2 publication Critical patent/WO2001039430A2/fr
Publication of WO2001039430A3 publication Critical patent/WO2001039430A3/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/254—Centralised controller, i.e. arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5651—Priority, marking, classes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H04L2012/566—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM layer
    • H04L2012/5661—Minicells
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5679—Arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management
    • H04L2012/5683—Buffer or queue management for avoiding head of line blocking
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/50—Overload detection or protection within a single switching element

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

L'invention concerne un procédé et un appareil permettant de gérer la mise en mémoire tampon et de programmer le transfert de paquets de données arrivant sur un ou plusieurs ports d'entrée et destinés à un ou plusieurs ports de sortie d'un commutateur de paquets ou routeur ou d'un sous-système de celui-ci. Un indice est attribué à chaque paquet qui arrive; lequel indice spécifie à la fois un port de sortie à destination unique destiné au paquet et une appartenance à une sous-classe, telle qu'une classe de priorité, une connexion ou un flux. Pour chaque paquet qui arrive, un mini paquet est crée qui contient l'indice du paquet, un identifiant unique, tel qu'une position de stockage. Une file d'attente est attribuée à chaque indice, dans laquelle les mini paquets pourvus dudit indice sont placés dans leur ordre d'arrivée. Les paquets sont transmis depuis la position de stockage vers des ports de sortie en fonction de la séquence des mini paquets produite par le système programmateur.
PCT/CA2000/001389 1999-11-24 2000-11-24 Programmateur de paquets programmable grande vitesse et gestionnaire de mémoire tampon WO2001039430A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU16848/01A AU1684801A (en) 1999-11-24 2000-11-24 A high-speed, programmable packet scheduler and buffer manager

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CA002290265A CA2290265A1 (fr) 1999-11-24 1999-11-24 Ordonnanceur programmable haute vitesse de paquets de donnees et gestionnaire de memoire tampon
CA2,290,265 1999-11-24

Publications (2)

Publication Number Publication Date
WO2001039430A2 WO2001039430A2 (fr) 2001-05-31
WO2001039430A3 true WO2001039430A3 (fr) 2001-10-18

Family

ID=4164692

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2000/001389 WO2001039430A2 (fr) 1999-11-24 2000-11-24 Programmateur de paquets programmable grande vitesse et gestionnaire de mémoire tampon

Country Status (3)

Country Link
AU (1) AU1684801A (fr)
CA (1) CA2290265A1 (fr)
WO (1) WO2001039430A2 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6937607B2 (en) 2001-06-21 2005-08-30 Alcatel Random early discard for cell-switched data switch
US7039914B2 (en) 2003-03-07 2006-05-02 Cisco Technology, Inc. Message processing in network forwarding engine by tracking order of assigned thread in order group
US7636307B2 (en) * 2003-03-13 2009-12-22 Alcatel Lucent Random early packet discard (RED)
US7974191B2 (en) * 2004-03-10 2011-07-05 Alcatel-Lucent Usa Inc. Method, apparatus and system for the synchronized combining of packet data
CN107528789B (zh) * 2016-06-22 2020-02-11 新华三技术有限公司 报文调度方法及装置
CN106528598B (zh) * 2016-09-23 2019-10-18 华为技术有限公司 一种链的管理方法及物理设备

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5850395A (en) * 1995-07-19 1998-12-15 Fujitsu Network Communications, Inc. Asynchronous transfer mode based service consolidation switch

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5850395A (en) * 1995-07-19 1998-12-15 Fujitsu Network Communications, Inc. Asynchronous transfer mode based service consolidation switch

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
HASHEMI M R ET AL: "A GENERAL PURPOSE CELL SEQUENCER/SCHEDULER FOR ATM SWITCHES", KOBE, APRIL 7 - 12, 1997,LOS ALAMITOS, CA: IEEE COMPUTER SOC,US, 7 April 1997 (1997-04-07), pages 29 - 37, XP000850281, ISBN: 0-8186-7782-1 *
HASHEMI M R ET AL: "THE SINGLE-QUEUE SWITCH: A BUILDING BLOCK FOR SWITCHES WITH PROGRAMMABLE SCHEDULING", IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS,US,IEEE INC. NEW YORK, vol. 15, no. 5, 1 June 1997 (1997-06-01), pages 785 - 794, XP000657032, ISSN: 0733-8716 *

Also Published As

Publication number Publication date
CA2290265A1 (fr) 2001-05-24
AU1684801A (en) 2001-06-04
WO2001039430A2 (fr) 2001-05-31

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