AU1684801A - A high-speed, programmable packet scheduler and buffer manager - Google Patents

A high-speed, programmable packet scheduler and buffer manager

Info

Publication number
AU1684801A
AU1684801A AU16848/01A AU1684801A AU1684801A AU 1684801 A AU1684801 A AU 1684801A AU 16848/01 A AU16848/01 A AU 16848/01A AU 1684801 A AU1684801 A AU 1684801A AU 1684801 A AU1684801 A AU 1684801A
Authority
AU
Australia
Prior art keywords
speed
buffer manager
packet scheduler
programmable packet
programmable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU16848/01A
Other languages
English (en)
Inventor
Massoud Hashemi
Alberto Leon-Garcia
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of AU1684801A publication Critical patent/AU1684801A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/254—Centralised controller, i.e. arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5651—Priority, marking, classes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H04L2012/566—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM layer
    • H04L2012/5661—Minicells
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5679—Arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management
    • H04L2012/5683—Buffer or queue management for avoiding head of line blocking
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/50—Overload detection or protection within a single switching element

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
AU16848/01A 1999-11-24 2000-11-24 A high-speed, programmable packet scheduler and buffer manager Abandoned AU1684801A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CA002290265A CA2290265A1 (fr) 1999-11-24 1999-11-24 Ordonnanceur programmable haute vitesse de paquets de donnees et gestionnaire de memoire tampon
CA2290265 1999-11-24
PCT/CA2000/001389 WO2001039430A2 (fr) 1999-11-24 2000-11-24 Programmateur de paquets programmable grande vitesse et gestionnaire de mémoire tampon

Publications (1)

Publication Number Publication Date
AU1684801A true AU1684801A (en) 2001-06-04

Family

ID=4164692

Family Applications (1)

Application Number Title Priority Date Filing Date
AU16848/01A Abandoned AU1684801A (en) 1999-11-24 2000-11-24 A high-speed, programmable packet scheduler and buffer manager

Country Status (3)

Country Link
AU (1) AU1684801A (fr)
CA (1) CA2290265A1 (fr)
WO (1) WO2001039430A2 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6937607B2 (en) * 2001-06-21 2005-08-30 Alcatel Random early discard for cell-switched data switch
US7039914B2 (en) 2003-03-07 2006-05-02 Cisco Technology, Inc. Message processing in network forwarding engine by tracking order of assigned thread in order group
US7636307B2 (en) * 2003-03-13 2009-12-22 Alcatel Lucent Random early packet discard (RED)
US7974191B2 (en) 2004-03-10 2011-07-05 Alcatel-Lucent Usa Inc. Method, apparatus and system for the synchronized combining of packet data
CN107528789B (zh) * 2016-06-22 2020-02-11 新华三技术有限公司 报文调度方法及装置
CN106528598B (zh) 2016-09-23 2019-10-18 华为技术有限公司 一种链的管理方法及物理设备

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5790770A (en) * 1995-07-19 1998-08-04 Fujitsu Network Communications, Inc. Method and apparatus for reducing information loss in a communications network

Also Published As

Publication number Publication date
WO2001039430A2 (fr) 2001-05-31
CA2290265A1 (fr) 2001-05-24
WO2001039430A3 (fr) 2001-10-18

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase