WO2001037285A1 - Method for testing semiconductor memory - Google Patents

Abstract

A variable switch circuit for connecting a wiring for connecting memories together to an arbitrary wiring is provided in a scribe region between memory circuits (chips) formed on a single wafer. An ALPG is constituted of part of the memory circuits. Thus, a test circuit on wafer level for testing the remaining memories by means of such an ALPG is realized.

Description

 Description Semiconductor memory inspection method Technical field

 The present invention relates to a technology for diagnosing a semiconductor integrated circuit (IC), and a technology for diagnosing a semiconductor integrated circuit in a wafer state. About technology. Background art

 Conventionally, as a diagnostic method for semiconductor memory, a test device called a test device generates a test pattern data, inputs the test data to the memory, writes the data, and then writes the written data from the memory. It was common to read and compare with the expected value.

 Also, a pattern generator which is described in the form of a program executable on a convenience store and generates a memory test pattern according to a predetermined algorithm, and a pattern generator which is formed by providing a memory logical design data is provided. There is a technology called “virtual test” that consists of a simulation and a memory test in which a memory designed using test patterns is inspected on a computer.

In a conventional general diagnosis method in which test pattern data is generated by a test and input to a memory, the IC constituting the test is one generation or more than the IC memory to be inspected. It is manufactured using the technology of the previous generation, and the next generation of ICs will be inspected at a test composed of such old generation ICs. As a result, the specifications required for testing ICs are extremely strict, and in order to achieve the desired speed, multiple identical circuits are prepared and parallel processing is performed. There was a problem that the entire area had to be complex and large-scale.

 Also, in the diagnostic method based on virtual test, a test pattern formed by a pattern generator must be stored in a storage device. Since the number of steps is hundreds of millions, there is a problem that the capacity of the ordinary computer system becomes insufficient and the inspection time becomes longer.

 Therefore, a micro-instruction-type control unit that generates a test pattern (address and data) of the memory circuit according to a predetermined algorithm and reads the written data over a semiconductor chip on which the memory circuit is mounted, and ALPG (Algorithmic Memory Pattern Generator) that consists of a data processing unit and a data judgment unit that judges the read data and outputs the judgment result, and can generate a predetermined test pattern according to a built-in program. The present inventors have proposed an invention related to a semiconductor memory equipped with a test circuit, which is referred to as “International Publication WO98 / 47152”.

 Since the above ALPG is constructed using the same process technology as the memory in which it is mounted, the circuit scale can be reduced to a large scale (hundreds of hundreds) compared to external testing. It is a technology that can be fully commercialized. However, it is inevitable that the chip size of a semiconductor memory equipped with ALPG will increase. For this reason, there are some semiconductor integrated circuits (ASICs) for practical use, but in the field of general-purpose memories, there is a demand to reduce the chip area as much as possible.

In addition, in semiconductor memory inspection, in addition to inspection at the wafer stage, high-temperature inspection called an aging test is performed to find potential defective products at an early stage. Conventionally, this aging test A number of 100 to 100 pieces of memory assembled in a package were mounted on a printed circuit board called an aging board, and a test pattern was applied from an external tester. As described above, the reason why the paging test is performed using an external tester is that if a test pattern is to be input to all chips in a wafer state, the number of probes is several hundred or more, and the structure is increased. This is because it is too complicated and the contact pressure reaches several tons, making it very difficult to realize.

 An object of the present invention is to provide a memory diagnosis technique capable of performing a diagnosis of a semiconductor memory without using an external tester.

 Another object of the present invention is to provide a memory diagnosis technique capable of performing an aging test of a semiconductor memory without using an external tester.

 Still another object of the present invention is to provide a memory diagnosis technique capable of performing a self-diagnosis of a semiconductor memory without increasing a chip size.

 The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

 The outline of a representative invention among the inventions disclosed in the present application is as follows.

That is, according to the present invention, the memory circuit outputs a predetermined logical signal (data) stored in advance when a certain signal (address) is input. Focusing on the fact that ALPG is composed of logic circuits such as combinational circuits and sequential circuits, and multiple memory circuits (chips) are formed simultaneously. Scribe between memory circuits on a single wafer A variable switch circuit is provided in the area to allow connection between each memory and a connection between any wires, and an ALPG is configured using a part of the memory circuits on the wafer. It implements a wafer-level test circuit for testing the remaining memory. When a sequential circuit is configured using a memory circuit, a feedback path from the data output terminal to the address input terminal is required, but this is also realized by the wiring provided in the scribe area and the variable switch circuit. can do. According to the above-described means, since the ALPG can be configured using an arbitrary memory circuit on the wafer and the remaining memory circuits can be inspected, the ALPG can be configured again using the memory circuits that have been inspected. Inspection of the rest of the memory circuits allows the inspection of all memory circuits on the wafer to be performed on the wafer without using an external tester. In addition, since a memory circuit can be inspected without using an external tester by forming a test circuit on the wafer, the aging test can be performed on the wafer and the test can be performed on each memory chip. Since no circuit is required, it is possible to realize a memory with no overhead, that is, a memory with a small chip size. However, since the test auxiliary circuit formed on the same wafer as the memory is formed using the same manufacturing technology as the memory, that is, the same generation circuit, the same operation speed as the memory to be tested can be easily achieved. It does not require a cable with a large signal delay unlike the case of using an external tester, so memory diagnosis can be performed in a short time.

Furthermore, when an ALPG is composed of multiple memory circuits on a single wafer, the ALPG is written in HDL (hardware 'disclosure' language) language, which is then decoded by a computer to construct the ALPG. Generates the connection information of the variable switch circuit necessary for this, creates a program that generates the control signal of the variable switch circuit according to the connection information, and uses this to efficiently configure the ALPG on the wafer. Do Can be.

 In the case of a memory having a redundant circuit having a spare memory row or a spare memory column that can be replaced with a defective bit around the memory circuit, the most appropriate spare memory is determined based on the determination result from the data determination means. It is also possible to provide an algorithm for selecting a memory row or spare memory column and replacing it with a defective bit, and to provide a self-rescue circuit that performs address conversion for replacing the defective bit according to the algorithm.

 Further, a logic circuit using the above memory circuit can be provided with a self-test function for performing a logic test of itself for each memory circuit. The logic circuit having the self-test function includes a memory circuit, a comparison circuit that compares data written in the memory circuit with data read from the memory circuit, and an address signal supplied to the memory circuit. A variable address conversion circuit that performs conversion based on a comparison result in the comparison circuit, wherein an input signal of a logic circuit having a desired logic function is used as an address signal to the memory circuit, It can be realized by writing data into the memory circuit so that the output signal is expected from the input signal of the logic circuit.o Brief description of the drawings

 FIG. 1 is a block diagram showing a schematic configuration of ALPG for testing a semiconductor memory.

 FIG. 2 is a block diagram illustrating a configuration example of a sequence control unit configuring ALPG.

 FIG. 3 is a block diagram illustrating a configuration example of an address operation unit included in ALPG.

Figure 4 shows an example of the configuration of the test data generation and calculation unit that constitutes the ALPG FIG.

 FIG. 5 is a block diagram showing a conceptual diagram in a case where the ALPG is configured on a wafer using a plurality of memory circuits on a wafer.

 FIG. 6 is a block diagram showing an example of a memory circuit and an auxiliary circuit that can configure an ALPG using the memory circuit.

 FIG. 7 is an explanatory diagram showing an example of a logic gate circuit composed of a memory circuit and an auxiliary circuit and an HDL description thereof.

 FIG. 8 is a circuit diagram showing a configuration example of a suitable address decoder when the present invention is applied.

 FIG. 9 is a circuit configuration diagram showing an example of a switch matrix as an auxiliary circuit that can configure the ALPG.

 FIG. 10 is a circuit configuration diagram showing an example of data storage as an auxiliary circuit that can configure the ALPG.

 FIG. 11 is an explanatory diagram showing another example (a flip-flop) of a logic gate circuit composed of a memory circuit and an auxiliary circuit and its HDL description.

 FIG. 12 is a block diagram showing another example of a memory circuit and an auxiliary circuit which can configure an ALPG using the memory circuit.

 FIG. 13 is a circuit configuration diagram showing an example of a variable address conversion circuit as an auxiliary circuit that can configure an ALPG. .

 FIG. 14 is a circuit configuration diagram showing an example of a data comparator as an auxiliary circuit that can configure an ALPG.

 FIG. 15 is a flowchart showing how to change an address in the variable address conversion circuit.

 FIG. 16 is a plan view showing a part of a wafer to which the present invention is applied. FIG. 17 is a schematic configuration diagram showing another embodiment of the present invention.

FIG. 18 shows an example of a test wiring structure on a wafer to which the present invention is applied. It is sectional drawing which shows an example.

 FIG. 19 is a plane layout diagram showing a pattern example of a first layer of a test wiring in a wafer to which the present invention is applied.

 FIG. 20 is a plan layout diagram showing a pattern example of the second layer of the test wiring on the wafer to which the present invention is applied.

 FIG. 21 is a plan layout diagram showing a pattern example of a third layer of test wiring on a wafer to which the present invention is applied.

 FIG. 22 is a plane layout diagram showing a pattern example of the first to third layers of the test wiring on the wafer to which the present invention is applied.

 FIG. 23 is a flowchart showing a conventional semiconductor memory inspection procedure.

Ό o

 FIG. 24 is a flowchart showing a procedure for inspecting a semiconductor memory according to the present invention.

 FIG. 25 is a flowchart showing an example of a bad bit test procedure.

 Figure 26 is a flowchart showing another example of the bad bit test procedure.

 FIG. 27 is a flowchart showing another example of a procedure for inspecting a semiconductor memory to which the present invention is applied.

 FIG. 28 is a flowchart showing the procedure of the defective bit test and the bit rescue processing.

 FIG. 29 is a plan view showing an example of a case where a test circuit (ALPG) is formed on an aging board.

 Figure 30 is a flowchart showing the test procedure when Aging is configured on the board and the remaining memory is tested.

Figure 31 shows an example in which an ALPG is configured on an aging board. 5 is a flowchart showing a memory inspection procedure in a copy processing.

BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 shows a schematic configuration of an ALPG that generates a test pattern for testing a memory circuit. The ALPG is composed of an instruction memory 11 storing a microprogram composed of a plurality of microinstructions described according to a predetermined test pattern generation algorithm, and a program counter 1 for designating a microinstruction to be read from the instruction memory 11. 2 and a sequence control circuit that decodes the instruction code in the microinstruction read from the instruction memory 11 and forms a control signal for the memory circuit and a control signal for the function block that constitutes the ALPG, such as the program counter 12. 13, an address operation circuit 14 that generates a test address according to the microinstruction read from the instruction memory 11, and a test that generates test data and expected value data according to the read microinstruction It is composed of a data generation circuit 15 and the like.

 In order to determine whether or not the memory circuit to be inspected is normal, it is necessary to have a means for comparing the data read from the memory circuit with the written data to determine whether they match. Such a comparison and judgment circuit can be provided in the ALPG, but it can also be performed by an external computer. Therefore, in the present embodiment, such a comparison / determination function is provided in an external computer to facilitate understanding, and the description will be made assuming that ALPG does not have a comparison / determination function.

As shown in FIG. 1, the microphone opening instruction stored in the instruction memory 11 includes an address field MFa in which a PC address indicating a jump address of an instruction used in a jump instruction is stored, and Sequence control code An opcode field MF b to be stored, an operand field MF c to store the number of instruction repetitions, and the like, and a control field MF to store a control code for instructing output and read / write of addresses and data. d, an address operation code field MFe in which an address operation instruction code is stored, a data generation code field MFf in which a data generation instruction code is stored, and the like.

 FIG. 2 shows a configuration example of the sequence control circuit 13. The sequence control circuit 13 of this embodiment is configured to decode the control code of the obbe code field MFb to form a control signal by decoding an instruction decoding control unit 30 and a value of the program counter 12. + 1 ”, a multiplexer 3 2 for selecting either the above-mentioned increment address 31 or the jump address in the address field MFa and supplying it to the program counter 1 2 and an operand filter 3. The index register 33 holding the number of repetitions in one field MF c, the decrement evening 34 to set the value of the index register 33 to “1 1”, and “1 1” A working register 35 that holds the value, a flag 36 that indicates the presence or absence of data reversal used in the jXd instruction (see Table 1) described later, and an operand program counter 12 that is used in the jindex instruction A flag 37 indicating the presence / absence of data transfer, a multiplexer 38 for selectively supplying the values of the registers 33 and 35 to the above-mentioned decrement register 34, and a working register 3 indicating the value of the decrement register 34. It consists of a demultiplexer 39 that distributes to any one of the five planes.

Table 1 shows the types and contents of the opcodes stored in the opcode field MFb in the microinstruction and used for the sequence control. 【table 1】

In Table 1, the instruction indicated by “nopj” is a no-operation S instruction that instructs the value of the program counter 12 to “+1” at increment 31 and returns to the program counter 12, that is, the program. This command instructs to move to the next command without performing any operation other than updating the county.

“Jindex 1” to “jindex 4” are instructions prepared for turning the instruction loop by jumping. In a memory pattern test, if the number of instructions can be reduced by repeatedly executing the same instruction using a jump instruction (for example, by incrementing the address to the final address, all memory cells can be used). (Such as writing and reading “1”). In this embodiment, an index register 33 is provided so that the number of loops (jumps) can be set, and a jump instruction is provided so that a plurality of types of determination methods can be executed. There are four index registries and 33 working regis- ters.

 Since each jump instruction has the same control content, the control operation using “jindexl” will be described below, and the other will be omitted.

 When the jindex 1 instruction is read from the opcode field MFb, it is determined whether the instruction is the first jindexl instruction, and the determination result is reflected in the flag 37. Specifically, the flag jf1 is set to 0 for the first jindexl, and jf1 is set to 1 for the second and subsequent times.

 When the jindex 1 instruction is read when the flag jf 1 = 0, the multiplexer 32 is controlled to set the PC address in the address field MFa of the micro instruction to the program counter 12, thereby controlling the microcontroller. The instruction jumps to that address and the flag jf1 is set to "1". At the same time, the number of loops in the operand field MFc is read into idX of the index register 33.

 If the jindex 1 instruction is read while the flag jf 1 = 1, the PC address in the address field MFa of the micro instruction is set in the program counter 12 and the loop in idx 1 of the index register 33 is set. The count is supplied to the decrement unit 34 via the multiplexer 38 and is stored in the working register 35 i dxwl via the demultiplexer 39. The working register 35 i When dxwl becomes “0”, the PC address in the address field MF a of the microphone opening instruction is not set to the program counter 12, and instead, the address of the program counter 12 is set to “1” in the increment counter 31. The multiplexer 32 is controlled to return “+1” to the program counter 12.

Therefore, the microcode opcode field MF b has the jindex Is stored in the address field MFa, the same jindex instruction is executed as many times as the number in the operand field MFc, and the loop is repeated. 12 is incremented, and control is performed such that the process proceeds to the next microphone opening instruction and exits the loop.

 In addition, “jXd” in Table 1 refers to df1g in flag 37, and when the flag is “0”, transfers the operand to the program counter and jumps to the jump address indicated by the operand. Jump to the instruction of the instruction and set the dflg flag to “1”, and look at the df1g flag, and when the flag is “1”, increment the value of the program counter to increase the program power. This is an instruction to return to df1g and reset the df1g flag to “0”.

 "Jmp" is an instruction to transfer the operand to the program counter and jump to the instruction at the jump address indicated by the operand. “Stp” is a stop command to end the sequence control.

 FIG. 3 shows a configuration example of the address operation circuit 14. The address operation circuit 14 of this embodiment is roughly composed of an X address operation unit 41 for generating an X address and a Y address operation unit 42 for generating a Y address. Since the X address operation unit 41 and the Y address operation unit 42 have almost the same configuration, the configuration of the X address operation unit 41 will be described below, and the description of the configuration of the Y address operation unit 42 will be omitted. In addition, by providing an impermissible Z-address operation unit as needed, a partial pattern can be generated (partial pattern).

The X address operation unit 41 includes an initial value register Xhold for storing an initial value of the X address, zero setting means 43 for holding “0”, and either an initial value of the X address or “0”. Multiplexer MUX 1 to select the Pace register Xbase that retains the selected initial value or `` 0 '', first arithmetic unit ALU 1 that adds the value of register Xbase, and the arithmetic result of arithmetic unit ALU 1 or `` 0 '' or feedback value A second multi-blexer MUX2 that selects one of them, a current register Xcurrent that holds the selected value, a second arithmetic unit ALU2 that adds or subtracts the value of the register Xcurrent, and this second operation A third multiplexer MUX3 for selecting either the output of the arithmetic unit ALU2 or the output of the first arithmetic unit ALU1, and an inverter I NV capable of inverting the selected output. This impulse I NV is provided in the memory pattern test because it may test for malfunction due to address signal switching noise, and it is necessary to output an inverted signal of the address signal at that time. By using this inverse signal, an inverted signal of the address in such a test can be easily formed.

 Although not particularly limited, in this embodiment, the X address generated by the arithmetic units ALU 1 and ALU 2 of the X address arithmetic unit 41 is sent to the Y address side, and the Y address generated by the Y address arithmetic unit 42 is sent to the Y address side. A third multiplexer MUX 3 is configured to output to the X address side. Thus, it is configured to be used as a test circuit for any of a plurality of types of memories, for example, an address multiplex type memory and an address non-multiplex type memory. In other words, by simply rewriting the microinstructions stored in the instruction memory 11, the necessary test patterns can be generated and tested for all memories.

The difference between the X address operation unit 41 and the Y address operation unit 42 is that when the first operation unit ALU 1 of the X address operation unit 41 overflows, the first operation unit A LU 1 of the Y address operation unit 42 overflows. On the other hand, a polo signal BR is supplied. Table 2 shows the types of operation codes stored in the operation code field MF e in the microinstruction and used for the Y address operation (pace operation) in the first arithmetic unit ALU 1 of the Y address operation unit 42 and the type The contents are shown.

 [Table 2]

 In Table 2, Ybase 0 is an instruction to set the value of the pace register Ybase to “0”, Ybase Yhold is an instruction to put the contents of the initial value register Yhold into the pace register Ybase, Ybase Yb ase + 1 is an instruction that increments (+1) the value of the base register Ybase and returns it to the base Ybase. Ybase— Ybase + 1 (BR) indicates that the value of the base register Ybase is not the maximum value. This command instructs to leave the value of Ybase as it is, and if the value of Xbase is the maximum value, increment the value of Ybase and return to Ybase.

Table 3 shows the types and contents of the operation codes used for the address operation in the first operation unit ALU1 of the X address operation unit 41. Table 4 shows the types and contents of operation codes used in the Y address operation (current operation) in the second operation unit ALU 2 of the Y address operation unit 42. Table 5 shows the types and contents of the operation codes used for the address operation in the second operation unit ALU 2 of the X address operation unit 41. Have been

 [Table 3]

Xbase operation operation

Xbase ^ -Xbase Non Operation Xbase— 0 0 → Xbase

Xbsset Xhold Xhol Xbase, Xbas0 * -Xbase + 1 Xbase + 1 → Xbase

Xbase-*-Xbase-1 Xbase-1 → Xbase

[Table 5]

 FIG. 4 shows a configuration example of the test data generation circuit 15. The test data generation circuit 15 of this embodiment includes an initial value register Thold for storing an initial value of the write data, and a test data generator for outputting the initial value (or the result of the arithmetic unit ALU). And a computing unit ALU having a bit shift function, and an inverter INVERT capable of inverting the output of the computing unit ALU. .

Table 6 shows the types and contents of the control codes stored in the data generation code field MFf in the microinstruction and used for the operation control in the test data generation circuit 15. ing. In Table 6, instructions represented by the same rules as the instructions in Tables 3 to 5 are almost the same. Tp Tp * 2 controls the register Tp and the arithmetic unit ALU, processes the 18-bit data in the register Tp with the arithmetic unit ALU, and sends the bit string to the MSB or LSB side. This is an instruction to shift the bits back to the register Tp. With this instruction, even if the memory unit is a type of memory in which data is read / written in units such as one word or one byte, data “1” is stored in memory cells one bit at a time. The test data for writing can be generated relatively easily. [Table 6]

 FIG. 5 shows a conceptual diagram in the case where the above ALPG is configured on a wafer using a plurality of memory circuits on a wafer. In FIG. 5, MEM is a readable and writable memory circuit such as a well-known general-purpose SRAM (static random access memory) or DRAM (dynamic random access memory). The gap between each of the memory circuits MEM is a scribe area serving as a cut portion when each memory circuit is divided into chips.

 In this embodiment, a wiring for enabling connection between the memory circuits MEM and a variable switch circuit for enabling connection between arbitrary wirings and an auxiliary circuit for configuring the ALPG are provided in advance in the scribe area. Then, after completion of the wafer, an arbitrary memory circuit MEM on the wafer is stored in the above-mentioned program counter 12, an incrementer 31, a multiplexer 32, an index register 33, an address arithmetic circuit 41, 42, etc., which constitute the ALPG. A logic function circuit is configured, and between each function circuit, that is, between each memory circuit, is connected by the wiring and the variable switch circuit provided in the scribe area, and an auxiliary circuit is further connected thereto to form an AL PG. .

Thereafter, the test pattern generated by the ALPG is supplied to the remaining memory circuits that do not constitute the ALPG by the ALPG configured in this manner, written and read, and the memory circuit is inspected. It is. In FIG. 5, the broken line indicates the flow of data for initial setting, and the solid line indicates the flow of data when operating as ALPG. Each memory times The initial data is set in the path MEM by inputting an address in the same way as a normal memory and writing data to the selected memory cell. When operating as an ALPG, in each memory circuit MEM, an input signal is given to an address terminal, and an output signal is taken out from a data terminal.

 Next, a specific method for configuring a logic function circuit such as a program counter 12 that configures an ALP G using a general-purpose memory circuit MEM, and specific connection means and auxiliary circuits required for the method are described. An example will be described.

 FIG. 6 shows a block diagram of an example of a variable logic function circuit 100 that enables the realization of a program counter 12 and other arbitrary logic function circuits that constitute an AL PG on a wafer using the memory circuit MEM. ing.

 In FIG. 6, reference numeral 110 denotes a readable and writable memory circuit having almost the same configuration as a known general-purpose DRAM (dynamic random access memory) or SRAM (static random access memory). And corresponds to the memory circuit on the wafer shown in FIG. The variable logic function circuit 100 is configured by combining the data storage circuit 160 and the switch matrix circuit 170 with the memory circuit 110. In this embodiment, the storage circuit 160 and the switch matrix circuit 170 are the auxiliary circuits formed in the scribe area of the wafer. However, since the data storage circuit 160 is one type of memory, it can be configured using the memory circuit MEM on the wafer in FIG.

In the memory circuit 110, a plurality of memory cells are arranged in a matrix, a plurality of word lines and a plurality of data lines are arranged in a grid, and the memory cells in the same row correspond to each other. The memory cells connected to the word line and in the same column are connected to the corresponding data lines, respectively. The memory array 111 is connected to the memory array 1 by decoding the supplied address signal. 11 The address decoder 1 12 that sets one corresponding one of the lead lines to the selected level, and the potential read out from the memory cell connected to the selected word line to the data line. It comprises a sense amplifier circuit 113 for amplification and a write / read control circuit 114 for controlling the operation timing of the sense circuit 113 and the like based on the chip select signal CE and the write control signal WE. 141 is an address input terminal to which an address signal is input, and 142 is a data input / output terminal to output read data from the memory circuit to the outside or to input write data from the outside.

 FIG. 7 shows an example (combinational circuit) of a logic gate circuit constituted by the variable logic function circuit of the embodiment and its HDL description. To configure a logic circuit having a desired logic function according to the HDL description using the variable logic function circuit of the embodiment, for example, a control device such as a general-purpose microcomputer is used as shown in FIG. Reads and decodes the HDL description from the storage device (file) that stores the design data described in the HDL description, and forms signals for configuring the corresponding logic functions in the variable logic function circuit 100. And output it.

 Next, a specific logic configuration method will be described using the NAND gate circuit of FIG. 7 as an example. First, the control device decodes the HDL description to recognize that the configuration target is a NAND gate circuit. For example, a truth signal in Table 7 below is shown as an address signal to be supplied to the variable logic function circuit 100. The combination of the input signals I n 0, 1 11 1 generates “0, 0”, “1, 0”, “0, 1”, “1, 1”.

Then, the generated address signal is applied to the address input terminal 141 (see FIG. 6) of the variable logic function circuit 100. At the same time, the control device 300 generates a data corresponding to the output Out 0 of the truth table as a write data corresponding to each of the above addresses, and outputs the write data to the variable logic function circuit 100. Data input in parallel with the input of the address signal. Apply to output terminal 1 4 2

 [Table 7]

Then, in the variable logic function circuit 100, the data is written to the memory circuit 110. Therefore, when the input signals I n0 and I n1 of the NAND gate circuit are inputted to the predetermined address input terminal 141 of the variable logic function circuit 100 after the end of writing, the corresponding signals stored in the memory circuit are obtained. Data is read out and a signal corresponding to the output Out 0 of the NAND gate circuit is output from a predetermined terminal of the data input / output terminals 142. As described above, when the variable logic function circuit of the embodiment of FIG. 6 is used, a desired logic function is realized by writing data into the memory circuit 110 in accordance with the HDL description. If the combinational logic circuit whose output state is determined by the input state is determined using the variable logic function circuit of the embodiment, the data storage 160 and the switch matrix 170 are unnecessary. It is. These circuits are used when a sequential circuit is configured using the variable logic function circuit of the embodiment as described later. Since not all ALPGs are sequential circuits, they include sequential circuits and combinational circuits, so that all memory circuits on a wafer can be used as auxiliary circuits for storage 160 · It is not necessary to provide a matrix 170.

Note that the two-input NAND gate circuit described above is When using a circuit, the input address signal may be 2 bits. Therefore, the address decoder 1 12 shown in FIG. 6 is divided into, for example, two bits, and one pad line in the memory array 111 can be selected with only two bits. It is good to do.

 As a result, a plurality of logic gate circuits can be realized by one variable logic function circuit. In addition, in order to have the same address configuration as the conventional memory and to realize a plurality of logic gate circuits with one memory array, it is necessary to complement address bits other than the above-mentioned input bits. If division is performed, address completion is not required. However, no address division is performed by assigning a number to each logic gate circuit that constitutes the logic to be implemented and using that number as the complementary address as the address of the logic gate to be focused on as the address of the logic gate of interest. It is also possible to use a memory array.

 FIG. 8 shows an example of such an address decoder capable of address division. In the address decoder of FIG. 8, seven AND gates G1 to G7 are connected in a pyramid shape corresponding to the eight address signals A0 to A7, and the unit decode circuits DEC1 and DEC2 are connected. .. Are configured. In a conventional address decoder without address division, all the outputs of G1 to G4 of the four AND gates in the first stage are configured to be input to the AND gate G5 or G6 in the second stage In contrast, in the address decoder of FIG. 8, only one of the outputs of the four AND gates G1 to G4 of the first stage is input to the AND gate G5 or G6 of the second stage. The remaining three outputs are configured so that their signal lines are fixed to a high level by being pulled up to Vcc.

As a method of fixing such a signal in an address decoder of a general-purpose semiconductor memory, for example, a high-resistance bloom is applied to the input terminals of the second-stage AND gates G5 and G6 which are to be set to a high level. It is necessary to connect to a dedicated power supply voltage line or the like via a test resistor, or to provide a switching switch at the input terminals of the second-stage AND gates G5 and G6, A method of applying Vcc only to the input terminal can be considered. In this case, the wiring for supplying Vcc and the wiring for supplying a signal for controlling the switching switch can be shared for each AND gate, and further, the wiring can be shared for all memory circuits on the wafer. Therefore, it is only necessary to provide one or two pads on the wafer.

 Note that the address decoder is not limited to the type using a two-input AND gate as shown in FIG. 8, and the same type is used for a type using another logic gate such as a three-input NAND gate. You can split the address in any way. Also, depending on the type of the gate circuit constituting the address decoder, the input of the gate circuit may be fixed to the ground potential instead of Vcc.

 FIG. 9 is a circuit configuration diagram showing a specific example of the switch matrix 170 included in the variable logic function circuit (FIG. 6) of the embodiment.

 As shown in FIG. 9 (A), the switch matrix 170 includes a plurality of signal lines 171 on which the address signal input to the address input terminal 141 is carried and the output signal of the storage 160. The signal lines 172 and 172 are arranged in a grid pattern so as to intersect each other, and a switching circuit 173 is arranged at each intersection of the signal lines 171 and 172. In addition, a control information RAM 174 for storing control information of each switching circuit 173 is provided. This control information RAM 174 can also be configured using the memory circuit MEM on the wafer.

As shown in FIG. 9 (B), the switching circuit 173 complements the address signal input from the address input terminal 141 or the output signal of the data storage 160 in order to select and output the selected signal. Switch elements SW1, SW consisting of a pair of MOSFETs that are turned on and off It is composed of two. The gate terminals of the switch elements SW1 and SW2 are configured to be controlled according to the control information stored in the control information RAM 174. However, instead of preparing the control information RAM 174, as shown in FIG. 9 (C), each intersection of the signal line 171 and the signal line 172 is a static memory cell similar to the S RAM cell. A configuration in which an MC and a switching switch C SW are provided may be employed.

 FIG. 10 is a logical configuration diagram showing a specific example of the data storage circuit 160 included in the variable logic function circuit (FIG. 6) of the embodiment.

 As shown in FIG. 10, the data storage circuit 160 includes a flip-flop FF provided corresponding to each two data lines of the memory array 111 in the memory circuit 110. 1, FF2, FFn, and AND gates G1, G2, ... Gn for forming a latch clock for each flip-flop.

 Then, in each flip-flop FFi, one signal (d i) of a pair of data lines is input to a data input terminal D. The other signal (A i) of the pair of data lines is input to the AND gate G i together with the system clock signal CLK. The output signal of the AND gate G i is input to the clock terminal ck of the corresponding flip-flop FF i, and the output signal to the terminal D is synchronized with the falling or rising of the signal to the clock terminal ck. The input signal is configured to be taken into the flip-flop FFi.

In the circuit of FIG. 10, when the signal A i is at a low level, the output of the AND gate G i is fixed to the mouth pelvis, so that even if the system clock CLK changes, the corresponding flip-flop FF i Does not perform latch operation. That is, in this embodiment, the signal A i is used as a signal (hereinafter, referred to as an active bit) for controlling whether or not the data is taken into the flip-flop FF i in one day. As shown in FIG. 7, the method of using the variable logic function circuit of the embodiment to configure a combinational circuit in which the output state (output data) is uniquely determined by the input state (input address) has already been described. With the above method, it is not possible to construct a sequential circuit. On the other hand, by using the data storage 160 having the above-described operating characteristics, the data read from the memory circuit 110 is selectively held according to a certain input state, By supplying this to the address decoder 112 via the switch and the matrix 170, the next input state can be controlled by the previous output data. In other words, this makes it possible to configure a sequential circuit.

 FIG. 11 shows a flip-flop circuit as an example (sequential circuit) of a logic circuit constituted by the variable logic function circuit of the embodiment shown in FIG. 6 and its HDL description. In the flip-flop circuit shown in FIG. 11, each output terminal of two NAND gate circuits G11 and G12 is connected to one input terminal of the other NAND gate circuit.

The truth table representing the output signal states corresponding to the input signals of the two NAND gate circuits G 11 and G 12 constituting this flip-flop circuit is as shown in Table 8 below. In Table 8, A 1 and A 2 are the above-mentioned active bits stored in the memory circuit 110 corresponding to the input, and the output value of the flip-flop corresponds only when this active bit is “1”. Output the truth value data of the NAND gate. [Table 8]

When a flip-flop circuit as shown in FIG. 11 is configured using the variable logic function circuit of FIG. 6, first, four input signals In 0, In 1, In 2, and I 2 n 3 is input from the address input terminal 141 to the address decoder via the switch matrix 170, and the output data d 1, A 1, d 2, of the truth table of Table 8 corresponding to the combination of these input signals A2 is output from the data input / output terminal 142. As a result, the output data d 1 of the truth table is stored at a predetermined address of the memory array 111 in the memory circuit 110 using the input signals InO, In1, In2, and In3 as addresses. , A 1, d 2, A 2 are written.

Next, in order to set the feedback loop of the flip-flop circuit to be configured, the state of a predetermined flip-flop (for example, FF1, FF2) in the data storage 160 is set. More specifically, first, the input signals In2 and In3 are fixed to "0", respectively, and attention is paid to the NAND gate circuit G11, and the input signals In0 and In1 are applied to the flip-flop FF1. "0, 0", "1, 0", "0, 1" according to the data to be retained Or set to "1, 1" and input from the address input terminal 141.

 Then, as shown in the columns a, b, c, and d of Table 8, when the input signals In2 and In3 are both fixed to "0", the NAND gate circuit G1 Is read as active bit A1 corresponding to. Therefore, the clock CLK is supplied to the flip-flop FF1 through the AND gate G1 of the storage 160. As a result, the data dl of "1" or "0" is taken into the flip-flop FF1 according to the combination of the input signals In0 and In1 at that time. That is, the state of the flip-flop FF1 is set.

 Next, the input signals In0 and Inl are fixed to "0", respectively, and attention is paid to the NAND gate circuit G12, and the input signals In2 and In3 are stored in the flip-flop FF2 according to the data to be held. To "0, 0", "1, 0", "0, 1" or "1, 1" and input from the address input terminal 141.

 Then, as shown in the columns of a, e, i, and m in Table 8, when the input signals In 0 and In 1 are both fixed to “0”, the N AND gate "1" is read out as active bit A2 corresponding to circuit G2. Therefore, the clock CLK is supplied to the flip-flop FF2 through the AND gate G2 of the storage 60. As a result, the data d2 of "1" or "0" is taken into the flip-flop FF2 according to the combination of the input signals In2 and In3 at that time. That is, the state of the flip-flop F F2 is set.

Note that the flip-flop consisting of two NAND gates as shown in Fig. 11 has an output Out because each output signal is fed back to one input terminal of the other NAND gate. 0 and Out 1 cannot be "0" at the same time. Therefore, when setting the states of the flip-flops FF 1 and FF 2 of the data storage 160, both of the holding states are “0”. Care must be taken to avoid this.

 After setting the flip-flops FF 1 and FF 2 to the desired state as described above, the switch CSW enclosed by a dotted line in FIG. 9A in the control information RAM 74 in the switch 'matrix circuit 170 31 Rewrite the data stored in the memory cells corresponding to 1 and C SW22, and switch those switches from the address input terminal 141 to the data storage 160 output terminal. As a result, the input signals I n1 and I n2 of the flip-flop of FIG. 11 are not permitted to be input, and the outputs Out 0 and Out 1 of the NAND gates G 11 and G 12 are instead used. It is supplied to the next-stage address decoder 112 as an input signal (address). In other words, this forms a feedback loop of the flip-flop.

 Using the variable logic function circuit of the embodiment of FIG. 6 to logically configure the flip-flop circuit having the configuration shown in FIG. 11 according to the HDL description of FIG. By decoding the L description, it recognizes that the configuration target is a flip-flop circuit. For example, as an address signal to be supplied to the variable logic function circuit 100, the input signal I n 0 shown in the truth table of Table 8 described above. , In 1, In 2, In 3 combination "0, 0, 0, 0,," 1, 0, 0, 0, ..., "0, 1, 0, 0, ......" 1 , 1, 1, 1 ".

 Then, the generated address signal is applied to the address input terminal 141 of the self-configuration circuit 100. At the same time, the controller generates the active bits' data A1, A2 corresponding to the data d1 and d2 in the truth table and the corresponding data bits A1 and A2 as the write data corresponding to the above addresses. The variable signal is applied to the input / output terminal 142 in parallel with the input of the address signal to the logic function circuit 100 in time.

Then, in the variable logic function circuit 100, the data to the memory circuit 110 is stored. Write in the evening. Therefore, when the input signals In0 to In3 of the flip-flop circuit are input to the predetermined address input terminal 141 of the variable logic function circuit 100 after the writing is completed, the corresponding data (output) stored in the memory circuit is output. The data bits dl and d2 and the active bits Al and A2) are read. Then, first, the output data corresponding to the bits whose active bits Al and A2 are "1" is taken into the flip-flop FFi shown in FIG. This is supplied to the address decoder 112 via the switch matrix 170.

 As a result, the next data is read from the memory circuit 110 in accordance with the previously read data, and the signal corresponding to the output Out 0, 0 ut 1 of the flip-flop circuit is decoded. Output from the specified input / output terminal 142. As described above, when the variable logic function circuit of the embodiment of FIG. 6 is used, flip-flop logic can be configured by writing data to the memory circuit 110 according to the HDL description. A desired logic function including a circuit is realized.

 In order to construct a desired logic circuit using a variable logic function circuit by a computer, first, an HDL description is decoded, and a combinational circuit and a sequential circuit constituting the logic circuit are extracted from the HDL description. Next, a truth table, that is, truth value data for the extracted combinational circuit or sequential circuit is generated. Then, data is written to the memory circuit 110 of the variable logic function circuit 100 using the generated truth value data. In addition, the computer interprets the HDL description and, when judging that the extracted logic circuit is a sequential circuit, extracts circuit connection information of the sequential circuit of interest, and extracts the extracted circuit connection information. The control information to be stored and stored in the control information RAM 174 of the switch matrix circuit 170 may be generated and written.

By the way, before testing the memory circuit by ALPG configured on the wafer It is unknown whether or not each memory circuit on the wafer contains a defect. Then, even if each memory circuit has a defect, the program counter 12 that constitutes the ALPG by automatically avoiding the defect and implements any other logic function circuit can be realized. An example of a configurable variable logic function circuit will be described with reference to FIGS.

 In FIG. 12, reference numeral 110 denotes a readable and writable memory circuit having substantially the same configuration as a well-known general-purpose DRAM (dynamic random 'access' memory) or SRAM (static' random access memory). The memory circuit 110 is combined with the input / output & comparison circuit 120 and the variable address conversion circuit 130 to form a variable logic function circuit. Here, a part of the input / output & comparison circuit 120 and the variable address conversion circuit 130 is formed in the scribe area of the wafer as an auxiliary circuit.

 The input / output & comparison circuit 120 as an auxiliary circuit takes in the write data input from outside of the memory circuit (another memory circuit) and transfers it to the sense amplifier circuit 113 or the memory circuit 111 It is configured to have a function of outputting the data read from 0 to the outside, and comparing the read data with the data inputted from outside. The variable address conversion circuit 130 is configured to convert an externally input address signal according to the comparison result in the input / output & comparison circuit 120 and supply the converted address signal to the address decoder 112. I have.

FIG. 13 is a block diagram showing a specific example of the variable address conversion circuit 130 included in the variable logic function circuit of the embodiment of FIG. The variable address conversion circuit 130 includes a circuit substantially similar to the memory circuit 110 and an address increment circuit 135. In other words, the variable address conversion circuit 130 also uses the memory circuit 110 on the wafer and the address increment 135 formed as an auxiliary circuit in the scribe area. Can be configured.

 The variable address conversion circuit 130 has a plurality of memory cells arranged in a matrix, a plurality of lead lines and a plurality of data lines arranged in a lattice, and the memory cells in the same row are various. The memory cells connected to the corresponding row lines and the memory cells in the same column are connected to the corresponding data lines, respectively. An address decoder that sets one corresponding read line in 1 3 1 to the selected level and amplifies the potential read to the data line from the memory cell connected to the selected read line It comprises a sense amplifier circuit 13 3, an address decoder 13 2, a write control circuit 13 4 for controlling the operation timing of the sense amplifier circuit 13 3, and the like. FIG. 14 shows a specific example of the input / output & comparison circuit 120 included in the variable logic function circuit.

 As shown in FIG. 14, the input / output & comparison circuit 120 is connected to the signal line 15 1 connected to the output terminal of the sense amplifier circuit 113 and the data input / output terminal 14 2. Switch means 121 provided between the signal line 152 and the read / write control circuit 114 and controlled by the comparison instruction signal CC supplied from the above-mentioned write / read control circuit 114, and the sense amplifier circuit 133 A NAND gate circuit 122 that receives a read signal and the comparison instruction signal CC supplied from the write / read control circuit 114 as input signals, and an output signal of the NAND gate circuit 122 and the above-mentioned data An exclusive OR gate circuit 123 that receives the signal input from the output terminal 142 as an input, and an OR gate that receives the output signals of a plurality of exclusive OR gate circuits 123 as inputs. And a circuit 124.

That is, a comparison circuit including the switch means 121, the NAND gate circuit 122, and the exclusive OR gate circuit 123 is provided for each data input / output terminal 142, and the comparison circuit of each comparison circuit is provided. Shiv OR The output signal of the gate circuit 123 is input to the OR gate circuit 124, and the output signal of the OR gate circuit 124 is supplied to the variable address conversion circuit 130 as a comparison result signal CM. Have been.

 Next, how to change the conversion address in the self-configurable variable logic function circuit of the above embodiment will be described with reference to the flowchart shown in FIG. Before the flow chart shown in FIG. 15 is started, the variable address conversion circuit 130 performs initial setting processing to store the memory circuit 131 in each address in the memory array 131. The address corresponding to each address of 0 is stored.

 When an address signal is input to the address input terminal 14 1 from the outside, the address decoder 13 2 of the variable address conversion circuit 13 decodes the address signal and the corresponding address in the memory array 13 1 is decoded. The address data stored in advance is output by setting the line to the selected level, that is, the address is converted (step S11). The read address data is amplified by the sense amplifier 33 and supplied to the address decoder 112 of the memory circuit 110. The address decoder 112 decodes the supplied address and sets the corresponding word line in the memory array 111 to the selected level. At that time, the address is input from the outside via the input / output & comparison circuit 120. The stored data is written to the selected memory cell (step S12).

Next, the corresponding write data is read from the memory array 111 (step S13). The read data is amplified by the sense amplifier 113 and supplied to the input / output & comparison circuit 120. At this time, the write data input at the time of data writing is input to the data input / output terminals 14 1. As a result, the input / output & comparison circuit 120 compares the data read from the memory array 111 with the write data input to the data input / output terminal 141, and matches or disagrees. To the variable address conversion circuit 130 address increment 1 3 5 Output.

 Then, the address increment 135 increments the input address signal when the writing has failed based on the comparison result signal CM (step S15). This incremented address is supplied to the address decoder 112 and decoded, and the next read line in the memory array 111 is set to the selected level. Then, returning to step S12, the data input from the outside via the input / output & comparison circuit 120 is written to the selected memory cell connected to the node line. Next, the write data is read again from the memory array 111, and the data input / output from the external device is input to the data input / output terminal 142 by the input / output & comparison circuit 120. Make a comparison. When they match, the overnight write operation for one address is completed. Then, the next address signal is generated and input to the address input terminals 141, and the writing process for the next address is executed.

 As described above, in the variable logic function circuit according to the present embodiment, after writing data, the write data is read and judged, and if there is an error, the address is updated and the data is written to the next address position. ing. As a result, even if there is a defect in the memory array 111, the address is automatically skipped and the data is written to the next address. Therefore, in the self-configurable variable logic function circuit of this embodiment, not only all the memory cells in the memory array 111 need not be normal, but also the It has the advantage of not having to test for bits.

 In FIG. 13, address conversion is directly performed in the memory array 131, but the memory capacity can be reduced by storing the additional amount of address conversion as data.

In the above embodiment, it is determined whether or not the memory array 111 is defective. In the description above, the output signal line of the sense amplifier 13 of the variable address conversion circuit 13 of FIG. 12 is connected to the address decoder 1 1 2 of the memory circuit 1 It is configured so that it can be supplied to the input / output & comparison circuit 120 as well. Then, in the same manner as described above, the normal / abnormal state of the data writing to the memory array 1331 of the variable address conversion circuit 130 is determined, and if abnormal, the address is skipped. This not only does not require all memory cells to be normal for the memory array 131, but also eliminates the need to test the memory array for bad bits in advance.

 FIG. 16 shows the configuration of a part of a wafer on which a plurality of variable logic function circuits of FIG. 12 are arranged.

 In FIG. 16, reference numeral 110 denotes an original memory circuit arranged in a matrix on a single semiconductor chip, and circuits around the original memory circuit are scribed on a wafer. Auxiliary circuits provided in the area, such as wiring and data connecting between each memory circuit, storage 160, switch, matrix 170, etc., and a variable logic function circuit 10 between the memory circuit and the auxiliary circuit. 0 is configured. As shown in the figure, a horizontal wiring area 210 and a vertical wiring area 220 are provided between each memory circuit 110, and a horizontal wiring area 210 and a vertical wiring area 210 are provided. A variable switch circuit 230 that enables signal lines to be selectively coupled is provided at the intersection with the region 220. Further, a variable switch circuit 240 for selectively coupling an address input terminal of the variable logic function circuit 100 to a signal line of the vertical wiring area 220, and a variable switch circuit 240 A variable switch circuit 250 for selectively coupling the data input / output terminal to the signal line of the horizontal wiring area 210 is provided.

In this way, by providing the wiring and the auxiliary circuit for connecting the memory circuits in the scribe area of the wafer, the memory circuit can be tested. A logic circuit having a desired logic function constituting the LPG can be configured according to the HDL description. The variable switch circuits 240 and 250 are also configured by a circuit similar to the switch matrix circuit 170 shown in FIG.

 Note that the data storage 160 does not need to be provided for each memory circuit, and as shown in FIG. 17, one is provided for several (for example, n) memory circuits MEM 1 to MEMn. It is also possible to adopt a configuration in which a signal is fed from the data storage 160 to a switch matrix 170 provided corresponding to a plurality of memory circuits. This reduces the number of storages 160 as a whole wafer and eliminates the need to intentionally widen the scribe area for auxiliary circuits.

 Next, a technique effective in applying the present invention to an actual device will be described. As described above, in the embodiment, it has been described that the wiring and the variable switch circuit are provided in the scribe area in order to configure the AL PG using the memory circuit on the wafer. If the number of function blocks that make up the ALPG increases or the number of function blocks that make up the ALPG increases (when the function blocks are subdivided), the wiring provided in the scribe area with a predetermined width may not be sufficient. Is expected. Thus, the present inventors have studied the provision of a wiring structure used only at the time of testing at the wafer stage.

 FIG. 18 shows an example of such a test wiring structure.

In FIG. 18, reference numeral 300 denotes a semiconductor substrate such as a single crystal silicon wafer, reference numeral 310 denotes a memory forming area in which a memory circuit 110 such as general-purpose SRAM is formed, and reference numeral 320 denotes data storage 160 or a switch mat. The scribe area where auxiliary circuits such as the Rix 170 and the variable switch circuits 230, 240, and 250 are formed, and 330 is above the completed memory circuit 110 340 is a pad connected to a lead terminal or the like by a bonding wire or the like.

 In this embodiment, insulating synthetic resin films 351, 352, 353 such as PIQ (polyimide insulating film) are sequentially formed on the surface of the final protective film 330 by a spin-on method or the like. 35 1, 352, 353 Wiring for connecting between the storage 160 and switch matrix 170 on the surface of 3, 352, 353 3 Wiring for connecting between the variable switch circuits 230, 240, 250 It has a structure in which 2 10 and 220 are formed. Although not particularly limited, in this embodiment, the wiring 360 is the first aluminum layer, the wiring 210 is the second aluminum layer, and the wiring 220 is the third aluminum layer. It is formed. Reference numeral 370 denotes a pad for applying a signal or a power supply voltage to each of the wirings 360, 210, and 220 by the probe 380.

 Further, as shown in FIGS. 19 to 22, in this embodiment, the wirings 360, 210, and 220 are formed above the memory circuit formation region 310. FIG. 19 shows an example of a wiring 360 pattern for connecting between the data storage 160 and the switch / matrix 170, and FIG. 20 shows a vertical wiring 210 for connecting between the variable switch circuits 230, 240 and 250. FIG. 21 shows an example of the pattern of the horizontal wiring 220 for connecting the variable switch circuits 230, 240, and 250, and FIG. 22 shows them collectively. Although not particularly limited, the feedback wiring 360 is formed in a direction of about 45 ° with respect to the wirings 210 and 220 which are orthogonal to each other, whereby the wiring length is shortened and the signal delay is correspondingly reduced. Has also been reduced.

When a PIQ is used, the accuracy of the wiring formed on its surface cannot be so high. However, in this embodiment, an auxiliary circuit for configuring a test AL PG formed in a scribe area is used. For wiring connecting between Since it is only used, high accuracy is not required and low resistance is sufficient, and there is sufficient wiring space since it is separate from the original wiring of the memory circuit. Therefore, in this embodiment, the wiring is formed as a wiring having a width of about 10 to 2 O ^ m. In addition, a pad 370 for applying a signal or a power supply voltage by a probe to each of the wirings 210 and 220 by a test at the time of the test, and the wiring 210 and 220 are formed in the memory circuit forming area 310 Because it is formed above, it can be provided with a margin. The resin films 35 1 to 35 3 and the wirings 360, 210, 220 on the surface thereof may be removed after the completion of the test on the wafer, but may be left.

 In the above embodiment, an example in which a functional circuit is configured by a self-configurable variable logic circuit has been described. However, when a controller for configuring these circuits has a measurement function, verification is performed using the measurement function and appropriate logic configuration is performed. Can be achieved.

 Next, a semiconductor memory inspection method to which the above embodiment is applied and its advantages will be described in comparison with a conventional semiconductor memory inspection method.

Inspection of a conventional semiconductor memory has been performed according to a procedure as shown in FIG. In other words, when the pre-process for forming the memory circuit on the wafer is completed, (1) DC test is performed by applying a DC voltage to the pad of the memory circuit on the wafer with a probe to check whether it has the desired DC voltage characteristics. (2) a defective bit test to determine whether or not there is a defective bit in the memory array; (3) a rescue process for replacing a detected defective bit with a spare memory cell; (2) a second DC test; Function test to check for logical operation, 組 立 Package assembly process, DCDC test in package state, フ ァ ン ク シ ョ ン Function test in package state, ACAC to test circuit characteristics by applying AC signal Tests: バ ー ン Burn-in (equivalent to aging) test to check the reliability of operating the circuit for several to 10 hours by applying high voltage at high temperature, DC DC test at low temperature,フ ァ ン ク シ ョ ン Function test under low temperature 、 AC test at low temperature, DC DC test at high temperature, フ ァ ン ク シ ョ ン function test at high temperature, ⑯ AC test at high temperature. In addition, in the burn-in test described in (1) above, monitoring / run-in was sometimes performed in which test patterns were given and the output signal was monitored to assure higher reliability of the product while monitoring the output signal. However, such a burn-in device is extremely expensive, and the unit price of the product is also high.

 On the other hand, FIG. 24 shows a test procedure in a semiconductor memory to which the above-described embodiment of the present invention is applied, and FIG. 25 shows details of a defective bit test indicated by ② in FIG. ing. In the semiconductor memory according to the embodiment, since the self-test can be performed in the wafer state by configuring the ALPPG on the wafer, the burn-in test can be performed in the wafer state. Thus, for example, by performing a defective bit test of (1) in parallel with a pin-in test using a pin-in device and performing a function test of (2) at room temperature, low temperature, and high temperature, respectively, as shown in FIG. As shown in Fig. 4, it is possible to omit the function test (1), the panning test (2), the function test at low temperature (2), and the function test at high temperature (2) in Fig. 23. However, there is an advantage that the total inspection time can be greatly reduced. In addition, since self-testing by ALPG can be performed at the time of a wafer-in test during a pin-in test, an expensive computer that can perform monitoring and pin-in is unnecessary because conventional monitoring and pin-in is unnecessary. This eliminates the need for one-in-one equipment, and makes it possible to obtain high reliability of products while avoiding cost increases.

Furthermore, in recent years, among semiconductor memory products, there has been a product called KGD (Know Good Die) that is delivered in a chip state that is not assembled into a package at the request of the user. Conventionally, such a product has to be subjected to a burn-in test. Although it was removed from the package after the test after the assembly in the temporary package, the memory to which the present invention was applied burns in the wafer state. Since it is possible to carry out a fin test, it can be shipped as a KGD product after the end of the function test in (1), and this has the advantage of greatly reducing costs.

 Here, the procedure of the faulty bit test of (1) in FIG. 24 will be described with reference to FIG. Note that the function test of (1) in FIG. 24 is performed in the same procedure as that of the defective bit test of FIG. 25, and a duplicate description will be omitted.

 In the failure bit test and function test, the number of products (each memory circuit) on the wafer and the mounting status of the products that failed DC test are first determined based on the results obtained in the DC test (1). (Step S2 1). Next, the settings relating to the product such as the number of addresses of the product to be inspected / the number of bits per night and whether it is SRAM or DRAM are performed (step S22). Then, the logic configuring the ALPG suitable for the product to be inspected is described in HDL or the like (step S23). Then, the description is decoded by a computer or the like to perform logic synthesis, and logic configuration data representing the ALPG at the gate level is obtained (step S24). Next, memory circuits that implement the logic function circuit that constitutes the ALPG are extracted from the wafer and their layout is determined (step S25) o

 Next, it is determined whether the logic function circuit realized on the wafer by the memory circuit is a sequential circuit or a combinational circuit (step S26). Then, in the case of a combinational circuit, logic value data to be written to the memory circuit is created according to the logic function circuit to be realized, and is written into the memory array of the corresponding memory circuit (step S27, step S27). S2 8). Then, it is determined whether the written data is read out and written correctly, and if it is incorrect, the part is removed from the logical configuration as a defective part, and the process returns to step S25 and starts over (step S29). , S30 → S31).

On the other hand, if the circuit is a sequential circuit in the determination in step S26, The circuit is decomposed into combinational circuits, a logical value to be written to the memory circuit is created for each circuit, and the logical value data is written in the memory array of the corresponding memory circuit (steps S32 to S34). Then, the written data is read out to judge whether or not the data can be written correctly. If the data is incorrect, the part is removed from the logic configuration as a defective part, and the process returns to step S25 and starts over (step S35, step S35). S36 → S31). When the read data is correct, the sequential circuit generates control data for switching the switch matrix 170 as an auxiliary circuit so that the next input state can be controlled by the previous output data. Is written in the memory circuit, and when it is read out, the switch matrix 170 is correctly switched via the data storage 160 (steps S37, S38).

 After that, the variable switch circuit arbitrarily connects between the memory circuits.

40, 250, the connection method is determined, and the control information is created. Based on the determined information, the control information is written to the corresponding control information memory of the variable switch circuits 230, 240, 250, and the variable switch circuit 2 is written. The ALPG is configured on the wafer by setting the connection status of 30, 240, and 250 (steps S39,

540). Then, the configured ALPG is activated to generate a test pattern, and writing and reading to and from the memory circuit to be inspected are performed and inspected sequentially (step S41). When the inspection is completed, it is determined whether the inspection has been completed for all the memory circuits on the wafer (step S50). If not, the process returns to step S25, and the inspection is completed. Reconfigure AL PG on wafer using memory circuit. Thereafter, it is determined in step S51 whether burn-in has been completed. If not completed, the flow returns to step S22 to reconfigure the ALPG, and repeats the above processing. finish. The inspection in steps S21 to S50 may be performed only once, but the Burnin test Since it takes a long time, reliability can be improved by repeatedly performing inspections during that time.

 Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it can be said that various modifications can be made without departing from the gist of the invention. Not even. For example, in the embodiment, an ALPG is configured using a memory circuit on a wafer, and a test pattern is written and read to and from another memory circuit using the ALPG, and data read from the memory circuit and Although the comparison of the written data and the comparison to determine whether they match is performed by an external computer, the ALPG having such a comparison and judgment function is implemented using a memory circuit on the wafer. You may make it comprise.

 FIG. 26 shows a procedure for testing a defective bit and a procedure for relieving a bit when an ALPG having a function of comparing and judging is formed on a wafer. The procedure in FIG. 26 is almost the same as the procedure in FIG. The difference is that the comparison and determination circuit determines whether the AL PG configured in step S23 matches the data read from the memory circuit and the written data, and the defective bit that is the determination result. A failure memory for storing the position information of the unit, and an inspection process by the ALPG (step S41), followed by a process of judging the presence or absence of a defect (step S42). This is the point at which the processing (steps S43 and S44) for deleting the memory circuit from the list of memory circuits composing the ALPG is stored.

Further, when each memory circuit includes a redundant circuit having a spare memory column, a spare memory row, and an address conversion circuit, a comparison judgment is made by comparing data read from the memory circuit with written data. A functional ALPG is configured using the memory circuit on the wafer, and based on the judgment result obtained by the ALPG inspection, It is also possible to configure a rescue circuit (a circuit having a redundancy replacement algorithm) that replaces the data with a spare memory cell by using the memory circuit on the wafer and automatically perform the bit rescue. Since the redundant replacement algorithm itself is known, it may be used.

 FIG. 27 shows a procedure for inspecting a semiconductor memory on a wafer provided with a bit rescue function. In the memory inspection of this embodiment, the ALPPG is formed on the wafer and the self-test can be performed in the wafer state, so that the pin-in test can be performed in the wafer state. In addition, since it has a bit rescue function, after the defective bit test is completed, the bit rescue process is continuously performed based on the test result.

 Thus, for example, by performing the defective bit test of (1) in parallel with the burn-in test using a burn-in device and performing the function test of (4) at room temperature, low temperature, and high temperature, respectively, as shown in FIG. As shown in Fig. 23, the remedy process in (3), the function test in (2), the thermal test in (4), the function test in low temperature, and the function test in high temperature in (2) are omitted. This has the advantage that the total inspection time can be greatly reduced.

FIG. 28 shows the detailed procedure of the defective bit test & remedy process in FIG. 27. The procedure in Figure 28 is almost the same as the bad bit test procedure in Figure 25. The difference is that the ALPG configured in step S23 compares the data read from the memory circuit with the data written, and determines whether or not they match, and the defective bit that is the determination result. ALPG that includes a fail memory that stores the position information of a fault, a rescue algorithm that determines whether the detected defective bit can be rescued by a redundant circuit in each memory circuit, and performs the rescue. Inspection processing (step S41) following the inspection processing (step S41), and processing for determining whether a defect can be remedied when a defect is found (step S41) 5), the process of storing in the fail memory when it cannot be repaired and deleting the memory circuit from the list of memory circuits constituting the ALPG (Steps S43 and S44). The point is that a rescue process (steps S46 and S47), which is sometimes performed by activating the rescue algorithm, is included.

 By the way, in the above-described embodiment, the case where the ALPG is configured at the wafer level and the memory circuit is tested with the ALPG has been described. However, recent general-purpose semiconductor memories each include a plurality of address decoders and sense amplifiers. It consists of memory mats, and each of the memory mats can be regarded as the memory circuits MEM1 to MEMn in FIG. That is, in one semiconductor memory, an ALPG can be configured with a plurality of memory mats in the same manner as in the above-described embodiment, and the test can be performed by the chip itself. In this case, since the present invention cannot be carried out using the conventional semiconductor memory as it is, a storage device 160 and a switch matrix 170 as shown in FIG. 17 are provided in the memory chip. You can do it.

 Furthermore, in the above embodiment, an ALPG is formed on a wafer on which a plurality of semiconductor memories are formed, and an auxiliary circuit for enabling self-test is provided to enable aging test in a wafer state. Although the embodiment has been described, the present invention is not limited to a wafer. In other words, in the past, in the pinning (aging) test, a plurality of memories to be inspected are mounted on a board called an aging board, but the self-test is performed by configuring an ALPG. A self-test is performed by making the auxiliary circuit that enables it into a semiconductor integrated circuit and mounting it on the aging board together with the memory under test and configuring the ALPG with this auxiliary circuit and part of the memory under test. It can also be done.

Figure 29 shows the configuration of a test circuit (ALPG) on the aging board. An example in the case of forming is shown. In FIG. 29, MEM is a memory to be inspected, and SW-MUX is a semiconductor integrated circuit corresponding to the switch matrix 170 and the variable switch circuits 230, 240, and 250 as auxiliary circuits in the embodiment of FIG. In FIG. 29, the data storage 160 as the auxiliary circuit in the embodiment of FIG. 16 is configured using the memory MEM to be inspected. A configuration including the switch matrix 170 and the data-storage 160 may be configured as a single semiconductor integrated circuit, and may be mounted on an aging board together with the memory to be tested to form an AL PG. .

 FIG. 30 shows an inspection procedure when an ALPG is configured using the memory to be inspected mounted on the aging board and the remaining memory is inspected. In the memory test of this embodiment, since the self-test can be performed during the burn-in test by configuring the ALPG on the aging board, the self-test is performed at room temperature and low temperature in addition to the high temperature using the burn-in device. As a result, as shown in Fig. 30, the relief processing in (3), the function test in (2), the function test in low temperature in (2), and the function test in high temperature in (2) in Fig. 23 are omitted. This has the advantage that the total inspection time can be greatly reduced.

 FIG. 31 shows the detailed procedure of the burn-in test (1) in FIG.

In the burn-in test on the aging port, first, the mounting status such as the number of products (each memory circuit) mounted on the board is grasped (step S61). Next, settings relating to the product such as the number of addresses and the number of data bits of the product to be inspected are made (step S62). Then, for example, an ALPG is constructed using the memory circuit on the left half of the board (step S63). The configuration of this ALP G is shown in steps 324 to 34 in FIG. The explanation is omitted because it is performed by logic synthesis according to the same procedure as 0.

 Next, an ALPG composed of the memory circuits on the left half of the aging board is activated to generate a test pattern, and writing to and reading from the right half memory circuits on the port under test is performed. Inspection (step S64). When the inspection is completed, it is determined whether all the memory circuits on the right side are normal (step S65). If not, the defective product is stored and the defective product is stored in the product list on the board. Delete (Steps S66, S67) o

 Thereafter, the settings for the right half of the product on the board are made (step S688). Then, an ALPG is constructed using the memory circuit on the right half of the board (step S69). This configuration of ALPG is also performed by logic synthesis according to the same procedure as steps S24 to S40 in FIG. Next, ALPG composed of the memory circuit on the right half of the aging board is activated to generate a test pattern, and writing and reading to and from the memory circuit on the left half of the board to be inspected are performed. Inspection is performed sequentially (step S70). When the inspection is completed, it is determined whether all the memory circuits on the right side are normal (Step S71). If not, the defective product is stored, and the defective product is listed on the board. (Steps S72 and S73). Thereafter, in step S74, it is determined whether or not the aging has been completed, and a series of processing ends. Industrial applicability

 In the above description, the invention made by the present inventor has been mainly described by taking as an example the inspection of a semiconductor memory, which is a field of application as a background, but this invention is not limited to this. It can also be used for inspection on a wafer.

Claims

 The scope of the claims

1. A connection means capable of arbitrarily connecting the memory circuits is provided on a semiconductor wafer or a printed circuit board on which a plurality of memory circuits are mounted, and a memory is used in accordance with a predetermined algorithm by using a part of the plurality of memory circuits. A test circuit for generating a signal for testing the circuit and reading the written data is constructed, and the test circuit is used to test other memory circuits that do not constitute the test circuit on the wafer or the printed board. A method for inspecting a semiconductor memory, wherein the method is performed.

2. Describe the test circuit configured on the wafer or printed circuit board in HDL language, decode the HDL description, perform logical configuration, and connect to the memory circuit on the wafer or printed circuit board. 2. The semiconductor memory inspection method according to claim 1, wherein an inspection circuit is formed on a wafer or a print substrate by performing writing and connection setting of the connection means.

3. As the connection means, a plurality of wirings formed vertically and horizontally on the surface of the wafer or the printed board via an insulating film, and a plurality of wirings provided in a scribe area of the wafer or a wiring area of the printed board. 3. The method for testing a semiconductor memory according to claim 1, wherein a variable switch circuit capable of conducting between arbitrary wirings is provided at the intersection. An auxiliary circuit for configuring the inspection circuit is provided in the scribe area or the wiring area, and the inspection circuit is configured by connecting the auxiliary circuit to a memory circuit on the wafer or printed circuit board. thing 4. The method according to claim 1, wherein the semiconductor memory is inspected.

5. The method for testing a semiconductor memory according to claim 1, wherein a signal holding circuit for holding a signal output from the memory circuit is provided as the auxiliary circuit.

6. As the auxiliary circuit, comparing means for comparing the data written in the memory circuit with the data read from the storage means, and comparing the address signal supplied to the memory circuit with the comparison result in the comparing means. Claims 1, 2, 3, and 4 in which variable address conversion means for performing conversion based on the above are included so as to have a self-test function for performing a logic test for the presence or absence of a defect in the memory circuit. Or the inspection method of semiconductor memory described in 5.

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7. If the memory circuit includes a spare memory cell and a redundant circuit for replacing a defective bit with the spare memory cell, a predetermined circuit is used by using the memory circuit on the wafer or printed circuit board. A rescue circuit for replacing a defective bit of the memory circuit with a spare memory cell in accordance with the algorithm, and performing a relief process for replacing the defective bit detected by the test circuit with the spare memory cell. The semiconductor memory inspection method according to claim 1, 2, 3, 4, 5, or 6.

8. A connection means capable of arbitrarily connecting the above-mentioned memory mats is provided on a chip of the semiconductor memory in which the memory array is composed of a plurality of memory mats, and a part of the plurality of memory mats is used. A test circuit for generating a signal for a memory mat test according to a predetermined algorithm and reading the written data is constituted, and the test circuit detects the chip by the test circuit. A method for inspecting a semiconductor memory, wherein an inspection of another memory mat that does not constitute an inspection circuit is performed.

9. A semiconductor device comprising a semiconductor wafer on which a plurality of memory circuits are mounted, the semiconductor device comprising a connection means capable of arbitrarily connecting the memory circuits.

10. A semiconductor device having a memory circuit comprising: a memory array having a plurality of memory cells; and an address decoder for decoding an address signal and selecting a memory cell in the memory array.

 The semiconductor device according to claim 1, wherein the address decoder comprises a switching means for switching an input state at an input terminal of the address decoder, and the switching means is capable of decoding a predetermined address unit.

11. A semiconductor device in which a memory array is composed of a plurality of memory mats, wherein a connection means for arbitrarily connecting the memory mats is provided on a chip serving as a base thereof. apparatus.